CN115513281A - Insulated gate bipolar transistor - Google Patents
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- CN115513281A CN115513281A CN202211473471.5A CN202211473471A CN115513281A CN 115513281 A CN115513281 A CN 115513281A CN 202211473471 A CN202211473471 A CN 202211473471A CN 115513281 A CN115513281 A CN 115513281A
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 175
- 229920005591 polysilicon Polymers 0.000 claims abstract description 151
- 239000012535 impurity Substances 0.000 claims description 20
- 239000002994 raw material Substances 0.000 claims description 19
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 9
- 229910052698 phosphorus Inorganic materials 0.000 claims description 9
- 239000011574 phosphorus Substances 0.000 claims description 9
- 238000003466 welding Methods 0.000 claims description 3
- 239000002019 doping agent Substances 0.000 claims 3
- 238000004519 manufacturing process Methods 0.000 abstract description 15
- 239000002184 metal Substances 0.000 abstract description 10
- 238000000034 method Methods 0.000 description 14
- 238000005530 etching Methods 0.000 description 7
- 238000005137 deposition process Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000003814 drug Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
The application discloses an insulated gate bipolar transistor which comprises a gate bus, a built-in resistor area and a gate lead bonding area, wherein the built-in resistor area comprises at least one built-in resistor island, the built-in resistor island comprises first polycrystalline silicon, second polycrystalline silicon and third polycrystalline silicon, the first polycrystalline silicon is respectively connected with one end of the second polycrystalline silicon and one end of the third polycrystalline silicon, and the other end of the second polycrystalline silicon is connected with the gate bus; the grid lead bonding area is connected with the other end of the third polysilicon. The number of the built-in resistor islands in the built-in resistor area can be adjusted, so that the grid built-in resistor of the insulated gate bipolar transistor can be flexibly adjusted, a polycrystalline silicon layer and a metal layer do not need to be designed again, the tape-out manufacturing does not need to be carried out again, and the manufacturing cost and the time cost are further saved.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to an insulated gate bipolar transistor.
Background
An Insulated Gate Bipolar Transistor (IGBT) is a new power electronic device in which a MOS field effect Transistor and a Bipolar Transistor are combined. The power transistor has the advantages of easy driving and simple control of the MOSFET, has the advantages of reduced on-state voltage of the power transistor, large on-state current and small loss, becomes one of core electronic components in a modern power electronic circuit, and is widely applied to various fields of national economy such as communication, energy, traffic, industry, medicine, household appliances, aerospace and the like. The application of the IGBT plays an extremely important role in improving the performance of a power electronic system.
Some current IGBTs with specific requirements need a built-in gate resistor, and the resistor needs to be customized according to application requirements. In an actual IGBT chip, due to the deviation between simulation and reality, the gate built-in resistance is usually adjusted many times, and a satisfactory gate built-in resistance can be obtained. At present, the mainstream technology is to introduce a gate built-in resistor by designing a polysilicon layer and a metal layer. Therefore, if the resistance of the gate built-in resistor is adjusted, the polysilicon layer and the metal layer need to be redesigned, that is, the tape-out process needs to be performed again.
Disclosure of Invention
The embodiment of the application provides an insulated gate bipolar transistor, and the built-in resistance of a grid electrode can be adjusted without re-performing tape-out manufacturing.
An embodiment of the present application provides an insulated gate bipolar transistor, including:
a gate bus line;
the embedded resistor area comprises at least one embedded resistor island, the embedded resistor island comprises first polycrystalline silicon, second polycrystalline silicon and third polycrystalline silicon, the first polycrystalline silicon is respectively connected with one end of the second polycrystalline silicon and one end of the third polycrystalline silicon, and the other end of the second polycrystalline silicon is connected with the grid bus;
and the grid lead pressure welding area is connected with the other end of the third polysilicon.
In the insulated gate bipolar transistor provided in the embodiment of the present application, the resistivity of the second polysilicon and the resistivity of the third polysilicon are both smaller than the resistivity of the first polysilicon.
In the insulated gate bipolar transistor provided in the embodiment of the present application, the first polysilicon has a first grain size and a first raw material concentration, and the second polysilicon and the third polysilicon both have a second grain size and a second raw material concentration.
In the insulated gate bipolar transistor provided in the embodiment of the present application, when the first grain size is equal to the second grain size, the first raw material concentration is greater than the second raw material concentration.
In the insulated gate bipolar transistor provided in the embodiment of the present application, when the first raw material concentration is equal to the second raw material concentration, the first grain size is smaller than the second grain size.
In the insulated gate bipolar transistor provided by the embodiment of the application, the square resistance of the first polysilicon is 5 Ω/sq-20 Ω/sq.
In the insulated gate bipolar transistor provided by the embodiment of the application, the square resistances of the second polysilicon and the third polysilicon are both 0.1 Ω/sq-1 Ω/sq.
In the insulated gate bipolar transistor provided in the embodiment of the present application, the doping impurity in the first polysilicon is phosphorus, and the doping concentration of the doping impurity is 1e19 -3 ~1e20cm -3 。
In the insulated gate bipolar transistor provided in the embodiment of the present application, the doping impurities in the second polysilicon and the third polysilicon are both phosphorus, and the doping concentration of the doping impurities is 1e20cm -3 ~1e21cm -3 。
In the insulated gate bipolar transistor provided by the embodiment of the application, the thickness of the first polysilicon is 0.2-2 μm.
In summary, the insulated gate bipolar transistor provided by the embodiment of the present application includes a gate bus, a built-in resistor area, and a gate lead bonding area, where the built-in resistor area includes at least one built-in resistor island, the built-in resistor island includes first polysilicon, second polysilicon, and third polysilicon, the first polysilicon is connected to one end of the second polysilicon and one end of the third polysilicon, respectively, and the other end of the second polysilicon is connected to the gate bus; and the grid lead press welding area is connected with the other end of the third polysilicon. According to the scheme, the number of the built-in resistor islands in the built-in resistor area can be adjusted, and/or the thickness of the first polycrystalline silicon is adjusted through an etching process or a deposition process, so that the grid built-in resistor of the insulated gate bipolar transistor is flexibly adjusted, the polycrystalline silicon layer and the metal layer are not required to be designed again, the tape-out manufacturing is also not required to be carried out again, and the manufacturing cost and the time cost are further saved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic view of a first structure of an insulated gate bipolar transistor according to an embodiment of the present application.
Fig. 2 is a schematic diagram of a second structure of an insulated gate bipolar transistor according to an embodiment of the present application.
Fig. 3 is a schematic diagram of a third structure of an insulated gate bipolar transistor according to an embodiment of the present application.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the recitation of a claim "comprising a" 8230a "\8230means" does not exclude the presence of additional identical elements in the process, method, article or apparatus in which the element is incorporated, and further, similarly named components, features, elements in different embodiments of the application may have the same meaning or may have different meanings, the specific meaning of which should be determined by its interpretation in the specific embodiment or by further combination with the context of the specific embodiment.
It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
In the following description, suffixes such as "module", "component", or "unit" used to denote elements are used only for the convenience of description of the present application, and have no specific meaning in themselves. Thus, "module", "component" or "unit" may be used mixedly.
In the description of the present application, it should be noted that the terms "upper", "lower", "left", "right", "inner", "outer", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a specific orientation, be configured and operated in a specific orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
The technical solution shown in the present application will be described in detail by specific examples. It should be noted that the description sequence of the following embodiments is not intended to limit the priority sequence of the embodiments.
Some current IGBTs with specific requirements need a built-in gate resistor, and the resistor needs to be customized according to application requirements. In an actual IGBT chip, due to the deviation between simulation and reality, the gate built-in resistance is usually adjusted many times, and a satisfactory gate built-in resistance can be obtained. At present, the mainstream technology is to introduce a gate built-in resistor by designing a polysilicon layer and a metal layer. Therefore, if the resistance of the gate built-in resistor is adjusted, the polysilicon layer and the metal layer need to be redesigned, that is, the tape-out process needs to be performed again.
Based on this, the embodiment of the application provides an insulated gate bipolar transistor. As shown in fig. 1, fig. 1 is a schematic structural diagram of an insulated gate bipolar transistor according to an embodiment of the present disclosure, where the insulated gate bipolar transistor may include a gate bus line 10, a built-in resistor region 20, and a gate lead bonding region 30.
The gate bus lines 10 are made of polysilicon. The gate bus line 10 is connected to the gates of thousands of cells in the active area to provide overall transmission of gate control signals to the individual cells.
Wherein the built-in resistive region comprises at least one built-in resistive island 21. The built-in resistor island 21 includes a first polysilicon 211, a second polysilicon 212, and a third polysilicon 213, the first polysilicon 211 is connected to one end of the second polysilicon 212 and one end of the third polysilicon 213, respectively, and the other end of the second polysilicon 212 is connected to the gate bus line 10.
Wherein the gate wire bonding area 30 is connected to the other end of the third polysilicon 213. The gate wire bond pad 30 is comprised of a polysilicon material.
Generally, when a power device is manufactured, a certain amount of impurities are doped in a polysilicon material, so that the polysilicon material has a certain resistance. Therefore, the first polysilicon 211, the second polysilicon 212, and the third polysilicon 213 each have a resistance.
Therefore, in this embodiment, the number of the internal resistor islands 21 in the internal resistor area 20 can be adjusted, so as to flexibly adjust the gate internal resistor of the igbt without redesigning the polysilicon layer and the metal layer, i.e., without re-performing tape-out manufacturing, thereby saving the manufacturing cost and time cost.
For example, when the resistance of each of the internal resistance islands 21 is 10 Ω and the number thereof is 1, the gate internal resistance at this time is 10 Ω. When the resistance of each of the internal resistance islands 21 is 10 Ω and the number thereof is 2, the gate internal resistance at this time is 5 Ω. When the number of the resistors 10 Ω of each of the internal resistor islands 21 is 3, the gate internal resistor is about 3.3 Ω at this time.
In the embodiment of the present application, the doping impurity in the first polysilicon 211 is phosphorus, and the doping concentration of the doping impurity is 1e19 -3 ~1e20cm -3 . The doping impurities in the second polysilicon 212 are all phosphorus, and the doping concentration of the doping impurities is 1e20cm -3 ~1e21cm -3 . The doping impurities in the third polysilicon 213 are all phosphorus, and the doping concentration of the doping impurities is 1e20cm -3 ~1e21cm -3 。
The doping concentrations of the doping impurities in the second polysilicon 212 and the third polysilicon 213 may be the same or different, and may be set according to actual conditions.
It should be noted that the doping impurities in the second polysilicon 212 and the third polysilicon 213 include, but are not limited to, phosphorus. The doping impurities in the second polysilicon 212 and the third polysilicon 213 may also include other doping impurities other than phosphorus. For example, the doping impurities in the second polysilicon 212 and the third polysilicon 213 may also be boron.
It is understood that the built-in resistance region needs to have at least one built-in resistance island 21 in order that the gate electric signal can be transmitted to the gate bus line 10. In the embodiment of the present application, the number of the built-in resistor islands 21 may be 1 to 5.
In the present embodiment, the first polysilicon 211 is used to form the gate built-in resistor, and the second polysilicon 212 and the third polysilicon 213 are used to conduct current. In order to facilitate the first polysilicon 211 to form a gate built-in resistor and the second polysilicon 212 and the third polysilicon 213 to conduct current, in the embodiment of the present application, the resistivity of the second polysilicon 212 and the third polysilicon 213 are both smaller than the resistivity of the first polysilicon 211.
In some embodiments, the resistivity of the first, second, and third polysilicon 211, 212, 213 may be adjusted by adjusting the grain size and/or raw material concentration of the first, second, and third polysilicon 211, 212, 213.
In some embodiments, the first polysilicon 211 may be predetermined to have a first grain size and a first raw material concentration, and the second polysilicon 212 and the third polysilicon 213 may each have a second grain size and a second raw material concentration.
At this time, in order to make the resistivity of both the second polysilicon 212 and the third polysilicon 213 smaller than the resistivity of the first polysilicon 211. In some embodiments, the following may be specific:
when the first grain size is equal to the second grain size, the first raw material concentration is greater than the second raw material concentration. When the first raw material concentration is equal to the second raw material concentration, the first grain size is smaller than the second grain size.
It should be noted that there are various ways to adjust the resistivity of the first polysilicon 211, the second polysilicon 212, and the third polysilicon 213, including but not limited to the above ways.
In some embodiments, the second polysilicon 212 and the third polysilicon 213 may be directly connected to the first polysilicon 211.
In another embodiment, the second polysilicon 212 and the first polysilicon 211 may be connected to each other through contact holes.
Specifically, a dielectric layer may be disposed between the first polysilicon 211 and the second polysilicon 212, so that the first polysilicon 211 and the second polysilicon 212. However, a contact hole through which the second polysilicon 212 and the first polysilicon 211 are connected may be provided on the dielectric layer.
It is understood that resistivity is proportional to resistance. In unit area, the higher the resistivity, the higher the resistance; the lower the resistivity, the lower the resistance.
In the embodiment of the present application, the resistance of the second polysilicon 212 and the third polysilicon 213 are both smaller than the resistance of the first polysilicon 211. The resistance of the second polysilicon 212 and the third polysilicon 213 are both less than 1 Ω.
In some embodiments, in order to make the resistance of the second polysilicon 212 and the third polysilicon 213 much smaller than that of the first polysilicon 211, the sizes of the second polysilicon 212 and the third polysilicon 213 may be set to be smaller than that of the first polysilicon 211.
It is understood that the size of the second polysilicon 212 may be the same as the size of the third polysilicon 213, or may be different from the size of the third polysilicon 213, and may be set according to actual situations.
In the embodiment of the present application, the aspect ratio of the first polysilicon 211 may be 1. In this embodiment, each first polysilicon 211 may have a different length to width ratio, so that each first polysilicon 211 has a different single resistance, which is beneficial to flexibly adjusting the gate built-in resistance.
The resistance of the second polysilicon 212 and the third polysilicon 213 is negligible small. Therefore, the resistance of the internal resistance island 21 can be adjusted by adjusting the aspect ratio of the first polysilicon layer 211, and the gate internal resistance of the igbt can be adjusted.
For example, when the aspect ratio of the first polysilicon 211 is 2. For another example, when the aspect ratio of the first polysilicon 211 is 3.
In the embodiment of the present application, the sheet resistance of the first polysilicon layer 211 is 5 Ω/sq to 20 Ω/sq. The second polysilicon 212 has a square resistance of 0.1 Ω/sq to 1 Ω/sq. The sheet resistance of the third polysilicon 213 is 0.1 Ω/sq to 1 Ω/sq.
It is understood that the square resistance of the second polysilicon 212 may be the same as the square resistance of the third polysilicon 213, or may be different from the square resistance of the third polysilicon 213, and may be set according to actual situations.
It should be noted that Ω/sq is the unit of square resistance, i.e. ohm/square.
In some embodiments, the resistance of the embedded resistance island 21 can be adjusted by adjusting the thickness of the first polysilicon 211 and adjusting the resistance of the first polysilicon 211, and thus the gate embedded resistance of the igbt can be adjusted. For example, the number of the preset built-in resistor islands 21 is 1, and the resistance of the first polysilicon 211 with the thickness t is 10 Ω. At this time, when the thickness of the first polysilicon layer 211 is t/2, the resistance of the internal resistance island 21 is 20 Ω. When the thickness of the first polysilicon layer 211 is t/3, the resistance of the built-in resistive island 21 is 30 Ω.
In the embodiment of the present application, the thickness of the first polysilicon layer 211 is 0.2 μm to 2 μm. In a specific implementation, the thickness of the first polysilicon 211 may be adjusted through an etching process or a deposition process. For example, the thickness of the first polysilicon 211 may be reduced by an etching process, or the thickness of the first polysilicon 211 may be increased by a deposition process.
In some embodiments, the igbt may further include package bond wires 34 and bond pads 40, as shown in fig. 2. Bond pad 40 is connected to gate lead bond area 30 by package bond 34 so that electrical signals applied externally to the gate are routed into the interior of the igbt.
In some embodiments, to facilitate the connection of package wire 34 to gate wire bond 30, a metal bond 50 may be disposed on gate wire bond 30 as shown in fig. 3.
The embodiment also provides a manufacturing method of the insulated gate bipolar transistor, and the manufacturing method of the insulated gate bipolar transistor may include the following steps: providing a semiconductor substrate, and manufacturing a field oxide and a terminal ring; step two, forming an active region; step three, forming and etching a first polysilicon layer to form first polysilicon; step four, forming and etching the second polysilicon layer so as to form second polysilicon and third polysilicon; step five, forming a contact hole by etching; step six, forming a metal layer and photoetching; and step seven, forming a passivation layer and carrying out back process.
It should be noted that, the above is a general manufacturing process of the igbt, and the specific manufacturing process of the igbt is the same as the manufacturing method of the conventional igbt, and is not described herein again.
In summary, the igbt provided in the embodiment of the present application may include a gate bus 10, an internal resistance region 20, and a gate wire bonding region 30, where the internal resistance region includes at least one internal resistance island 21, the internal resistance island 21 includes first polysilicon 211, second polysilicon 212, and third polysilicon 213, the first polysilicon 211 is connected to one end of the second polysilicon 212 and one end of the third polysilicon 213, respectively, and the other end of the second polysilicon 212 is connected to the gate bus 10; the gate wire bonding area 30 is connected to the other end of the third polysilicon 213. According to the scheme, the number of the built-in resistor islands 21 in the built-in resistor area 20 can be adjusted, and/or the thickness of the first polysilicon 211 is adjusted through an etching process or a deposition process, so that the gate built-in resistor of the insulated gate bipolar transistor can be flexibly adjusted, the polysilicon layer and the metal layer do not need to be designed again, the tape-out manufacturing does not need to be carried out again, and the manufacturing cost and the time cost are further saved.
The insulated gate bipolar transistor provided by the present application is described in detail above, and the principle and the implementation of the present application are explained in the present application by applying specific examples, and the description of the above examples is only used to help understand the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manner and the application scope may be changed, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. An insulated gate bipolar transistor, comprising:
a gate bus line;
the embedded resistor area comprises at least one embedded resistor island, the embedded resistor island comprises first polycrystalline silicon, second polycrystalline silicon and third polycrystalline silicon, the first polycrystalline silicon is respectively connected with one end of the second polycrystalline silicon and one end of the third polycrystalline silicon, and the other end of the second polycrystalline silicon is connected with the grid bus;
and the grid lead pressure welding area is connected with the other end of the third polysilicon.
2. The insulated gate bipolar transistor of claim 1 wherein the resistivity of each of the second polysilicon and the third polysilicon is less than the resistivity of the first polysilicon.
3. The insulated gate bipolar transistor of claim 2, wherein the first polysilicon has a first grain size and a first raw material concentration, and the second polysilicon and the third polysilicon each have a second grain size and a second raw material concentration.
4. The insulated gate bipolar transistor of claim 3, wherein the first raw material concentration is greater than the second raw material concentration when the first grain size is equal to the second grain size.
5. The insulated gate bipolar transistor of claim 3, wherein the first grain size is smaller than the second grain size when the first raw material concentration is equal to the second raw material concentration.
6. The insulated gate bipolar transistor of any of claims 1-5, wherein the first polysilicon has a sheet resistance of 5 Ω/sq to 20 Ω/sq.
7. The insulated gate bipolar transistor according to any one of claims 1 to 5, wherein the sheet resistance of the second polysilicon and the third polysilicon are each 0.1 Ω/sq to 1 Ω/sq.
8. The insulated gate bipolar transistor according to any one of claims 1 to 5, wherein the dopant impurity in the first polysilicon is phosphorus, and the dopant impurity has a dopant concentration of 1e19 -3 ~1e20cm -3 。
9. The insulated gate bipolar transistor according to any one of claims 1 to 5, wherein the doping impurities in the second polysilicon and the third polysilicon are both phosphorus, and the doping concentration of the doping impurities is 1e20cm -3 ~1e21cm -3 。
10. The insulated gate bipolar transistor according to any one of claims 1 to 5, wherein the first polysilicon has a thickness of 0.2 μm to 2 μm.
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| CN110945662A (en) * | 2017-05-18 | 2020-03-31 | 通用电气公司 | Integrated gate resistor for semiconductor power conversion device |
| CN110164966A (en) * | 2018-02-14 | 2019-08-23 | 富士电机株式会社 | Semiconductor device |
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