CN115499104B - Communication method between chip die - Google Patents
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- CN115499104B CN115499104B CN202211298483.9A CN202211298483A CN115499104B CN 115499104 B CN115499104 B CN 115499104B CN 202211298483 A CN202211298483 A CN 202211298483A CN 115499104 B CN115499104 B CN 115499104B
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- 238000000034 method Methods 0.000 title claims abstract description 43
- 238000004891 communication Methods 0.000 title claims abstract description 17
- 230000005540 biological transmission Effects 0.000 claims abstract description 153
- 238000012546 transfer Methods 0.000 claims abstract description 59
- 238000001514 detection method Methods 0.000 claims abstract description 18
- 238000012790 confirmation Methods 0.000 claims description 8
- 238000012937 correction Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 11
- 235000015429 Mirabilis expansa Nutrition 0.000 description 5
- 244000294411 Mirabilis expansa Species 0.000 description 5
- 235000013536 miso Nutrition 0.000 description 5
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0006—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format
- H04L1/0007—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format by modifying the frame length
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
- H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40169—Flexible bus arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/22—Parsing or analysis of headers
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Quality & Reliability (AREA)
- Computer Security & Cryptography (AREA)
- Communication Control (AREA)
Abstract
The invention discloses a communication method between chips die, which comprises the following steps: a write transfer method and a read transfer method; the writing transmission method comprises writing transmission packets from a main die to a secondary die and from the die to the main die, and the step of writing the transmission packets comprises the following steps: write control, write address, transfer byte control, write data, write transfer packet error detection code and transfer acknowledgement; the reading transmission method comprises reading control, address reading, transmission byte control, reading data and reading transmission packet error detection codes. The invention realizes the dynamic data transmission, can support the transmission of different data lengths, selects the writing transmission byte according to the byte number to be written, selects the reading transmission byte according to the byte number to be read, and reduces the transmission time.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a communication method between chips die.
Background
In chip design, many chips are designed to be dual die or multi die, and referring to fig. 1, the AFE die and the MCU die are connected via a serial bus (such as SPI or I2C protocol), and the MCU die sends read and write requests via the serial bus and reads the register configuration and status and data in the AFE die.
The general technology in the field has the following problems:
(1) At present, a general bus does not have relevant measures for protecting and improving reliability, and cannot know whether the current operation is correctly transmitted or not after the transmission is finished, for example, if a bit has a transmission error in the write transmission process, an AFE die cannot identify the transmission error, which may cause wrong configuration; the MCU die can not identify transmission errors and can not carry out retransmission; if a bit has a transmission error in the reading operation process, the MCU die cannot identify the transmission error, and can possibly read the error result and cannot correct the error bit when the bit has the transmission error;
(2) The prior art does not map the AFE into the address space of the MCU, so that efficient reading and writing are ensured; assuming that the read and write in the AFE are transmitted according to 8 bits, a 32-bit output transmission can be completed only by transmitting the address and control signal for many times; assuming that both reading and writing in the AFE transmit according to 32 bits, the prior art cannot meet the requirements of people at the present stage if only a certain bit of the configuration register is modified and the 32-bit data transmission time is occupied.
Based on the current situation, the improvement of the prior art is urgently needed.
Disclosure of Invention
The present invention is directed to a method for communication between chips die, so as to solve the problems in the background art.
The invention provides a communication method between chips die, which comprises the following steps: a write transfer method and a read transfer method; wherein,
the write transmission method needs to write the write transmission packets from the main die to the slave die and from the slave die to the main die;
the step of writing the transmission packet comprises the following steps: write control, write address, transfer byte control, write data, write transfer packet error detection code and transfer acknowledgement; wherein the write control is used for indicating that the current packet is write transmission; the write address is used for writing the address of the transmission packet; the transmission byte control is used for indicating the number of data bytes in the current packet; the write data is used for writing data into the transmission packet; the write transmission packet error detection code is used for detecting the transmission error and error correction of the write transmission packet; the transmission acknowledgement is used to confirm that the bit has been correctly transmitted by the transmission from the die to the master die.
In the reading transmission method, reading transmission packets from a main die to a secondary die and from the secondary die to the main die are required;
the step of reading the transmission packet comprises: reading control, address reading, transmission byte control, data reading and transmission packet error detection code reading; wherein,
the read control is used for indicating that the current packet is read transmission; the reading address is used for reading the address of the transmission packet; the transmission byte control is used for indicating the number of data bytes in the current packet; the read data is used for reading data in the transmission packet; and the read transmission packet error detection code is used for detecting the transmission error and correcting the error of the read transmission packet.
The invention has the following beneficial effects:
(1) The correctness of communication transmission between the master die and the slave die is ensured, error correction or data discarding can be realized after a write transmission error is detected, and retransmission is carried out through the master die; and error correction can be realized after a read transmission error is detected, or read data is discarded and re-read is carried out.
(2) The dynamic data transmission is realized, the transmission with different data lengths can be supported, the write transmission bytes are selected according to the number of bytes needing to be written, the read transmission bytes are selected according to the number of bytes needing to be read, and the transmission time is reduced.
Drawings
FIG. 1 is a schematic diagram of a prior art chip die of the present invention;
FIG. 2 is a schematic diagram of a write transfer method according to the present invention;
FIG. 3 is a schematic diagram of a read transfer method according to the present invention;
FIG. 4 is a timing diagram of a byte read transfer protocol according to the present invention;
FIG. 5 is a timing diagram of a byte write transfer protocol according to the present invention;
FIG. 6 is a timing diagram of a nibble read transfer protocol according to the present invention;
FIG. 7 is a timing diagram of a nibble write transfer protocol according to the present invention;
FIG. 8 is a timing diagram of a word read transfer protocol according to the present invention;
FIG. 9 is a timing diagram of a WRITE TRANSFER protocol in accordance with the present invention;
FIG. 10 is a timing diagram of a double word read transfer protocol according to the present invention;
FIG. 11 is a timing diagram of a double word write transfer protocol according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the invention without making any creative effort, shall fall within the protection scope of the invention.
The invention provides a communication method between chip die, which comprises the following steps: a write transfer method and a read transfer method; wherein,
referring to fig. 2, the present invention discloses an embodiment of a read transmission method, in which a write transmission packet from a master die to a slave die and from the slave die to the master die needs to be written first; the position of the control bit in the transmission packet in fig. 2 is not limited to the position in the above figure, and the step of writing the transmission packet includes: write control, write address, transfer byte control, write data, write transfer packet error detection code and transfer acknowledgement; wherein,
the write control is used for indicating that the current packet is write transmission; the write address is used for writing the address of the transmission packet; the transmission byte control is used for indicating the number of data bytes in the current packet; the write data is used for writing data into a transmission packet; the write transmission packet error detection code is used for detecting the transmission error and error correction of the write transmission packet, and the generation operation of the write transmission packet error detection code comprises write control/write address/transmission byte control/write data; the transmission acknowledgement is used to confirm that the bit has been correctly transmitted by the transmission from the die to the master die.
In an embodiment, the write transfer method has high reliability control over write transfer:
specifically, when the slave die does not detect an error or detects an error and corrects the error, the data is finally written into the slave die and returns to the successful confirmation of the master die, and the master die knows that the last transmission is completed correctly after receiving the successful confirmation;
specifically, when the slave die detects an error and cannot correct the error, the slave die discards the write transmission content, and returns a failure confirmation to the master die, and the master die receives the failure confirmation, knows that the last transmission failed, and retransmits the write transmission.
In an embodiment, the write transmission method controls the transmission bytes, dynamically adjusts the number of transmission bytes, selects the transmission bytes according to the number of bytes needing to be written, and reduces the transmission time:
specifically, when the byte transmission control indication of write transmission is detected as byte transmission, the write data is 8 bits, and the received correct data is written in the address position from die;
specifically, when the detection write transfer byte control indicates half-word transfer, the write data is 16 bits, and the received correct data is written into the write address position from die (the write address lower bit is forced to be 0);
specifically, when the byte control indication of the write transfer is detected as a word transfer, the write data is 32 bits, and the correct data is received and written into the write address location from die (the write address is forced to be considered as 0 lower two bits).
Referring to fig. 3, the present invention discloses an embodiment of a read transmission method, in which a read transmission packet from a master die to a slave die and from the slave die to the master die needs to be read first; the position of the control bit in the transmission packet in fig. 3 is not limited to the position in the above figure, and the step of reading the transmission packet includes: reading control, address reading, transmission byte control, data reading and transmission packet error detection code reading; wherein,
the read control is used for indicating that the current packet is read transmission; the reading address is used for reading the address of the transmission packet; the transmission byte control is used for indicating the number of data bytes in the current packet; the read data is used for reading data in the transmission packet; the read transport packet error detection code is used for detecting a transport error and correcting an error of the read transport packet, and the read transport packet error detection code generating operation includes write control/write address/transport byte control/write data.
In an embodiment, the read transfer method has high reliability control over read transfers:
specifically, when the main die does not detect an error or detects an error and corrects the error, correct read data can be acquired; when the main die detects an error and cannot correct it, the read data content is discarded and the data is re-read.
In an embodiment, the read transmission method controls the transmission bytes, dynamically adjusts the number of transmission bytes, selects the read transmission bytes according to the number of bytes needing to be read, and reduces the transmission time:
specifically, when the byte transmission control indication of the read transmission is detected to be byte transmission, the read data is 8 bits, and correct byte data is returned from the die according to the read address;
specifically, when the detection read transfer byte control indication is halfword transfer, the read data is 16 bits, and the halfword data is returned from die according to the read address (the read address is forced to be 0 at the low order);
specifically, when the read transfer byte control indication is detected as a word transfer, the read data is 32 bits, and the word data is returned from the die according to the read address (the two lower bits of the read address are forced to be 0).
The invention also discloses a specific embodiment of byte transmission control, and the serial interface of the embodiment is based on an SPI-like interface, and the address length is 12 bits (namely 4KB address space).
The coding of the control bit is defined as: the read control is defined as code 1 and the write control is defined as code 0;
the encoding of the transport byte control is defined as: byte transmission is defined as encoding 00, halfword transmission is defined as encoding 01, word transmission is defined as encoding 10, and doubleword transmission is defined as encoding 11;
the encoding of the response control is defined as: the encoding of the failure response is defined as: 0, the encoding of a successful response is defined as: 1
The encoding of the packet error detection code is defined as: CRC8, fixed as 8 bits;
referring to fig. 4 to 11, sclk denotes a serial clock, csn denotes a chip select signal, and is active low, mosi denotes a data signal, which is output by a master die or input from a slave die, miso denotes a data signal, which is input by a master die or output from a slave die, CRC denotes a cyclic redundancy check, and ACK denotes an acknowledgement; d [ n ], n represents the number of bits of the transmitted data, am, m is the number of address bits;
in fig. 4, if byte read transfer is implemented, the encoding of the control bit is set to 1, and the encoding of the transfer byte control is set to 00, so that the miso outputs a CRC containing 1 byte of read data and 1 byte;
in fig. 5, if byte write transfer is implemented, the encoding of the control bit is set to 0, and the encoding of the transfer byte control is set to 00, mosi outputs write data including 1 byte and CRC including 1 byte;
in fig. 6, if the nibble read transfer is implemented, the encoding of the control bit is set to 1, and the encoding of the transfer byte control is set to 01, so that the miso outputs read data including 2 bytes and CRC of 1 byte;
in fig. 7, if the nibble write transfer is implemented, the encoding of the control bit is set to 0, and the encoding of the transfer byte control is set to 01, then mosi outputs write data including 2 bytes and CRC of 1 byte;
in fig. 8, if the word read transfer is implemented, the encoding of the control bit is set to 1, and the encoding of the transfer byte control is set to 10, so that the miso outputs the read data including 4 bytes and the CRC including 1 byte;
in fig. 9, if the word write transfer is realized, the encoding of the control bit is set to 0, and the encoding of the transfer byte control is set to 10, then mosi outputs a CRC including 4 bytes of write data and 1 byte;
in fig. 10, if the double-word read transfer is implemented, the encoding of the control bit is set to 1, and the encoding of the transfer byte control is set to 11, so that the miso outputs the read data including 8 bytes and the CRC including 1 byte;
in fig. 11, when the double-word write transfer is implemented, the encoding of the control bit is set to 0, and the encoding of the transfer byte control is set to 11, mosi outputs write data including 8 bytes and CRC of 1 byte.
Therefore, the invention selects the transmission byte according to the byte number to be written or read, realizes the dynamic adjustment of the transmission byte number and reduces the transmission time.
Although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that various changes in the embodiments and/or modifications of the invention can be made, and equivalents and modifications of some features of the invention can be made without departing from the spirit and scope of the invention.
Claims (7)
1. A communication method between chips die is characterized in that: according to the byte number to be written or read, the byte number to be transmitted is dynamically adjusted and selected, and the transmission time is reduced;
the communication method comprises the following steps: a write transfer method and a read transfer method;
the write transmission method comprises write transmission packets from a master die to a slave die and from the master die to the slave die, and the write transmission packets comprise the steps of:
write control for indicating that the current packet is a write transfer;
a write address for writing an address of a transport packet;
a transmission byte control for indicating the number of data bytes in the current write transmission packet;
write data for writing data to the write transfer packet;
a write transmission packet error detection code for detecting a transmission error and correcting an error of the write transmission packet;
a transmission acknowledgement to confirm that the bit has been correctly transmitted by the write transmission from the die to the master die;
the write transmission method can realize that the current write transmission content is discarded and retransmitted when the error can not be corrected in the write transmission;
when the slave die detects errors and can not correct the errors, the slave die discards the write transmission content, and returns a failure confirmation to the master die, and the master die learns the last transmission failure after receiving the failure confirmation and retransmits the write transmission content;
the reading transmission method comprises reading transmission packets from a main die to a slave die and from the master die to the main die, and the step of reading the transmission packets comprises the following steps:
a read control for indicating that the current read transport packet is read transport;
a read address for reading an address of a transport packet;
a transmission byte control for indicating the number of data bytes in the current read transmission packet;
the read data is used for reading data in the read transmission packet;
a read transport packet error detection code for detecting a transport error and correcting an error of the read transport packet;
in the reading transmission method, when the main die does not detect errors or detects and corrects the errors, correct reading data content is obtained; when the primary die detects an error and cannot correct it, the read data content is discarded and the data is re-read.
2. The method of communication between chips die of claim 1, wherein: the write transfer method can realize detection error control or correction error control of write transfer.
3. The method of inter-chip die communication according to claim 2, wherein: and when the slave die does not detect the error or detects the error and corrects the error, the data is finally written into the slave die and returns to the success confirmation of the master die, and the master die knows that the last transmission is completed correctly after receiving the success confirmation.
4. The method of inter-chip die communication according to claim 1, wherein: the write transmission method dynamically adjusts the number of transmission bytes through write transmission byte control, and realizes the write transmission byte control.
5. The method of inter-chip die communication according to claim 4, wherein: when the byte transmission control indication of the write transmission is detected to be byte transmission, the write data is set to be 8 bits, and correct data is received from die and written into a write address position;
when detecting that the byte control indication of write transmission is half-word transmission, setting write data to be 16 bits, and receiving correct data from die and writing the data into a write address position;
when the byte control indication of write transmission is detected to be word transmission, the write data is set to be 32 bits, and correct data is received from die and written into a write address position; wherein the lower bit of the write address is 0.
6. The method of inter-chip die communication according to claim 1, wherein: the reading transmission method dynamically adjusts the number of transmission bytes by reading the transmission bytes to realize the control of the reading transmission bytes.
7. The method of inter-chip die communication according to claim 6, wherein: when the byte transmission control indication of the read transmission is detected to be byte transmission, the read data is 8 bits, and correct byte data is returned from the die according to the read address;
when the control indication of the read transmission byte is detected to be half-word transmission, the read data is 16 bits, and half-word data is returned from die according to the read address;
when the control indication of the read transmission byte is detected to be word transmission, the read data is 32 bits, and the word data is returned from the die according to the read address; wherein, the lower bit of the read address is 0.
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CN107483157A (en) * | 2017-09-01 | 2017-12-15 | 郑州云海信息技术有限公司 | A kind of CRC check method and system based on FPGA |
CN111427832A (en) * | 2020-04-17 | 2020-07-17 | 展讯通信(上海)有限公司 | Data transmission method and communication device of serial bus |
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