CN115498062A - Double-gate heterostructure exciton transistor, preparation method and application - Google Patents
Double-gate heterostructure exciton transistor, preparation method and application Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 239000000463 material Substances 0.000 claims abstract description 38
- 229910004298 SiO 2 Inorganic materials 0.000 claims abstract description 15
- 230000005540 biological transmission Effects 0.000 claims abstract description 5
- 230000003287 optical effect Effects 0.000 claims abstract description 4
- 238000012545 processing Methods 0.000 claims abstract description 3
- 239000010408 film Substances 0.000 claims description 130
- 239000010410 layer Substances 0.000 claims description 96
- 239000002356 single layer Substances 0.000 claims description 46
- 229920002120 photoresistant polymer Polymers 0.000 claims description 26
- 239000010409 thin film Substances 0.000 claims description 24
- 238000004528 spin coating Methods 0.000 claims description 18
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 16
- 239000010931 gold Substances 0.000 claims description 16
- 229910052737 gold Inorganic materials 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 16
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 15
- 229910021389 graphene Inorganic materials 0.000 claims description 15
- 230000008569 process Effects 0.000 claims description 14
- 150000004770 chalcogenides Chemical class 0.000 claims description 12
- 238000001259 photo etching Methods 0.000 claims description 12
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- 238000000609 electron-beam lithography Methods 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 10
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 8
- 238000011161 development Methods 0.000 claims description 8
- 238000010894 electron beam technology Methods 0.000 claims description 8
- 238000005566 electron beam evaporation Methods 0.000 claims description 6
- 238000001704 evaporation Methods 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 4
- 239000003292 glue Substances 0.000 claims description 4
- 238000011068 loading method Methods 0.000 claims description 4
- 238000012546 transfer Methods 0.000 claims description 4
- 238000002791 soaking Methods 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 6
- 238000002198 surface plasmon resonance spectroscopy Methods 0.000 abstract description 5
- 230000003993 interaction Effects 0.000 abstract description 4
- 230000031700 light absorption Effects 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 239000011229 interlayer Substances 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 238000010521 absorption reaction Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000008367 deionised water Substances 0.000 description 3
- 229910021641 deionized water Inorganic materials 0.000 description 3
- CWQXQMHSOZUFJS-UHFFFAOYSA-N molybdenum disulfide Chemical compound S=[Mo]=S CWQXQMHSOZUFJS-UHFFFAOYSA-N 0.000 description 3
- 229910052982 molybdenum disulfide Inorganic materials 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- -1 transition metal chalcogenide compounds Chemical class 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- ROUIDRHELGULJS-UHFFFAOYSA-N bis(selanylidene)tungsten Chemical compound [Se]=[W]=[Se] ROUIDRHELGULJS-UHFFFAOYSA-N 0.000 description 2
- 238000012512 characterization method Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052723 transition metal Inorganic materials 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 1
- 238000001069 Raman spectroscopy Methods 0.000 description 1
- 238000013473 artificial intelligence Methods 0.000 description 1
- 230000002238 attenuated effect Effects 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 238000009440 infrastructure construction Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- ITRNXVSDJBHYNJ-UHFFFAOYSA-N tungsten disulfide Chemical compound S=[W]=S ITRNXVSDJBHYNJ-UHFFFAOYSA-N 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
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Abstract
The invention provides a double-gate heterostructure exciton transistor, a preparation method and application thereof, wherein the transistor comprises SiO with a bottom gate electrode plated on the surface 2 a/Si substrate attached to SiO 2 A two-dimensional layered material heterojunction on the Si substrate, a dielectric layer film attached to the middle region of the two-dimensional layered material heterojunction, two-side transparent conductive layer films attached to the two-dimensional layered material heterojunction and positioned at two sides of the dielectric layer film, and a middle transparent conductive layer film attached to the dielectric layer film. The middle transparent conductive layer film is attached with a grid electrode, and the two transparent conductive layer films are respectively attached with a drain electrode and a source electrode. During operation, incident light and SiO 2 Bottom gate electrode on/Si substrateThe surface plasmon resonance effect can be generated by the interaction between the excitonic transistors, the light absorption efficiency of the semiconductor material can be enhanced by utilizing the surface plasmon resonance effect, and an integrated system consisting of a plurality of excitonic transistors has the advantages of an optical data transmission system and an electronic data processing system.
Description
Technical Field
The invention relates to the technical field of electronic components, in particular to a double-gate heterostructure exciton transistor, a preparation method and application.
Background
Along with the development of new infrastructure construction such as big data, artificial intelligence, etc., higher requirements are put forward on the power efficiency and the integration density of devices, and excitonic devices begin to appear in the field of vision of people. When the exciton device works, a light signal penetrates through the source electrode to be incident on the channel material, the channel material is excited to generate interlayer excitons, and an electric field is generated in the channel under the action of source-drain voltage to enable the interlayer excitons to realize micron-scale distance transmission. The interlayer exciton is dissociated into an electron and a hole at the drain electrode, energy is discharged in the form of light, and the transmission of the interlayer exciton, that is, the on-off of the exciton device can be controlled by changing the gate voltage. However, due to the common defects in the channel material, poor coupling between material layers, and other problems, the light signal incident on the channel material through the source reduces the effective absorption of the light signal by the channel material, and the interlayer exciton yield in the source channel region is reduced. Since the generated interlayer excitons are reduced and the optical signal generated by the interlayer excitons being dissociated at the drain is attenuated, the transistor signal conversion efficiency is seriously lowered. Therefore, it is very important to solve the technical problem of low light signal absorption and conversion efficiency of the exciton device at room temperature.
Disclosure of Invention
Aiming at the technical problems of low absorption and conversion efficiency of incident light in the existing exciton transistor, the invention provides a preparation method of a double-gate heterostructure exciton transistor, which is implemented by using SiO 2 The bottom gate electrode arranged in the groove on the Si substrate and the surface plasmon resonance effect generated by the interaction of incident light limit the light field in a small range near the bottom gate electrode, greatly enhance the absorption of the exciton transistor to the incident light, thereby converting more incident light into excitons and simultaneously solving the problem of large energy loss in the signal transmission process of the exciton transistor.
The technical scheme adopted by the invention is as follows:
a double-gate heterostructure exciton transistorCharacterized in that the SiO film comprises SiO with a bottom gate electrode plated on the surface 2 a/Si substrate, adhered to SiO 2 The two-dimensional layered material heterojunction on the Si substrate, a dielectric layer film attached to the middle region of the two-dimensional layered material heterojunction, two-side light-transmitting conducting layer films attached to the two-dimensional layered material heterojunction and located on two sides of the dielectric layer film, and a middle light-transmitting conducting layer film attached to the dielectric layer film, wherein the middle light-transmitting conducting layer film is not in contact with the two-side light-transmitting conducting layer films, a grid electrode is attached to the middle light-transmitting conducting layer film, and a drain electrode and a source electrode are respectively attached to the two-side light-transmitting conducting layer films.
Furthermore, the two-dimensional layered material heterojunction is formed by two laminated single-layer chalcogenide thin films, wherein the single-layer chalcogenide thin film is a single layer of MoS 2 Thin film, single layer WSe 2 A film; the dielectric layer film is a single-layer h-BN film; the middle light-transmitting conducting layer film and the light-transmitting conducting layer films on the two sides are single-layer graphene films.
Further, the SiO 2 A plurality of grooves are formed in the/Si substrate, and the bottom gate electrodes are attached to the grooves and completely fill the grooves.
Further, the thickness of the dielectric layer film is 0.4-2 nm; the thickness of the transparent conductive layer film is 0.4-4 nm.
Furthermore, the grooves are arranged in parallel, the number of the grooves is 5-8, the depth of the grooves is 45-50 nm, the length of the grooves is 10-15 mu m, and the distance between every two adjacent grooves is 500nm.
The preparation method of the double-gate heterostructure exciton transistor is characterized by comprising the following steps:
step 1: in SiO 2 Etching a plurality of grooves on the Si substrate;
step 2: siO after step 1 2 Spin-coating photoresist on Si substrate, photoetching bottom gate electrode pattern in the groove by using electron beam, evaporating gold film in the groove by electron beam evaporation process, the thickness of the evaporated gold film is identical to the depth of the groove, removing the photoresist and the gold film outside the exposure area to form SiO with bottom gate electrode plated on the surface 2 a/Si substrate;
and 3, step 3: mechanically stripping two single-layer chalcogenide thin films, dielectric layer thin films and light-transmitting conducting layer thin films by means of a two-dimensional material transfer platform, and sequentially transferring the chalcogenide thin films, the dielectric layer thin films and the light-transmitting conducting layer thin films to SiO with the surface plated with a bottom gate electrode 2 The dielectric layer film length is less than two single-layer chalcogenide films and the light-transmitting conducting layer film, and the dielectric layer film length is positioned in the middle area between the two-dimensional layered material heterojunction formed by the two single-layer chalcogenide films and the light-transmitting conducting layer film;
and 4, step 4: spin-coating photoresist on the light-transmitting conducting layer film again, photoetching source electrode, grid electrode and drain electrode patterns by using an electron beam, evaporating a gold film on the light-transmitting conducting layer film by using an electron beam evaporation process, and then removing the photoresist and the gold film outside an exposure area;
and 5: and etching the light-transmitting conducting layer film into three parts which are not in contact with the middle light-transmitting conducting layer film and the two side light-transmitting conducting layer films, so that the middle light-transmitting conducting layer film is attached to the dielectric layer film, and the two side light-transmitting conducting layer films are attached to the two-dimensional layered material heterojunction and positioned on the two sides of the dielectric layer film, thereby obtaining the double-gate heterostructure exciton transistor.
Further, the spin-on photoresist process in step 2 is as follows: dropping the photoresist to SiO 2 On the dielectric layer, spin-coating at 800r/min for 20s, and then spin-coating at 2000r/min for 50s; carrying out electron beam exposure and development after glue homogenizing, and carrying out development treatment for 50s by adopting a developing solution; the spin coating process of the photoresist in the step 4 comprises the following steps: dripping photoresist on the transparent conducting layer film, spin-coating at the speed of 400r/min for 20s, and then spin-coating at the speed of 1000r/min for 50s; and carrying out electron beam exposure and development after glue homogenizing.
Further, the electron beam lithography process in step 2 is: introducing nitrogen gas into the photoetching equipment, and then vacuumizing to 5X 10 vacuum degree -3 And Pa, carrying out electron beam lithography after loading an accelerating voltage to 30 kV.
Further, when the photoresist and the gold film outside the exposure area are removed in the step 2, siO is added 2 Soaking the Si substrate in acetone until the gold film outside the exposure area is photoetchedThe glue is totally separated from SiO 2 a/Si substrate.
Use of an integrated system consisting of a number of said double-gate heterostructure excitonic transistors for integrated optical data transmission and electronic data processing systems.
In the present invention, incident light and SiO 2 The interaction between the bottom gate electrodes on the/Si substrate can generate a surface plasmon resonance effect, and the surface plasmon resonance effect can be utilized to enhance the light absorption efficiency of the channel material, so that more incident light is converted into excitons. The combination of the bottom gate electrode and the exciton device can effectively solve the problems of light absorption and low conversion rate of channel materials. The transparent conductive layer film is used as a transparent grid, and can enable each layer to form good coupling.
The electrons are positioned in a conduction band, the holes are positioned in a valence band, and the electric control transportation and modulation of the interlayer excitons of the heterogeneous double-layer film in the same physical space can be simultaneously completed through the upper and lower grid voltages and the source and drain voltages by utilizing the characteristic that the electrons and the holes in the interlayer excitons are respectively positioned in different layers.
The interlayer exciton in the double-gate heterostructure exciton transistor has long service life and micron-level diffusion length, and unique characteristics of polarization, wavelength, intensity and the like of emission of the transistor can be conveniently controlled by electric control, so that the power efficiency of the transistor is improved, and the problem that practical application of a single two-dimensional material is limited at normal temperature due to insufficient diffusion length of the exciton is solved.
According to the invention, the two-dimensional material heterojunction is used as a channel material, electrons jump and leave holes under the action of incident light, the characteristics that the electrons and the holes are respectively in different layers are formed, and the service life of excitons is prolonged by two orders of magnitude due to the characteristic of interlayer exciton charge space separation. Meanwhile, transition metal chalcogenide compounds such as molybdenum disulfide and tungsten disulfide with atomic-scale thickness have important potential application value in photoelectronics and valley electronics due to direct band gap and monolayer-limited semiconductor properties. The two-dimensional characteristics of the single-layer transition metal chalcogenide compound have an enhancement effect on coulomb interaction, so that bound electron-hole pairs can be generated, and the development of an exciton device at room temperature becomes possible.
Drawings
FIG. 1 is a schematic diagram of a SiO coated with a bottom gate electrode according to the present invention 2 The structure of the/Si substrate is shown schematically.
Fig. 2 is a perspective view of a dual-gate heterostructure exciton transistor fabricated in accordance with embodiments of the present invention.
Fig. 3 is a front view of a dual gate heterostructure exciton transistor fabricated in an embodiment of the present invention.
In the figure: 1-a silicon substrate; 2-a silicon dioxide layer; 3-a bottom gate electrode; 4-two-dimensional layered material heterojunction; 5-a dielectric layer film; 6-middle light-transmitting conductive layer film; 7-left side light-transmitting conductive layer film; an 8-source electrode; 9-a grid; 10-a drain electrode; 11-right light-transmissive conductive layer film.
Detailed Description
The invention will be further described with reference to the following figures and specific examples, but the scope of the invention is not limited thereto.
The double-gate heterostructure exciton transistor comprises SiO with a bottom gate electrode 3 plated on the surface 2 a/Si substrate attached to SiO 2 A two-dimensional layered material heterojunction 4 on a Si substrate, a dielectric layer film 5 attached to the two-dimensional layered material heterojunction 4 in the middle, a left light-transmitting conductive layer film 7 and a right light-transmitting conductive layer film 11 attached to the two-dimensional layered material heterojunction 4 and located on two sides of the dielectric layer film 5, and a middle light-transmitting conductive layer film 6 attached to the dielectric layer film 5, wherein the middle light-transmitting conductive layer film 6, the left light-transmitting conductive layer film 7 and the right light-transmitting conductive layer film 11 are not in contact with each other, a grid 9 is attached to the middle light-transmitting conductive layer film 6, a source electrode 8 is attached to the left light-transmitting conductive layer film 7, and a drain electrode 10 is attached to the right light-transmitting conductive layer film 11.
The two-dimensional layered material heterojunction 4 is formed by two single-layered chalcogenide compounds, such as molybdenum disulfide and tungsten diselenide. The dielectric layer film 5 is a single-layer h-BN film; the middle light-transmitting conducting layer film 6, the left light-transmitting conducting layer film 7 and the right light-transmitting conducting layer film 11 are all single-layer graphene films.
The preparation method of the double-gate heterostructure exciton transistor is described below by taking a heterojunction formed by molybdenum disulfide and tungsten diselenide as an example.
Firstly, the silicon substrate 1 is sequentially placed in absolute ethyl alcohol and deionized water to be ultrasonically cleaned in a low-frequency ultrasonic oscillation mode. Wherein the ultrasonic frequency is: 20kHz, power density: 1W/cm 2 The cleaning time is as follows: and 2min, blowing nitrogen to blow the glass fiber after cleaning. A silicon dioxide layer 2 is deposited by chemical vapour deposition to a thickness of 300nm on a silicon substrate 1.
Method for etching Si/SiO by using focused ion beam 2 And etching the substrate, wherein the number of the grooves is 5, the width is 500nm, the length is 10 mu m, the depth is 50nm, and the distance between the adjacent grooves is 500nm. For SiO treated by etching 2 the/Si substrate was cleaned with deionized water and baked with nitrogen. Etching the Si/SiO 2 The substrate was placed on a leveling plate, the photoresist was dropped onto the silicon dioxide layer 2, spin-coated at 800r/min for 20s and then at 2000r/min for 50s. And (3) exposing and drawing a bottom gate electrode 3 pattern through an EBL (electron beam lithography) technology after photoresist is homogenized, wherein the photoetching process comprises the following steps: introducing nitrogen gas into the photoetching equipment, and then vacuumizing to 5X 10 vacuum degree -3 And Pa, carrying out electron beam lithography after loading an accelerating voltage to 30 kV. After photoetching, siO 2 And putting the/Si substrate into a developing solution for 50s, slightly shaking to disperse the photoresist, and evaporating a gold film with the thickness of 50nm on an exposure area by an electron beam evaporation technology. Immersing the coated substrate in acetone, standing for 4h to ensure that the metal film of the unexposed area is completely separated from the substrate, taking out the substrate, washing the substrate with deionized water, and drying the substrate by nitrogen for later use.
High quality single layer MoS production by mechanical stripping 2 Thin film, single layer WSe 2 Film, monolayerh-BN film, single-layer graphene film, and characterization by Raman spectroscopy, wherein the single-layer MoS 2 Thin films and monolayer WSe 2 The thickness of the film is 0.7nm, and the thickness of the single-layer h-BN film and the single-layer graphene film is 0.4nm. The single-layer MoS after characterization 2 Thin film, single layer WSe 2 The film, the single-layer h-BN film and the single-layer graphene film are sequentially transferred to the SiO plated with the bottom gate electrode 3 by a dry transfer method 2 On the Si substrate, the materials should be precisely attached during the transfer process, wherein the length of the single-layer h-BN film is less than that of the other three films and is positioned on the single-layer MoS 2 Thin films and monolayer WSe 2 The two-dimensional layered material heterojunction 4 formed by the thin film and the single-layer graphene thin film are arranged in the middle. And (3) placing the transferred substrate on a photoresist evening disc, dripping photoresist on the single-layer graphene film on the uppermost layer, spin-coating at the speed of 400r/min for 20s, and then spin-coating at the speed of 1000r/min for 50s. And (3) exposing and drawing a top gate electrode pattern through an EBL (electron beam lithography) technology after photoresist is homogenized, wherein the photoetching process comprises the following steps: introducing nitrogen gas into the photoetching equipment, and then vacuumizing to 5X 10 vacuum degree -3 Pa, and carrying out electron beam lithography after loading an accelerating voltage to 30 kV. After photoetching, the substrate is put into a developing solution for 50s, the photoresist is dispersed by slight shaking, and a gold film with the thickness of 50nm is evaporated on an exposure area by an electron beam evaporation technology. And immersing the coated substrate in acetone, standing for 4h to enable the metal film of the unexposed area to be completely separated from the substrate, and finally etching the single-layer graphene film into three mutually non-contact parts, namely a middle single-layer graphene film, a left single-layer graphene film and a right single-layer graphene film, by means of a plasma etching technology, wherein the etching width is 500nm. And attaching the middle single-layer graphene film to the single-layer h-BN film, and attaching the left single-layer graphene film and the right single-layer graphene film to the two-dimensional layered material heterojunction 4 and positioned at two sides of the single-layer h-BN film to obtain the double-gate heterostructure exciton transistor.
The examples are preferred embodiments of the present invention, but the present invention is not limited to the above embodiments, and any obvious modifications, substitutions or variations can be made by those skilled in the art without departing from the spirit of the present invention.
Claims (10)
1. The double-gate heterostructure exciton transistor is characterized by comprising SiO with a bottom gate electrode (3) plated on the surface 2 a/Si substrate attached to SiO 2 The two-dimensional layered material heterojunction structure comprises a two-dimensional layered material heterojunction (4) on a Si substrate, a dielectric layer film (5) attached to the middle area of the two-dimensional layered material heterojunction (4), two side light-transmitting conducting layer films attached to the two-dimensional layered material heterojunction (4) and located on two sides of the dielectric layer film (5), and a middle light-transmitting conducting layer film (6) attached to the dielectric layer film (5), wherein the middle light-transmitting conducting layer film (6) is not in contact with the two side light-transmitting conducting layer films, a grid electrode (9) is attached to the middle light-transmitting conducting layer film (6), and a drain electrode (10) and a source electrode (8) are respectively attached to the two side light-transmitting conducting layer films.
2. The double-gate heterostructure exciton transistor of claim 1, wherein: the two-dimensional layered material heterojunction (4) is formed by two laminated single-layer chalcogenide thin films, and the single-layer chalcogenide thin film is a single-layer MoS 2 Thin film, single layer WSe 2 A film; the dielectric layer film (5) is a single-layer h-BN film; the middle light-transmitting conducting layer film (6) and the light-transmitting conducting layer films on the two sides are single-layer graphene films.
3. The double-gate heterostructure exciton transistor of claim 1, wherein: the SiO 2 A plurality of grooves are formed in the/Si substrate, and the bottom gate electrodes (3) are attached to the grooves and completely fill the grooves.
4. The double-gate heterostructure exciton transistor of claim 2, wherein: the thickness of the dielectric layer film (5) is 0.4-2 nm; the thickness of the middle transparent conductive layer film (6) and the thickness of the transparent conductive layer films at the two sides are both 0.4-4 nm.
5. The double-gate heterostructure exciton transistor of claim 3, wherein: the grooves are arranged in parallel, the number of the grooves is 5-8, the depth of the grooves is 45-50 nm, the length of the grooves is 10-15 mu m, and the distance between every two adjacent grooves is 500nm.
6. The method of fabricating the double-gate heterostructure exciton transistor of any of claims 1-5, comprising the steps of:
step 1: in SiO 2 Etching a plurality of grooves on the Si substrate;
and 2, step: siO after step 1 2 Spin-coating photoresist on a Si substrate, photoetching a bottom gate electrode (3) pattern in the groove by using an electron beam, evaporating a gold film in the groove by using an electron beam evaporation process, wherein the thickness of the evaporated gold film is consistent with the depth of the groove, and then removing the photoresist and the gold film outside an exposure area to form SiO with the bottom gate electrode (3) plated on the surface 2 a/Si substrate;
and step 3: mechanically stripping two single-layer chalcogenide thin films, a dielectric layer thin film (5) and a light-transmitting conducting layer thin film by a two-dimensional material transfer platform, and sequentially transferring the chalcogenide thin films, the dielectric layer thin film (5) and the light-transmitting conducting layer thin films to SiO with the surface plated with a bottom gate electrode (3) 2 The dielectric layer film (5) is shorter than the chalcogenide film and the light-transmitting conducting layer film of two single layers, and is positioned in the middle area between the two-dimensional layered material heterojunction (4) consisting of the chalcogenide film of two single layers and the light-transmitting conducting layer film;
and 4, step 4: spin-coating photoresist on the light-transmitting conducting layer film again, photoetching patterns of a source electrode (8), a grid electrode (9) and a drain electrode (10) by using electron beams, evaporating a gold film on the light-transmitting conducting layer film by using an electron beam evaporation process, and then removing the photoresist and the gold film outside an exposure area;
and 5: and etching the light-transmitting conducting layer film into three non-contact parts, namely a middle light-transmitting conducting layer film (6) and two side light-transmitting conducting layer films, so that the middle light-transmitting conducting layer film (6) is attached to the dielectric layer film (5), and the two side light-transmitting conducting layer films are attached to the two-dimensional layered material heterojunction (4) and positioned at two sides of the dielectric layer film (5), thereby obtaining the double-gate heterostructure exciton transistor.
7. The method of fabricating a double-gate heterostructure exciton transistor of claim 6, wherein: the spin coating process of the photoresist in the step 2 comprises the following steps: dropping the photoresist to SiO 2 On the dielectric layer, spin-coating at 800r/min for 20s, and then spin-coating at 2000r/min for 50s; carrying out electron beam exposure and development after spin coating, and carrying out development treatment for 50s by adopting a developing solution; the spin coating process of the photoresist in the step 4 comprises the following steps: dropping photoresist on the transparent conducting layer film, spin-coating at the speed of 400r/min for 20s, and then spin-coating at the speed of 1000r/min for 50s; and after glue is homogenized, electron beam exposure and development are carried out.
8. The method of fabricating a double-gate heterostructure exciton transistor of claim 6, wherein: the electron beam lithography process in the step 2 is as follows: introducing nitrogen gas into the photoetching equipment, and then vacuumizing to 5X 10 vacuum degree -3 And Pa, carrying out electron beam lithography after loading an accelerating voltage to 30 kV.
9. The method of manufacturing a double-gate heterostructure exciton transistor of claim 6, wherein: when the photoresist and the gold film outside the exposure area are removed in the step 2, siO is added 2 Soaking the Si substrate in acetone until the gold film outside the exposure area is completely separated from SiO with the photoresist 2 a/Si substrate.
10. Use of an integrated system consisting of several double gate heterostructure excitonic transistors as defined in anyone of the claims 1-5 for integrated optical data transmission and electronic data processing systems.
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