CN115498037A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN115498037A
CN115498037A CN202110674533.8A CN202110674533A CN115498037A CN 115498037 A CN115498037 A CN 115498037A CN 202110674533 A CN202110674533 A CN 202110674533A CN 115498037 A CN115498037 A CN 115498037A
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layer
resistance
resistor
resistive
forming
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蔡巧明
马丽莎
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Zhongxin North Integrated Circuit Manufacturing Beijing Co ltd
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Zhongxin North Integrated Circuit Manufacturing Beijing Co ltd
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Priority to CN202110674533.8A priority Critical patent/CN115498037A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a semiconductor substrate comprising a resistance area, wherein a resistance structure material layer is formed on the semiconductor substrate of the resistance area; forming one or more parallel trenches in the resistive structure material layer in the resistive region, the trenches penetrating a portion of the thickness of the resistive structure material layer; after the groove is formed, patterning the resistance structure material layer, removing part of the resistance structure material layer outside the groove, and reserving part of the resistance structure material layer containing the groove as a resistance structure; forming a dielectric layer on the semiconductor substrate at the side part of the resistance structure, wherein the dielectric layer is also filled in the groove and is exposed out of the top part of the resistance structure; removing part of the resistor structure at the junction of the resistor structure and the dielectric layer along the extension direction of the resistor structure to form an opening surrounded by the dielectric layer and the rest resistor structure; an electrode is formed in the opening. The top of the resistor structure is provided with the groove, so that the probability of the occurrence of the dent defect on the top surface of the resistor structure is reduced.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
Active and passive devices are typically included in an integrated circuit. The active device includes a MOS transistor and the passive device includes a resistor. The resistor is an indispensable component in the integrated circuit design, and in the integrated circuit design, the resistor can be a polysilicon resistor or a metal resistor.
Among them, in a device having a metal gate structure, a polysilicon resistance structure is generally used. In addition, the polysilicon resistor structure is generally large in size at present.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which improve the performance of the semiconductor structure.
To solve the above problem, an embodiment of the present invention provides a semiconductor structure, including: a semiconductor substrate including a resistance region; the resistor structure is positioned on the semiconductor substrate of the resistor area, wherein one or more grooves which are arranged in parallel are formed at the top of the resistor structure, and the grooves penetrate through part of the thickness of the resistor structure; the electrodes are positioned in the resistance area, are positioned on two sides of the resistance structure along the extension direction of the resistance structure, and are connected with the side wall of the resistance structure; and the dielectric layer is positioned on the semiconductor substrate at the side parts of the resistance structure and the electrode, is also filled in the groove, and is exposed out of the tops of the resistance structure and the electrode.
Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, including: providing a semiconductor substrate, wherein the semiconductor substrate comprises a resistance area, and a resistance structure material layer is formed on the semiconductor substrate of the resistance area; forming one or more parallel trenches in the resistive structure material layer in the resistive region, the trenches extending through a portion of the thickness of the resistive structure material layer; after the groove is formed, patterning the resistance structure material layer, removing part of the resistance structure material layer outside the groove, and reserving the part of the resistance structure material layer containing the groove as a resistance structure; forming a dielectric layer on the semiconductor substrate at the side part of the resistance structure, wherein the dielectric layer is also filled in the groove and is exposed out of the top part of the resistance structure; removing part of the resistor structure at the junction of the resistor structure and the dielectric layer along the extension direction of the resistor structure to form an opening surrounded by the dielectric layer and the rest of the resistor structure; an electrode is formed in the opening.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the semiconductor structure provided by the embodiment of the invention, one or more grooves which are arranged in parallel are formed at the top of the resistor structure; in the process of forming the resistor structure and the dielectric layer, the process of planarizing the resistor structure and the dielectric layer is generally included, and when planarizing is performed, if the size of the resistor structure is large, a serious dent defect (destroying defect) is likely to occur on the top surface of the resistor structure, in this embodiment, the electrodes are located on two sides of the resistor structure along the extending direction of the resistor structure, and the electrodes are only used for electrically connecting the resistor structure, the size of the electrodes is small, so that the size of the remaining resistor structure is large, and the dent defect is more likely to occur, and therefore, by forming the grooves on the top of the resistor structure, the contact area between the grinding pad and the top surface of the resistor structure in the planarizing process is reduced, so that the probability of the dent defect occurring on the top surface of the resistor structure is reduced, the flatness of the top surface of the resistor structure is improved, the integrity of the resistor structure is favorably ensured, the probability of the deviation of the resistance of the resistor structure is reduced, and the performance of the semiconductor structure is improved.
In the method for forming the semiconductor structure provided by the embodiment of the invention, one or more parallel grooves are formed in the resistance structure material layer; in the process of forming the resistor structure and the dielectric layer, the process of planarizing the resistor structure and the dielectric layer is generally included, and when planarizing is performed, if the size of the resistor structure is large, a serious dent defect (destroying defect) is likely to occur on the top surface of the resistor structure, and in this embodiment, the electrodes are formed on two sides of the resistor structure along the extending direction of the resistor structure, and the electrodes are only used for electrically connecting the resistor structure, the size of the electrodes is small, so that the size of the remaining resistor structure is large, and the dent defect is more likely to occur, and therefore, by forming the grooves on the top of the resistor structure, the contact area between the grinding pad and the top surface of the resistor structure in the planarizing process is reduced, so that the probability of the dent defect occurring on the top surface of the resistor structure is reduced, the flatness of the top surface of the resistor structure is improved, the integrity of the resistor structure is favorably ensured, the probability of the deviation of the resistance of the resistor structure is reduced, and the performance of the semiconductor structure is improved.
Drawings
Fig. 1 to 4 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;
FIGS. 5-7 are schematic structural diagrams illustrating a semiconductor structure according to an embodiment of the present invention;
fig. 8 to 20 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The performance of semiconductor structures is still desired. There are reasons why the performance of semiconductor structures has yet to be improved when analyzed in conjunction with a method of forming the semiconductor structures.
Referring to fig. 1 to 4, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.
Referring to fig. 1, a semiconductor substrate 10 is provided, the semiconductor substrate 10 includes a resistance region 10R and a device region 10H, a resistance structure material layer 20 is formed on the semiconductor substrate 10, and the resistance structure material layer 20 includes a metal barrier layer 22 and a top resistance layer 23 on the metal barrier layer 22.
Referring to fig. 2, the resistance structure material layer 20 is patterned, the remaining resistance structure material layer 20 on the semiconductor substrate 10 in the resistance region 10R is left as a resistance structure 30, and the top resistance layer 23 on the remaining metal barrier layer 22 is left as a dummy gate layer 31 in the device region 10H.
After patterning the resistive structure material layer 20, in the resistive region 10R, the remaining metal barrier layer 22 is used as a bottom resistive layer in the resistive structure 30.
The extending direction of the resistor structure 30 is a first direction (not labeled), and the arrangement direction of the resistor structure 30 and the dummy gate layer 31 is a second direction (as shown in the X direction in fig. 2). The first direction is perpendicular to the second direction, and both the first direction and the second direction are parallel to the surface of the semiconductor substrate 10.
Referring to fig. 3, fig. 3 is a cross-sectional view taken along a second direction, and a dielectric layer 40 is formed on the semiconductor substrate 10 at a side of the resistance structure 30.
The process of forming the dielectric layer 40 generally includes a process of planarizing the dielectric layer 40, and after the planarization process is performed, a relatively serious recess defect is likely to occur at the top of the resistor structure 30 due to the relatively large line width of the resistor structure 30.
Referring to fig. 4, fig. 4 is a cross-sectional view taken along a first direction, in which a portion of the resistor structure 30 at the interface between the resistor structure 30 and the dielectric layer 40 is removed to form an opening surrounded by the dielectric layer 40 and the remaining resistor structure 30; an electrode 35 is formed in the opening.
In the process of forming the electrode 35, a process of planarizing the electrode 35 is usually included, and this planarization process easily causes the top surface of the resistor structure 30 to further recess, even causes the top resistive layer 23 in the resistor structure 30 to excessively recess, so as to expose the metal barrier layer 22 at the bottom thereof, and since the metal barrier layer 22 has a greater influence on the resistance of the resistor structure 30, the resistance of the resistor structure 30 is easily shifted.
Moreover, the electrodes 35 are formed on both sides of the resistor structure 30 along the first direction (i.e., the extending direction of the resistor structure 30), and the remaining resistor structure 30 has a larger size, so that the recess defect is more likely to occur.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a semiconductor substrate comprising a resistance area, wherein a resistance structure material layer is formed on the semiconductor substrate of the resistance area; forming one or more parallel trenches in the resistive structure material layer in the resistive region, the trenches extending through a portion of the thickness of the resistive structure material layer; after the groove is formed, patterning the resistance structure material layer, removing part of the resistance structure material layer outside the groove, and reserving the part of the resistance structure material layer containing the groove as a resistance structure; forming a dielectric layer on the semiconductor substrate at the side part of the resistance structure, wherein the dielectric layer is also filled in the groove and is exposed out of the top part of the resistance structure; removing part of the resistor structure at the junction of the resistor structure and the dielectric layer along the extension direction of the resistor structure to form an opening surrounded by the dielectric layer and the rest resistor structure; an electrode is formed in the opening.
In the method for forming the semiconductor structure provided by the embodiment of the invention, one or more parallel grooves are formed in the resistance structure material layer; in the process of forming the resistor structure and the dielectric layer, the process of planarizing the resistor structure and the dielectric layer is usually included, and during planarization, if the size of the resistor structure is large, severe dishing defects (sinking defects) easily occur on the top surface of the resistor structure, and in this embodiment, the electrodes are formed on two sides of the resistor structure along the extending direction of the resistor structure, and the electrodes are only used for electrically connecting the resistor structure, the size of the electrodes is small, so that the size of the remaining resistor structure is large, and dishing defects are easily occurred, and therefore, by forming the grooves on the top of the resistor structure, the contact area between the grinding pad and the top surface of the resistor structure in the planarization process is reduced, the probability of dishing defects occurring on the top surface of the resistor structure is reduced, the flatness of the top surface of the resistor structure is improved, the integrity of the resistor structure is ensured, the probability of resistance value deviation of the resistor structure is reduced, and the performance of the semiconductor structure is improved.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings.
Referring to fig. 5 to fig. 7 in combination, a schematic structural diagram of an embodiment of the semiconductor structure of the present invention is shown, in which fig. 5 is a top view of the resistor structure, fig. 6 is a cross-sectional view of fig. 5 based on the AA direction, and fig. 7 is a cross-sectional view of fig. 5 based on the BB direction.
For convenience of illustration, the device region is not illustrated in fig. 7, and only the resistance region is illustrated in fig. 7.
The semiconductor structure includes: a semiconductor substrate 101 including a resistance region 101R; a resistor structure 301 located on the semiconductor substrate 101 of the resistor region 101R, wherein one or more trenches (not shown) arranged in parallel are formed in the top of the resistor structure 301, and the trenches penetrate through a part of the thickness of the resistor structure 301; electrodes 351 located in the resistive region 101R, wherein the electrodes 351 are located on two sides of the resistive structure 301 along the extending direction (X direction in fig. 7 and 9) of the resistive structure 301, and are connected to the sidewalls of the resistive structure 301; and the dielectric layer 401 is positioned on the semiconductor substrate 101 at the side parts of the resistance structure 301 and the electrode 351, the dielectric layer 401 is also filled in the groove, and the dielectric layer 401 exposes the top parts of the resistance structure 301 and the electrode 351.
In the semiconductor structure provided by the embodiment of the present invention, one or more trenches arranged in parallel are formed at the top of the resistor structure 301; in the process of forming the resistor structure 301 and the dielectric layer 401, a process of planarizing the resistor structure 301 and the dielectric layer 401 is generally included, and in the planarizing process, if the size of the resistor structure 301 is large, a serious dishing defect (dishing defect) is likely to occur on the top surface of the resistor structure 301, and in this embodiment, the electrodes 351 are located on two sides of the resistor structure 301 in the extending direction of the resistor structure 301, and the electrodes 351 are only used for electrically connecting the resistor structure 301, the size of the electrodes 351 is small, so that the size of the remaining resistor structure 301 is large, and a dishing defect is more likely to occur, and therefore, by forming the grooves on the top of the resistor structure 301, the contact area between the polishing pad and the top surface of the resistor structure 301 in the planarizing process is reduced, so that the probability of the dishing defect occurring on the top surface of the resistor structure 301 is reduced, the flatness of the top surface of the resistor structure 301 is improved, which is beneficial to ensuring the integrity of the resistor structure, thereby reducing the probability of the resistance value of the resistor structure to shift, and further improving the performance of the semiconductor structure.
The semiconductor substrate 101 provides a process operation basis for the formation process of the semiconductor structure.
In this embodiment, the material of the semiconductor substrate 101 is silicon, in other embodiments, the material of the semiconductor substrate may also be one or more of germanium, silicon carbide, gallium arsenide, and indium gallium, and the semiconductor substrate may also be another type of semiconductor substrate such as a silicon-on-insulator semiconductor substrate or a germanium-on-insulator semiconductor substrate. The material of the semiconductor substrate 101 may be a material suitable for process requirements or easy integration.
In this embodiment, the semiconductor substrate 101 includes a resistance region 101R and a device region 101H. The resistor region 101R is used to form a resistor structure, and the device region 101H is used to form a MOS transistor.
In this embodiment, the device region 101H is a Low Voltage (LV) device region for forming a low voltage device. As an example, the operating voltage of the low voltage device is less than 2V.
It should be noted that the semiconductor substrate 101 may further include a high voltage device region (not shown) for forming a high voltage device. The operating voltage of the high-voltage device is greater than the operating voltage of the low-voltage device. As an example, the operating voltage of the high voltage device is greater than 10V.
In this embodiment, the semiconductor structure further includes an isolation structure 111 located in the semiconductor substrate 101 of the resistance region 101R.
The isolation structure 111 is used for isolating the resistor structure 301 on the isolation structure 111 from the semiconductor substrate 101 to prevent a short circuit between the resistor structure 301 and a well (well) region in the semiconductor substrate 101, and the isolation structure 111 is also used for isolating different devices, for example, in a CMOS manufacturing process, an isolation structure is usually formed between an NMOS transistor and a PMOS transistor. Specifically, the Isolation structure 111 is a Shallow Trench Isolation (STI) structure.
The isolation structure 111 is made of an insulating material. In this embodiment, the material of the isolation structure 111 includes silicon oxide or silicon oxynitride.
It should be noted that, in this embodiment, a metal gate structure of the second device region 101H is formed by a process of forming a high-k gate dielectric layer and then forming a metal gate (high-k first metal gate last), and the resistance structure 301 and the dummy gate layer of the second device region 101H are formed together. The dummy gate layer occupies a space for the gate electrode layer of the second device region 101H.
Therefore, in this embodiment, the semiconductor structure further includes: the gate dielectric layer 211 is positioned on the semiconductor substrate 101 of the device region 101H and the resistance region 101R; the metal barrier layer 221 is positioned on the gate dielectric layer 211; a gate electrode layer 361 over the metal blocking layer 221 of the device region 101H.
In this embodiment, in the device region 101H, the gate dielectric layer 211, the metal blocking layer 221, and the gate electrode layer 361 form a metal gate structure.
The gate dielectric layer 211 is used to isolate the electrode 351 from the semiconductor substrate 101, and the gate electrode layer 361 from the semiconductor substrate 101.
The material of the gate dielectric layer 211 comprises HfO 2 、ZrO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al 2 O 3 、SiO 2 And La 2 O 3 One or more of (a). In this embodiment, the gate dielectric layer 211 includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. Wherein, the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide. Specifically, the high-k dielectric material comprises HfO 2 、ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al 2 O 3 And the like.
It should be noted that the gate dielectric layer 211 may further include a gate oxide layer located between the high-k gate dielectric layer and the semiconductor substrate 101. As an example, the material of the gate oxide layer is silicon oxide.
The metal blocking layer 221 is used for isolating the gate dielectric layer 211 and the electrode 351, and the gate dielectric layer 211 and the gate electrode layer 361 so as to protect the gate dielectric layer 211, and the metal blocking layer 221 is also used for blocking easily-diffused ions (for example, al ions) in the electrode 351 and the gate electrode layer 361 from diffusing into the gate dielectric layer 211.
Specifically, the material of the metal barrier layer 221 includes one or both of titanium nitride (TiN) and silicon-doped titanium nitride (TiSiN). In this embodiment, the metal barrier layer 221 is made of titanium nitride.
The gate electrode layer 361 includes a work function layer (not shown), and an electrode layer (not shown) on the work function layer. The work function layer is used for adjusting the threshold voltage of the formed transistor, and the electrode layer is used for leading out the electrical property of the gate electrode layer 361.
The resistive structure 301 acts as a passive device in the integrated circuit.
In this embodiment, the resistor structure 301 includes the metal barrier layer 221 located in the resistor region 101R, and a top resistive layer 231 located on the metal barrier layer 221, where the metal barrier layer 221 is used as a bottom resistive layer in the resistor structure.
In this embodiment, the resistor structure 301 is located on the isolation structure 111 in the resistor 101R region, so that the resistor structure 301 is insulated from the semiconductor substrate 101.
In this embodiment, the material of the top resistive layer 231 includes polysilicon.
It should be noted that, since the resistance of the top resistive layer 231 is much larger than the resistance of the metal barrier layer 221, the current in the resistive structure 301 mainly flows through the metal barrier layer 221, and accordingly, compared with the top resistive layer 231, the metal barrier layer 221 has a larger influence on the resistance of the resistive structure 301.
In this embodiment, the trench penetrates through a part of the thickness of the resistor structure 301, and a part of the thickness of the resistor structure 301 is remained, so as to maintain the resistance of the resistor structure 301 to meet the performance requirement and protect other film layers located under the resistor structure 301.
Specifically, the trench runs through a portion of the thickness of the top resistive layer 231.
In this embodiment, the extending direction of the plurality of parallel arranged trenches is the same as the extending direction of the resistor structure 301, so that the contact area between the polishing pad and the top surface of the resistor structure 301 during the planarization process can be reduced under the condition that a small number of trenches are formed, the process cost can be saved, the process complexity can be reduced, and the process efficiency can be improved.
In this embodiment, the arrangement direction of the plurality of parallel arranged trenches is perpendicular to the extending direction of the resistor structure 301, and then a sufficient number of the plurality of parallel arranged trenches are arranged in the direction perpendicular to the extending direction of the resistor structure 301 according to the width of the resistor structure 301, so as to greatly reduce the contact area with the top surface of the resistor structure 301 during the planarization process, thereby reducing the probability of the occurrence of the recess defect on the top surface of the resistor structure 301.
It should be noted that the depth h of the groove cannot be too large or too small. If the depth h of the trench is too large, the removed resistor structure 301 is too large, which is easy to affect the resistance of the resistor structure 301, and the depth h of the trench is too large, which is easy to cause damage to other film layers below the trench in the process of forming the trench; if the depth h of the trench is too small, the height of the raised resistor structure 301 around the trench is too small, and the raised resistor structure 301 around the trench is easily removed in the planarization process of the dielectric layer 401, so that the resistor structure 301 at the bottom of the trench is easily contacted in the planarization process, the contact area with the top surface of the resistor structure 301 in the planarization process is difficult to reduce, and the probability of the occurrence of the dent defect on the top surface of the resistor structure 301 is difficult to reduce. Therefore, in this embodiment, the depth h of the trench is 1/4 to 1/3 of the thickness of the resistor structure 301.
Note that the width w1 of the groove must not be too large or too small. If the width w1 of the trench is too large, the resistance structure 301 is removed too much, which easily affects the resistance of the resistance structure 301, and the dielectric layer 401 in the trench is prone to have a serious top surface depression problem during the planarization process; if the width w1 of the trench is too small, the line width of the raised resistor structure 301 around the trench is still large, so that it is difficult to reduce the contact area with the top surface of the resistor structure 301 during the planarization process, and further difficult to reduce the probability of the occurrence of the recess defect on the top surface of the resistor structure 301, and the process difficulty of the photolithography process used during the formation of the trench is also easily increased. Therefore, in the present embodiment, the width w1 of the trench is 0.15 μm to 2 μm.
Meanwhile, it should be noted that the distance w2 between adjacent trenches cannot be too large or too small. If the distance w2 between adjacent trenches is too large, that is, the line width of the raised resistive structure 301 around the trench is still large, it is difficult to reduce the contact area with the top surface of the resistive structure 301 during the planarization process, and it is difficult to reduce the probability of the top surface of the resistive structure 301 having a dishing defect, and accordingly, the width w1 of the trench is too small; if the distance w2 between adjacent trenches is too small, the width w1 of the formed trench is easily too large, the removed resistor structure 301 is too large, the resistance of the resistor structure 301 is easily affected, and in the planarization process, the dielectric layer 401 in the trench is easily subjected to a serious problem of top surface depression. Therefore, in the present embodiment, the distance w2 between adjacent trenches is 0.15 μm to 2 μm.
In this embodiment, the semiconductor structure further includes: a protective layer 341 on the sidewalls of the trench.
In the process of planarizing the resistor structure 301 and the dielectric layer 401, the protective layer 341 protects the resistor structure 301 on the sidewall of the trench, so as to reduce the probability of over-grinding of the resistor structure 301, further effectively reduce the probability of the top surface of the resistor structure 301 having a recess defect, improve the flatness of the top surface of the resistor structure 301, and further improve the performance of the semiconductor structure.
In this embodiment, the protective layer 341 conformally covers the sidewalls and the bottom of the trench, so that the protective layer 341 protects the resistive structure 301 on the sidewalls of the trench and also protects the resistive structure 301 on the bottom of the protective layer 341.
In this embodiment, the material of the protection layer 341 includes silicon nitride or silicon oxynitride.
The silicon nitride has high hardness, and can play a good role in protecting the resistance structure 301 on the side wall and the bottom of the trench in the planarization process.
Along the extending direction of the resistor structure 301, the electrodes 351 are located at two sides of the resistor structure 301 and connected to the sidewalls of the resistor structure 301, that is, the electrodes 351 are connected to the ends of the resistor structure 301.
Specifically, the electrodes 351 are located on the metal barrier layer 221 on both sides of the top resistive layer 231.
The electrodes 351 are used to electrically connect with conductive plugs, thereby electrically connecting the resistive structure 301 with other circuits.
The electrodes 351 are located at the ends of the resistive structure 301. Since the longer the length of the resistor structure 301 is, the larger the resistance of the resistor structure 301 is, by locating the electrodes 351 at the ends of the resistor structure 301, the length of the resistor structure 301 can be maximized, so that the resistor structure 301 obtains a larger resistance.
In this embodiment, the material of the electrode 351 includes a metal material. The metal material has better conductivity, which is beneficial to improving the electrical connection performance of the resistance structure 301 and the external interconnection structure, thereby improving the electrical performance of the semiconductor structure.
In this embodiment, the electrode 351 and the gate electrode layer 361 in the MOS transistor have the same material and the same stacked structure, so that the electrode 351 and the gate electrode layer 361 in the MOS transistor can be formed in the same process. For example, the device gate structure adopted in the low-voltage device region is a metal gate structure, and the metal gate structure is favorable for improving the electrical performance of the MOS transistor and reducing the leakage current.
Accordingly, in the formation of the semiconductor structure, the electrode 351 is formed simultaneously in the step of forming the gate electrode layer 361.
In this embodiment, the material of the electrode 351 includes one or more of TiN, taN, ta, ti, tiAl, W, AL, tiSiN, and TiAlC.
In this embodiment, the electrode 351 and the gate electrode layer 361 are made of the same material, so that the electrode 351 and the gate electrode layer 361 can be formed in the same step, thereby improving the process efficiency and saving the process cost.
The electrode 351 includes a work function layer (not shown), and an electrode layer (not shown) on the work function layer for electrically leading out the electrode 351.
The dielectric layer 401 is used for isolation between adjacent devices.
In this embodiment, the dielectric layer 401 is filled in the trench and covers the sidewall of the protection layer 341, so as to improve the flatness of the top of the resistor structure 301, and provide a better process platform for the subsequent processes.
In this embodiment, the material of the dielectric layer 401 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
It should be noted that, in general, the process of forming the dielectric layer 401 includes a process of planarizing the resistor structure 301 and the dielectric layer 401, in this embodiment, a trench is formed on the top of the resistor structure 301, so that a contact area between a polishing pad and the top surface of the resistor structure 301 during the planarization process is reduced, and thus, a probability of a recess defect occurring on the top surface of the resistor structure 301 is reduced.
In this embodiment, the semiconductor structure further includes: and the covering layer 501 covers the dielectric layer 401, the resistance structure 301 and the electrode 351.
In this embodiment, the covering layer 401 correspondingly covers the gate electrode layer 361.
The capping layer 501 is used to provide a process platform for forming a conductive plug.
The material of the capping layer 501 is an insulating material, and in this embodiment, the material of the capping layer 501 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
In this embodiment, the semiconductor structure further includes: and a conductive plug 511 penetrating the cover 501 on the top of the electrode 351 and electrically connecting the electrode 351.
The conductive plug 511 is used to electrically connect the electrodes 351.
In this embodiment, the material of the conductive plug 511 includes tungsten, ruthenium, or cobalt.
It should be noted that, generally, the process of forming the electrode 351 includes a process of planarizing the resistive structure 301 and the electrode 351, in this embodiment, the top of the resistive structure 301 is formed with a trench, so that the contact area between the polishing pad and the top surface of the resistive structure 301 during the planarization process is reduced, thereby reducing the probability of the occurrence of the dishing defect on the top surface of the resistive structure 301.
It should be noted that, in this embodiment, the flatness of the top surface of the resistor structure 301 is improved, so that the quality of forming the electrode 351 is improved, and further, the reliability of the electrical connection between the conductive plug 511 and the electrode 351 is improved, and the performance of the semiconductor structure is further improved.
Fig. 8 to 20 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 8, a semiconductor substrate 100 is provided, which includes a resistance region 100R, and a resistance structure material layer 200 is formed on the semiconductor substrate 100 of the resistance region 100R.
The semiconductor substrate 100 provides a process operation basis for subsequent processes.
In this embodiment, the material of the semiconductor substrate 100 is silicon, in other embodiments, the material of the semiconductor substrate may also be one or more of germanium, silicon carbide, gallium arsenide, and indium gallium, and the semiconductor substrate may also be another type of semiconductor substrate such as a silicon-on-insulator semiconductor substrate or a germanium-on-insulator semiconductor substrate. The material of the semiconductor substrate 100 may be a material suitable for process requirements or easy integration.
In this embodiment, the semiconductor substrate 100 includes a resistor region 100R, and the resistor region 100R is used to form a resistor structure.
In this embodiment, the semiconductor substrate 100 further includes a device region 100H, and the device region 100H is used for forming a MOS transistor. MOS transistors are among others active devices in integrated circuits.
In this embodiment, the device region 100H is a low voltage device region for forming a low voltage device. As an example, the operating voltage of the low voltage device is less than 2V.
It should be noted that the semiconductor substrate 100 may further include a high voltage device region (not shown) for forming a high voltage device. The operating voltage of the high-voltage device is greater than the operating voltage of the low-voltage device. As an example, the operating voltage of the high voltage device is greater than 10V.
It should be further noted that, in this embodiment, the metal gate structure of the second device region 100H is formed by a process of forming a high-k gate dielectric layer and then forming a metal gate (high-k first metal gate last), and the resistance structure formed in the resistance region 100R and the dummy gate layer formed in the second device region 100H are formed together.
Therefore, in this embodiment, a gate dielectric layer 210 is further formed between the resistive structure material layer 200 and the semiconductor substrate 100, and the resistive structure material layer 200 includes a metal barrier layer 220 and a top resistive layer 250 on the metal barrier layer 220.
The gate dielectric layer 210 is used for isolating a subsequently formed electrode from the semiconductor substrate 100 and a subsequently formed gate electrode layer from the semiconductor substrate 100.
The material of the gate dielectric layer 210 comprises HfO 2 、ZrO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al 2 O 3 、SiO 2 And La 2 O 3 One or more of (a). In this embodiment, the gate dielectric layer 210 includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. Wherein, the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide. Specifically, the high-k dielectric material comprises HfO 2 、ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al 2 O 3 And the like.
It should be noted that the gate dielectric layer 210 may further include a gate oxide layer located between the high-k gate dielectric layer and the semiconductor substrate 101. As an example, the material of the gate oxide layer is silicon oxide.
The metal barrier layer 220 is used for isolating the gate dielectric layer 210 from a subsequently formed electrode and the gate dielectric layer 210 from a subsequently formed gate electrode layer to protect the gate dielectric layer 210, and the metal barrier layer 220 is also used for blocking easily-diffusible ions (e.g., al ions) in the electrode and the gate electrode layer from diffusing into the gate dielectric layer 210.
Specifically, the material of the metal barrier layer 220 includes one or both of titanium nitride (TiN) and silicon-doped titanium nitride (TiSiN). In this embodiment, the metal barrier layer 220 is made of titanium nitride.
The resistive structure material layer 200 is used for forming a resistive structure, and the metal barrier layer 220 of the resistive region 100R is used as a bottom resistive layer.
In this embodiment, the material of the top resistive layer 250 includes polysilicon.
In this embodiment, the resistance structure material layer 200 is further formed on the semiconductor substrate 100 in the device region 100H for preparing a dummy gate layer to be formed in the device region 100H. The dummy gate layer is used for occupying a space position for forming the metal gate structure.
In this embodiment, an isolation structure 110 is further formed in the semiconductor substrate 100 of the resistor region 101R.
A resistor structure is subsequently formed on the isolation structure 110, the isolation structure 110 is used to isolate the resistor structure from the semiconductor substrate 100 to prevent a short circuit between the resistor structure and a well (well) region in the semiconductor substrate 100, and the isolation structure 110 is also used to achieve isolation between different devices, for example, in a CMOS manufacturing process, an isolation structure is typically formed between an NMOS transistor and a PMOS transistor. Specifically, the Isolation structure 110 is a Shallow Trench Isolation (STI) structure.
The isolation structure 110 is made of an insulating material. In this embodiment, the isolation structure 110 includes silicon oxide or silicon oxynitride.
Referring to fig. 9 and 10 in combination, fig. 10 is a top view of the resistive structure material layer 200 of the resistive region 100R, and fig. 9 is a cross-sectional view of fig. 10 based on the AA direction, in the resistive region 100R, one or more parallel trenches 230 are formed in the resistive structure material layer 200, and the trenches 230 penetrate through a portion of the thickness of the resistive structure material layer 200.
After the resistive structure material layer 200 is patterned to form a resistive structure in the resistive region 100R, the trench 230 is located in the resistive structure.
In the process of forming the resistor structure and the dielectric layer, a process of planarizing the resistor structure and the dielectric layer is usually included, and during planarization, if the size of the resistor structure is large, severe dishing defects (sinking defects) easily occur on the top surface of the resistor structure, and in this embodiment, the electrodes are formed on two sides of the resistor structure along the extending direction of the resistor structure, and the electrodes are only used for electrically connecting the resistor structure, the size of the electrodes is small, so that the size of the remaining resistor structure is large, and dishing defects are more easily occurred, and therefore, by forming the grooves 230 on the top of the resistor structure, the contact area between the polishing pad and the top surface of the resistor structure in the planarization process is reduced, so that the probability of dishing defects occurring on the top surface of the resistor structure is reduced, the flatness of the top surface of the resistor structure is improved, the integrity of the resistor structure is ensured, the probability of resistance value deviation of the resistor structure is reduced, and the performance of the semiconductor structure is improved.
In this embodiment, the trench 230 penetrates through a part of the thickness of the resistance structure material layer 200, and a part of the thickness of the resistance structure material layer 200 is remained, so as to maintain the normal performance and resistance of the subsequent resistance structure, and protect the metal barrier layer 220 located under the resistance structure material layer 200, so as to reduce or avoid the influence on the resistance value of the resistance structure.
Specifically, the trench 230 runs through a portion of the thickness of the top resistive layer 250.
In this embodiment, one or more parallel trenches 230 are formed using a dry etch process.
The dry etching process has anisotropic etching characteristics, so that the dry etching process is selected, which is favorable for reducing the damage to the remaining resistance structure material layer 200 on the side of the groove 230, and meanwhile, the dry etching process has more etching directionality, and is favorable for improving the sidewall morphology quality and the size precision of the groove 230.
In this embodiment, the extending direction of the plurality of parallel arranged trenches 230 is the same as the extending direction of the resistance structure material layer 200, so that the contact area with the top surface of the resistance structure 301 in the planarization process can be reduced under the condition that a small number of trenches are formed, the process cost can be saved, the process complexity can be reduced, and the process efficiency can be improved.
In this embodiment, the arrangement direction of the plurality of parallel-arranged trenches 230 is perpendicular to the extending direction of the resistance structure material layer 200, and then a sufficient number of the plurality of trenches 230 are arranged in the direction perpendicular to the extending direction of the resistance structure material layer 200 according to the width of the resistance structure 300, so as to greatly reduce the contact area with the top surface of the resistance structure during the planarization process, thereby reducing the probability of the occurrence of the recess defect on the top surface of the resistance structure.
It should be noted that the depth h of the groove 230 should not be too large or too small. If the depth h of the trench 230 is too large, the removed resistance structure material layer 200 is too much, which is likely to cause damage to the metal barrier layer 220 under the trench 230, and then affects the resistance value of the resistance structure 300; if the depth h of the trench 230 is too small, the height of the raised resistor structure around the trench 230 is too small, and the raised resistor structure around the trench 230 is easily removed in the planarization process of the dielectric layer 401, so that the resistor structure at the bottom of the trench 230 is easily contacted in the planarization process, the contact area with the top surface of the resistor structure in the planarization process is difficult to reduce, and the probability of the occurrence of the dent defect on the top surface of the resistor structure is difficult to reduce. Therefore, in the present embodiment, the depth h of the trench 230 is 1/4 to 1/3 of the thickness of the resistive structure material layer 200.
Note that the width w1 of the trench 230 cannot be too large or too small. If the width w1 of the trench 230 is too large, a dielectric layer may be formed in the trench 230 in the following step, and the dielectric layer in the trench is prone to have a serious top surface depression problem during the planarization process; if the width w1 of the trench 230 is too small, the line width of the raised resistor structure around the trench 230 is still large, so that it is difficult to reduce the contact area with the top surface of the resistor structure during the planarization process, and further difficult to reduce the probability of the occurrence of the recess defect on the top surface of the resistor structure, and the process difficulty of the photolithography process and the dry etching process used in forming the trench 230 is also easily increased. Therefore, in the present embodiment, the width w1 of the trench 230 is 0.15 μm to 2 μm.
Meanwhile, it should be noted that the distance w2 between adjacent trenches 230 cannot be too large or too small. If the distance w2 between adjacent trenches 230 is too large, that is, the line width of the raised resistor structure around the trench 230 is still large, it is difficult to reduce the contact area with the top surface of the resistor structure during the planarization process, and therefore it is difficult to reduce the probability of the occurrence of the dishing defect on the top surface of the resistor structure, and accordingly, the width w1 of the trench 230 is too small; if the distance w2 between adjacent trenches 230 is too small, the width w1 of the formed trench 230 is too large, and a dielectric layer is formed in the trench 230 subsequently, so that the dielectric layer in the trench 230 is prone to have a serious top surface recess problem during planarization, and the process difficulty of the photolithography process and the dry etching process for forming the trench 230 is also prone to increase. Therefore, in the present embodiment, the distance w2 between adjacent trenches 230 is 0.15 μm to 2 μm.
Referring to fig. 11 and 12 in combination, fig. 11 and 12 are cross-sectional views based on fig. 9, after the trench 230 is formed, the resistive structure material layer 200 is patterned, a portion of the resistive structure material layer 200 outside the trench 230 is removed, and a portion of the resistive structure material layer 200 including the trench 230 is remained as the resistive structure 300.
The part of the resistance structure material layer 200 including the trench 230 is reserved as the resistance structure 300, so that in the subsequent planarization process, the contact area between the polishing pad and the top surface of the resistance structure 300 is reduced, the probability of the occurrence of the recess defect on the top surface of the resistance structure 300 is reduced, the flatness of the top surface of the resistance structure 300 is improved, the integrity of the resistance structure 300 is ensured, meanwhile, the integrity of the metal barrier layer 220 is protected, the probability of the deviation of the resistance value of the resistance structure 300 is reduced, and the performance of the semiconductor structure is improved.
The resistive structure 300 acts as a passive device in an integrated circuit.
In this embodiment, the remaining metal barrier layer 220 and the top resistive layer 250 in the resistor region 100R are used as the resistor structure 300, and the metal barrier layer 220 is used as the bottom resistive layer in the resistor structure 300.
In this embodiment, the resistor structure 300 is located on the isolation structure 110 in the resistor 100R region, so that the resistor structure 300 is insulated from the semiconductor substrate 100.
In this embodiment, the resistive structure material layer 200 directly forms the resistive structure 300, and thus, the material of the top resistive layer 250 includes polysilicon.
It should be noted that, since the resistance of the top resistive layer 250 is much larger than the resistance of the metal barrier layer 220, the current in the resistor structure 300 mainly flows through the metal barrier layer 220, and accordingly, compared with the top resistive layer 250, the metal barrier layer 220 has a larger influence on the resistance of the resistor structure 300.
In this embodiment, after forming the trench 230, before forming a dielectric layer on the semiconductor substrate 100 at the side of the resistor structure 300, the method further includes: a protective layer 340 is formed on the sidewalls of the trench 230.
In the process of planarizing the resistor structure 300 and the dielectric layer 400, the protective layer 340 protects the resistor structure 300 on the side wall of the trench, so that the probability of over-grinding of the resistor structure 300 is reduced, the probability of the top surface of the resistor structure 300 having a recess defect is further effectively reduced, the flatness of the top surface of the resistor structure 300 is improved, and the performance of the semiconductor structure is further improved.
In this embodiment, the protection layer 340 is formed before the dielectric layer is formed on the semiconductor substrate 100 at the side of the resistor structure 300, and then the protection layer 340 conformally covers the sidewall and the bottom of the trench 230, so that the protection layer 340 protects the resistor structure 300 at the bottom of the protection layer 340 while protecting the resistor structure 300 at the sidewall of the trench 230.
In this embodiment, the material of the protection layer 340 includes silicon nitride or silicon oxynitride.
The silicon nitride has high hardness, and can play a good role in protecting the resistance structure 300 on the side wall and the bottom of the trench in the planarization process.
Specifically, in this embodiment, the protection layer 340 is formed before the patterning of the resistance structure material layer 200, so that the protection layer 340 is also used as an etching mask for patterning the resistance structure material layer 200, which simplifies the process steps.
Referring to fig. 11, the step of forming the protection layer 340 includes: a layer of protective material 240 is formed on the layer of resistive structure material 200, the layer of protective material 240 conformally covering the bottom and sidewalls of the trench 230 and the top of the layer of resistive structure material 200.
The protective material layer 240 is used to form a protective layer 340.
In this embodiment, the protective material layer 240 is formed by an atomic layer deposition process.
The protective material layer 240 formed by the atomic layer deposition process has good thickness uniformity and good step coverage (step coverage) capability, so that the protective material layer 240 can conformally cover the bottom and the sidewall of the trench 230 and the top of the resistance structure material layer 200.
Referring to fig. 12, a portion of the protective material layer 240 outside the trench 230 is removed, forming a protective layer 340 that conformally covers the bottom and sidewalls of the trench 230 and extends over a portion of the top of the resistive material layer 200.
The protective layer 340 is also used as an etching mask for patterning the resistive structure material layer 200.
In this embodiment, a dry etching process is used to remove a portion of the protective material layer 240 outside the trench 230.
The dry etching process has anisotropic etching characteristics, so that the dry etching process is selected to be beneficial to reducing damage to the resistance structure material layer 200, meanwhile, the dry etching process has etching directionality, and the improvement of the sidewall morphology quality and the size precision of the protective layer 340 and the resistance structure 300 is facilitated.
With continued reference to fig. 12, the step of patterning the resistive structural material layer 200 includes: and removing the resistance structure material layer 200 exposed by the protective layer 340 by using the protective layer 340 as a mask.
The protective layer 340 is used as a mask to form the resistor structure 300, which is beneficial to forming the resistor structure 300 with high dimensional accuracy.
In this embodiment, in the step of patterning the resistive structure material layer 200, a portion of the top resistive layer 250 on the semiconductor substrate 100 in the device region 100H is also reserved as the dummy gate layer 310.
The dummy gate layer 310 occupies a space for forming a gate electrode layer in a subsequent process.
In this embodiment, the dummy gate layer 310 is formed in the same step as the resistor structure 300, thereby simplifying the process steps for forming the semiconductor structure. The dummy gate layer 310 is made of the same material as the top resistive layer 250.
In this embodiment, after patterning the resistance structure material layer 200 and before forming a dielectric layer subsequently, the method further includes: and removing the gate dielectric layer 210 exposed by the resistor structure 300 and the dummy gate layer 310.
Referring to fig. 13, a dielectric layer 400 is formed on the semiconductor substrate 100 at the side of the resistor structure 300, the dielectric layer 400 is further filled in the trench 230, and the dielectric layer 400 is exposed at the top of the resistor structure 300.
The dielectric layer 400 is used for isolation between adjacent devices.
In this embodiment, the dielectric layer 400 is formed by a chemical vapor deposition process.
In this embodiment, the dielectric layer 400 is filled in the trench 230 and covers the sidewall of the protection layer 340, so as to improve the flatness of the top of the resistor structure 300 and provide a better process platform for subsequent processes.
In this embodiment, the dielectric layer 400 is exposed at the top of the resistor structure 300 to prepare for removing a portion of the resistor structure 300 to form an electrode.
In this embodiment, the dielectric layer 400 further exposes the top of the dummy gate layer 310, so as to prepare for removing the dummy gate layer 310 subsequently.
In this embodiment, the material of the interlayer dielectric layer 400 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.
In this embodiment, the step of forming the dielectric 400 layer includes: a dielectric material layer (not shown) covering the resistor structure 300 is formed on the semiconductor substrate 100.
The dielectric material layer is used to form the dielectric layer 400.
In this embodiment, the material of the interlayer dielectric material layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.
In this embodiment, the step of forming the dielectric layer 400 further includes: and carrying out planarization treatment on the protective layer 340 and the dielectric material layer on the top of the resistor structure 300, and removing the protective layer 340 and the dielectric material layer higher than the top of the resistor structure 300.
The protective layer 340 and the dielectric material layer on the top of the resistor structure 300 are subjected to planarization treatment, so that the top of the resistor structure 300 is exposed, an electrode is formed in the resistor structure 300 in the following step, and meanwhile, the resistor structure 300 with high top surface flatness is formed, so that a good process platform is provided for the subsequent manufacture.
It should be noted that, during the process of planarizing the top of the dielectric material layer, when the depth of the formed trench 230 is small or the dielectric material layer is excessively polished, the dielectric layer 400 in the trench 230 may be removed, so that the protective layer 340 remains in the trench 230. In this embodiment, the dielectric layer 400 is remained in the trench 230.
With reference to fig. 14 to 16, fig. 14 is a top view of the resistor structure 300, fig. 15 is a cross-sectional view of fig. 14 based on the AA direction, fig. 16 is a cross-sectional view of fig. 14 based on the BB direction, and along the extending direction of the resistor structure 300, a portion of the resistor structure 300 at the interface between the resistor structure 300 and the dielectric layer 400 is removed, so as to form an opening 330 surrounded by the dielectric layer 400 and the remaining resistor structure 300.
The openings 330 are used to provide spatial locations for subsequently formed electrodes.
In this embodiment, the opening 330 is formed by a dry etching process.
In this embodiment, in the step of removing a part of the resistor structure 300 at the interface between the resistor structure 300 and the dielectric layer 400, a part of the top resistive layer 250 at the interface between the resistor structure 300 and the dielectric layer 400 is removed to form an opening 330 surrounded by the dielectric layer 400, the metal barrier layer 220 and the remaining top resistive layer 250, and the dummy gate layer 310 is also removed to form a gate opening 320.
The gate opening 320 is used to provide a spatial location for the subsequent formation of a gate electrode layer.
In this embodiment, the gate opening 320 is formed by a dry etching process.
Referring to fig. 17 to 19 in combination, fig. 17 is a top view of the resistor structure 300, fig. 16 is a cross-sectional view of fig. 17 based on the AA direction, and fig. 19 is a cross-sectional view of fig. 17 based on the BB direction, and the electrode 350 is formed in the opening 330.
In this embodiment, along the extending direction of the resistor structure 300, the electrode 350 is located between the resistor structure 300 and the dielectric layer 400, that is, the electrode 350 is connected to the end of the resistor structure 300, specifically, the electrode 350 is located on the metal barrier layer 220 on both sides of the top resistor layer 250.
The electrodes 350 are located at the ends of the resistive structure 300. Since the longer the length of the resistor structure 300 is, the larger the resistance of the resistor structure 300 is, and the electrode 350 is located at the end of the resistor structure 300, the length of the resistor structure 300 can be maximized, so that the resistor structure 300 obtains a larger resistance.
The electrodes 350 are used to make electrical connections to conductive plugs and thus to make electrical connections between the resistive structure 300 and other circuitry.
In this embodiment, the material of the electrode 350 includes a metal material. The metal material has better conductivity, which is beneficial to improving the electrical connection performance of the resistor structure 300 and an external interconnection structure, thereby improving the electrical performance of the semiconductor structure.
In this embodiment, the electrode 350 and the gate electrode layer of the MOS transistor have the same material and the same stack structure, so that the electrode 350 and the gate electrode layer of the MOS transistor can be formed in the same process. For example, the device gate structure adopted in the low-voltage device region is a metal gate structure, and the metal gate structure is favorable for improving the electrical performance of the MOS transistor and reducing the leakage current.
Accordingly, in the present embodiment, the electrode 350 is formed simultaneously in the step of forming the gate electrode layer of the MOS transistor, thereby simplifying the process steps of forming the semiconductor structure.
With continued reference to fig. 18, the step of forming an electrode 350 in the opening 330 further includes: a gate electrode layer 360 is formed in the gate opening 320.
The gate electrode layer 360 is used to control the on/off of the channel of the transistor.
In this embodiment, the gate electrode layer 360 and the resistor structure 300 are formed in the same step, thereby simplifying the process steps for forming the semiconductor structure. The gate electrode layer 360 is therefore the same material as the electrode 350.
In this embodiment, the metal gate structure is formed by a process of forming a high-k gate dielectric layer and then forming a metal gate (high-k first metal gate last), so that the metal gate layer 360 includes a work function layer (not shown) on the high-k gate dielectric layer and an electrode layer (not shown) on the work function layer. The work function layer is used for adjusting the threshold voltage of the MOS transistor, and the electrode layer is used for electrically leading out the gate electrode layer 361.
In this embodiment, in the device region 100H, the gate dielectric layer 210, the metal blocking layer 220 and the gate electrode layer 360 form a metal gate structure.
It should be noted that, generally, the process of forming the electrode 350 and the gate electrode layer 360 includes a process of planarizing the resistor structure 300, the electrode 350 and the gate electrode layer 360, in this embodiment, a trench is formed at the top of the resistor structure 300, so that the contact area between the polishing pad and the top surface of the resistor structure 300 is reduced in the planarization process, and the probability of the occurrence of the recess defect on the top surface of the resistor structure 300 is reduced.
Referring to fig. 20, fig. 20 is a sectional view based on fig. 19, a conductive plug 510 electrically connected to the electrode 350 is formed on top of the electrode 350.
The conductive plug 510 is used to electrically connect the electrodes 350.
In this embodiment, the material of the conductive plug 510 includes tungsten, ruthenium, or cobalt.
In this embodiment, before forming the conductive plug 510, the method further includes: a capping layer 500 is formed overlying the dielectric layer 340, resistive structure 300, and electrode 350.
The capping layer 500 is used to provide a process platform for forming the conductive plug 510.
The material of the cover layer 500 is an insulating material. In this embodiment, the material of the cap layer 500 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
In this embodiment, the covering layer 500 also covers the gate electrode layer 360.
In this embodiment, the step of forming a conductive plug 510 electrically connected to the electrode 350 on top of the electrode 350 includes: forming a covering layer 500 penetrating the top of the electrode 350 and exposing a conductive hole (not labeled) of the electrode 350; the conductive plug 510 is formed in the conductive hole.
The conductive plug 510 penetrates the cover layer 500 on top of the electrode 350, thereby making an electrical connection with the electrode 350.
It should be noted that, in this embodiment, the flatness of the top surface of the resistor structure 300 is improved, so as to improve the formation quality of the electrode 350, further improve the electrical connection reliability between the conductive plug 510 and the electrode 350, and further improve the performance of the semiconductor structure.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A semiconductor structure, comprising:
a semiconductor substrate including a resistance region;
the resistor structure is positioned on the semiconductor substrate of the resistor area, wherein one or more parallel grooves are formed at the top of the resistor structure, and the grooves penetrate through part of the thickness of the resistor structure;
the electrodes are positioned in the resistance area, are positioned on two sides of the resistance structure along the extension direction of the resistance structure, and are connected with the side wall of the resistance structure;
and the dielectric layer is positioned on the semiconductor substrate at the side parts of the resistance structure and the electrode, is also filled in the groove, and is exposed out of the tops of the resistance structure and the electrode.
2. The semiconductor structure of claim 1, further comprising: the protective layer is positioned on the side wall of the groove;
the dielectric layer is filled in the groove and covers the side wall of the protective layer.
3. The semiconductor structure of claim 2, in which the protective layer conformally covers sidewalls and a bottom of the trench.
4. The semiconductor structure of claim 1, wherein the plurality of parallel arranged trenches extend in the same direction as the resistive structure;
the arrangement direction of the plurality of parallel grooves is perpendicular to the extending direction of the resistor structure.
5. The semiconductor structure of claim 1, further comprising an isolation structure in the semiconductor substrate of the resistive region;
the resistance structure is located on the isolation structure of the resistance region.
6. The semiconductor structure of claim 1, wherein the semiconductor substrate further comprises a device region;
the semiconductor structure further includes: the gate dielectric layer is positioned on the semiconductor substrate of the device area and the resistance area; the metal barrier layer is positioned on the gate dielectric layer; the gate electrode layer is positioned on the metal barrier layer of the device region;
the resistor structure comprises the metal barrier layer positioned in the resistor area and a top resistor layer positioned on the metal barrier layer, and the metal barrier layer is used as a bottom resistor layer in the resistor structure;
the electrodes are located on the metal barrier layers on two sides of the top resistance layer, and the electrodes and the gate electrode layers are made of the same material.
7. The semiconductor structure of claim 1, wherein a depth of the trench is 1/4 to 1/3 of a thickness of the resistive structure.
8. The semiconductor structure of claim 1, wherein the width of the trenches is 0.15 μm to 2 μm, and a distance between adjacent trenches is 0.15 μm to 2 μm.
9. The semiconductor structure of claim 2, wherein a material of the protective layer comprises silicon nitride or silicon oxynitride.
10. The semiconductor structure of claim 6, wherein the material of the metal barrier layer comprises one or both of titanium nitride and silicon-doped titanium nitride; the material of the top resistive layer comprises polysilicon.
11. The semiconductor structure of claim 1, wherein a material of the electrode comprises one or more of TiN, taN, ta, ti, tiAl, W, AL, tiSiN, and TiAlC.
12. The semiconductor structure of claim 5, wherein a material of the isolation structure comprises silicon oxide or silicon oxynitride.
13. The semiconductor structure of claim 6, in which a material of the gate dielectric layer comprises HfO 2 、ZrO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al 2 O 3 、SiO 2 And La 2 O 3 One or more of (a).
14. A method of forming a semiconductor structure, comprising:
providing a semiconductor substrate comprising a resistance area, wherein a resistance structure material layer is formed on the semiconductor substrate of the resistance area;
forming one or more parallel trenches in the resistive structure material layer in the resistive region, the trenches extending through a portion of the thickness of the resistive structure material layer;
after the groove is formed, patterning the resistance structure material layer, removing part of the resistance structure material layer outside the groove, and reserving the part of the resistance structure material layer containing the groove as a resistance structure;
forming a dielectric layer on the semiconductor substrate on the side part of the resistance structure, wherein the dielectric layer is also filled in the groove and is exposed out of the top part of the resistance structure;
removing part of the resistor structure at the junction of the resistor structure and the dielectric layer along the extension direction of the resistor structure to form an opening surrounded by the dielectric layer and the rest resistor structure;
an electrode is formed in the opening.
15. The method of forming a semiconductor structure of claim 14, wherein after forming the trench, prior to forming a dielectric layer on the semiconductor substrate at the side of the resistive structure, further comprising: and forming a protective layer on the side wall of the groove.
16. The method of forming a semiconductor structure of claim 15, wherein the protective layer is formed before patterning the resistive structure material layer;
the step of forming the protective layer includes: forming a protective material layer on the resistive structure material layer, the protective material layer conformally covering the bottom and sidewalls of the trench and the top of the resistive structure material layer;
removing part of the protective material layer outside the groove to form a protective layer which conformally covers the bottom and the side wall of the groove and extends to cover part of the top of the resistance material layer;
the step of patterning the resistive structure material layer includes: and removing the resistance structure material layer exposed out of the protective layer by taking the protective layer as a mask.
17. The method of forming a semiconductor structure of claim 16, wherein forming the dielectric layer comprises: forming a dielectric material layer covering the resistance structure on the semiconductor substrate;
and carrying out planarization treatment on the protective layer and the dielectric material layer on the top of the resistor structure, and removing the protective layer and the dielectric material layer which are higher than the top of the resistor structure.
18. The method of forming a semiconductor structure according to claim 14, wherein in the step of providing the semiconductor substrate, the semiconductor substrate further comprises a device region, the resistive structure material layer is further formed on the semiconductor substrate in the device region, the resistive structure material layer comprises a metal barrier layer and a top resistive layer on the metal barrier layer, and a gate dielectric layer is further formed between the resistive structure material layer and the semiconductor substrate;
in the step of patterning the resistance structure material layer, the residual metal barrier layer and the top resistance layer in the resistance region are used as resistance structures, the metal barrier layer is used as a bottom resistance layer in the resistance structures, and part of the top resistance layer on the semiconductor substrate in the device region is reserved as a pseudo gate layer;
after the patterning of the resistance structure material layer and before the forming of the dielectric layer, the method further comprises the following steps: removing the exposed gate dielectric layer of the resistance structure and the dummy gate layer;
in the step of forming the dielectric layer, the dielectric layer is exposed out of the top of the pseudo gate layer;
in the step of removing part of the resistor structure at the junction of the resistor structure and the dielectric layer, part of the top resistor layer at the junction of the resistor structure and the dielectric layer is removed to form an opening surrounded by the dielectric layer, the metal barrier layer and the remaining top resistor layer, the dummy gate layer is also removed, and a gate opening is formed in the device region;
in the step of forming an electrode in the opening, further comprising: a gate electrode layer is formed in the gate opening.
19. The method of claim 18, wherein the metal barrier layer comprises one or both of titanium nitride and silicon-doped titanium nitride, and the top resistive layer comprises polysilicon.
20. The method of forming a semiconductor structure of claim 16, wherein the layer of protective material is formed using an atomic layer deposition process.
CN202110674533.8A 2021-06-17 2021-06-17 Semiconductor structure and forming method thereof Pending CN115498037A (en)

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