CN115497836B - Semiconductor packaging method, packaging structure and supporting sheet for semiconductor packaging - Google Patents

Semiconductor packaging method, packaging structure and supporting sheet for semiconductor packaging Download PDF

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Publication number
CN115497836B
CN115497836B CN202211461686.5A CN202211461686A CN115497836B CN 115497836 B CN115497836 B CN 115497836B CN 202211461686 A CN202211461686 A CN 202211461686A CN 115497836 B CN115497836 B CN 115497836B
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layer
chips
temporary
bearing plate
plastic
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CN115497836A (en
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徐立
孙超
徐虹
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Jiangyin Changdian Advanced Packaging Co Ltd
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Jiangyin Changdian Advanced Packaging Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

The invention discloses a semiconductor packaging method, a packaging structure and a supporting sheet for semiconductor packaging, wherein the method comprises the steps of providing a temporary bearing plate, wherein the temporary bearing plate is provided with a plurality of chips, the temporary bearing plate is provided with a chip layout area and an edge area surrounding the chip layout area, and the chips are positioned on the chip layout area; forming a plastic layer by using a vacuum film pressing process, wherein the plastic layer covers the chip layout area and the edge area; providing a supporting sheet, wherein the supporting sheet is provided with an auxiliary piece corresponding to the edge area of the temporary bearing plate, the supporting sheet is combined with the temporary bearing plate, and the auxiliary piece is embedded into the plastic sealing layer and surrounds the chip layout area to assist in increasing the thickness of the plastic sealing layer in the edge area; the temporary carrier plate is removed. The invention can avoid the problem of falling off of plastic packaging materials, reduces the operation difficulty of the packaging process and improves the production yield.

Description

Semiconductor packaging method, packaging structure and supporting sheet for semiconductor packaging
Technical Field
The present invention relates to the field of packaging technologies, and in particular, to a semiconductor packaging method, a semiconductor packaging structure, and a supporting sheet for semiconductor packaging.
Background
The vacuum film pressing process is a plastic packaging process for pressing and filling under the vacuum environment by utilizing the temperature regulation and the pressure effect. Compared with the traditional plastic packaging process, the vacuum film pressing process has the advantages of no need of customizing a die, flexible thickness and size adjustment and the like. However, in the vacuum film pressing process, the molding of the molding compound depends on the physical properties of the material in a molten state and the force application mode of the vacuum film pressing machine in the molding process.
When the wafer is packaged, the chips cannot be distributed due to the influence of the chip size, the packaging process and the like, and an edge area with at least 3mm from the edge of the wafer inwards. The stress state of the molten plastic package material in the edge area is different from that of the chip layout area, and the thickness of the plastic package material in the edge area is obviously lower than that of the chip layout area after the plastic package material is molded. Because the plastic packaging material of the edge area of the wafer is thinner, the problem of falling off can occur in the subsequent flow, so that the packaging process is difficult to operate, and the production yield is affected.
Disclosure of Invention
The present invention is directed to a semiconductor packaging method and a semiconductor packaging supporting sheet, which solve the above-mentioned problems.
In order to achieve the above object, the present invention provides a semiconductor packaging method, which comprises,
step A, providing a temporary bearing plate, wherein the temporary bearing plate is provided with a plurality of chips, the temporary bearing plate is provided with a chip layout area and an edge area surrounding the chip layout area, and the chips are positioned on the chip layout area;
step B, forming a plastic sealing layer by utilizing a vacuum film pressing process, wherein the plastic sealing layer covers the chip layout area and the edge area;
step C, providing a supporting sheet, wherein the supporting sheet is provided with an annular auxiliary piece corresponding to the edge area of the temporary bearing plate, the supporting sheet is combined with the temporary bearing plate, and the auxiliary piece is embedded into the plastic sealing layer and surrounds the chip layout area to assist in increasing the thickness of the plastic sealing layer in the edge area; and
and D, removing the temporary bearing plate.
As a further improvement of an embodiment of the present invention, step D further includes dicing the plurality of chips into a plurality of individual packages, and leaving no auxiliary member on each package.
As a further improvement of an embodiment of the present invention, in step C, when the auxiliary member is embedded in the plastic layer, a part of the plastic material in the plastic layer overflows from the edge area, and step C further includes trimming the plastic layer.
As a further improvement of an embodiment of the present invention, before the step D, baking and curing the plastic sealing layer; and the difference of the total thickness of the cured plastic sealing layer is less than or equal to 20um.
As a further improvement of an embodiment of the present invention, the auxiliary member is a glue dispensing layer or a film laminating layer.
As a further development of an embodiment of the invention, the molding layer has a first thickness h1 and the auxiliary element has a second thickness h2, wherein h1×0.1 < h2 < h1×0.8.
As a further development of an embodiment of the invention, the edge region has a first width w1 and the auxiliary element has a second width w2, wherein w1×0.5 < w2 < w1.
As a further improvement of an embodiment of the present invention, the height of the auxiliary element is between 40um and 200um, and the width of the auxiliary element is between 1700um and 2970 um.
As a further improvement of an embodiment of the present invention, after the temporary carrier plate is removed, the step D further includes wiring and ball mounting on the plurality of chips; or, a high-density rewiring layer is arranged on the chips, and the high-density rewiring layer is electrically connected with the chips through a plurality of microcontacts.
As a further improvement of an embodiment of the present invention, in the step a, the temporary carrier plate includes a carrier sheet and a temporary bonding film separable therefrom, the plurality of chips are disposed on the temporary bonding film, and the temporary bonding film is laid on the carrier sheet; step D includes removing the carrier sheet and tearing off the temporary bonding film.
As a further improvement of an embodiment of the present invention, a redistribution layer is prefabricated on the supporting sheet, at least two chips of the plurality of chips are provided with electrodes, and in step C, the redistribution layer is electrically connected with the electrodes when the supporting sheet is combined with the temporary carrier plate; and D, cutting the at least two chips into the same packaging body.
In addition, the invention also provides a supporting sheet for semiconductor packaging, which is used for being combined with a temporary bearing plate, wherein the temporary bearing plate is provided with a plurality of chips, the temporary bearing plate is provided with a chip layout area and an edge area surrounding the chip layout area, and the chips are positioned on the chip layout area; the temporary bearing plate is also provided with a plastic layer formed by a vacuum film pressing process, and the plastic layer covers the chip layout area and the edge area; the support piece corresponds the marginal area of interim loading board is provided with annular auxiliary member, the support piece with interim loading board combines, the auxiliary member embedding in the plastic envelope layer and encircle the chip overall arrangement area is in order to assist to promote the plastic envelope layer in the thickness of marginal area.
As a further improvement of an embodiment of the present invention, the auxiliary member is a glue dispensing layer or a film laminating layer.
As a further improvement of an embodiment of the present invention, the height of the auxiliary element is between 40um and 200um, and the width of the auxiliary element is between 1700um and 2970 um.
In addition, the invention also provides a semiconductor packaging structure which comprises a supporting sheet, at least two chips and a plastic sealing layer. A rewiring layer is pre-arranged on the supporting sheet, and an auxiliary piece is arranged on at least a partial edge of the supporting sheet; the at least two chips are provided with electrodes; the electrode is electrically connected with the rewiring layer; the plastic layer covers the at least two chips, and the auxiliary piece is embedded in the plastic layer and at least partially surrounds the at least two chips.
According to the semiconductor packaging method, the packaging structure and the supporting sheet for semiconductor packaging, the annular auxiliary piece is arranged on the supporting sheet, when the supporting sheet is combined with the temporary bearing plate, the auxiliary piece is embedded into the plastic sealing layer to achieve the flow limiting and supporting effects of the mold on the plastic sealing material in the similar plastic sealing process, so that the vacuum film pressing process can optimize the forming condition of the edge plastic sealing material on the premise of keeping the original advantages. Therefore, the problem of falling of plastic packaging materials is avoided, the difficulty in operation of a packaging process is reduced, and the production yield is improved.
The invention will now be described in more detail with reference to the drawings and specific examples, which are not intended to limit the invention thereto.
Drawings
FIG. 1 is a flow chart of a semiconductor packaging method of the present invention;
FIG. 2A is a schematic diagram of a temporary carrier plate and a plurality of chips;
FIG. 2B is a top view of the temporary carrier plate of FIG. 2A;
FIG. 3 is a schematic illustration of forming a molding layer on a temporary carrier plate;
FIG. 4A is a schematic view of a support sheet combined with a temporary carrier plate;
FIG. 4B is a bottom view of the support sheet of FIG. 4A;
FIGS. 5 to 6 are schematic views of a finished plastic layer and a cured plastic layer;
FIGS. 7A-7B are schematic views of a carrier sheet removed and a temporary bonding film removed;
FIGS. 8A and 8B are schematic diagrams of wiring, ball placement and dicing of multiple chips;
fig. 9 is a schematic diagram of another semiconductor package structure according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below in conjunction with the detailed description of the present invention and the corresponding drawings. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, are intended to fall within the scope of the present invention.
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for explaining the present invention and are not to be construed as limiting the present invention.
Referring to fig. 1 to 8B, fig. 1 is a flowchart of a semiconductor packaging method according to the present invention, and fig. 2A is a schematic diagram of a temporary carrier and a plurality of chips; FIG. 2B is a top view of the temporary carrier plate of FIG. 2A; FIG. 3 is a schematic illustration of forming a molding layer on a temporary carrier plate; FIG. 4A is a schematic view of a support sheet combined with a temporary carrier plate; FIG. 4B is a bottom view of the support sheet of FIG. 4A; FIGS. 5 to 6 are schematic views of a finished plastic layer and a cured plastic layer; FIGS. 7A-7B are schematic views of a carrier sheet removed and a temporary bonding film removed; fig. 8A and 8B are schematic diagrams of wiring on a plurality of chips and dicing the chips after ball placement.
The semiconductor packaging method of the present invention comprises:
step A (S110), providing a temporary bearing plate, wherein the temporary bearing plate is provided with a plurality of chips, the temporary bearing plate is provided with a chip layout area and an edge area surrounding the chip layout area, and the chips are positioned on the chip layout area;
step B (S120), forming a plastic layer by utilizing a vacuum film pressing process, wherein the plastic layer covers the chip layout area and the edge area;
step C (S130), providing a supporting sheet, wherein the supporting sheet is provided with an annular auxiliary piece corresponding to the edge area of the temporary bearing plate, and the supporting sheet is combined with the temporary bearing plate, and the auxiliary piece is embedded into the plastic sealing layer and surrounds the chip layout area to assist in increasing the thickness of the plastic sealing layer in the edge area; and
and D (S140), removing the temporary bearing plate.
Specifically, as shown in fig. 2A and 2B, in step a, a temporary carrier 100 is provided, the temporary carrier 100 has a plurality of chips 210 thereon, the temporary carrier 100 has a chip layout area 101 and an edge area 102 surrounding the chip layout area 101, and the plurality of chips 210 are located on the chip layout area 101. It should be noted that, for convenience of description, the chips 210 are not shown in fig. 2B, and only two chips 210 are shown in fig. 2A, but the present invention is not limited thereto. As shown in FIGS. 2A and 2B, the edge region 102 has a first width w1, and typically, the first width w1 is greater than or equal to 3000um. In this embodiment, the edge region 102 is annular, and the first width w1 is a difference between radii of inner and outer concentric circles forming the edge region 102.
As shown in fig. 2A, in the present embodiment, the temporary carrier plate 100 includes a carrier sheet 110 and a temporary bonding film 120 detachable therefrom, the temporary bonding film 120 is laid on the carrier sheet 110, and the plurality of chips 210 are disposed on the temporary bonding film 120.
As shown in fig. 3, in step B, a plastic layer 220 is formed by using a vacuum film pressing process, and the plastic layer 220 covers the chip layout area 101 and the edge area 102, so that the plastic layer 220 can cover the plurality of chips 210, where "cover" means that the plastic layer 220 covers at least a part of the area of the plurality of chips 210. As shown by arrow a in fig. 3, the thickness of the molding layer 220 at the local edge region 102 is smaller than the thickness at the chip layout region 101, or the molding layer 220 is considered to have a defect at the local edge region 102 on the side away from the temporary carrier 100.
In practice, the material used for the plastic layer 220 is an organic polymer resin with inorganic filler, or an organic polymer resin with glass fiber cloth and filler, or a polymer composite material with filler such as epoxy resin, polyimide (PI), dry film, etc.
As shown in fig. 4A and 4B, in step C, a supporting sheet 300 is provided, and an auxiliary member 310 is disposed on the supporting sheet 300 corresponding to the edge region 102 of the temporary carrier 100, and the supporting sheet 300 is combined with the temporary carrier 100, and the auxiliary member 310 is embedded into the molding layer 220 and surrounds the chip layout region 101 to assist in increasing the thickness of the molding layer 220 in the edge region 102. In the present embodiment, the shape and size of the supporting sheet 300 are the same as those of the temporary loading plate 100, so that the supporting sheet 300 and the temporary loading plate 100 can completely correspond to each other when combined, and in practical operation, the invention is not limited thereto.
In this embodiment, the auxiliary member 310 is a glue layer, i.e. a circle of Dam glue (Dam glue) is formed on the supporting sheet 300 in advance. In the present embodiment, as shown in fig. 4B, the auxiliary member 310 is a continuous annular adhesive layer. In another embodiment, the auxiliary element 310 may also be an annular adhesive layer formed by a plurality of discrete dispensing. Further, the distance between the two dispensing centers is smaller than the side length of the shortest side of the chip 210, so as to ensure that the four corners (or at least two corners) of the chip 210 adjacent to the edge area 202 can be supported when the supporting sheet 300 is engaged with the temporary carrier 100. In practice, the auxiliary element 310 may be other organic film layers.
In actual operation, as shown by arrow B in fig. 4A, in step C, when the auxiliary member 310 is embedded in the molding layer 220, the molding layer 220 is not yet cured, and part of the molding material in the molding layer 220 overflows from the edge region 102 due to the embedding of the auxiliary member 310. As shown in fig. 5, step C further includes trimming the molding layer 220. Specifically, the plastic package material overflowed from the edge area 102 is trimmed and cut away (the dotted line is a cutting line in fig. 5), so that the edge of the plastic package layer 220 may be, for example, flush with the edges of the temporary carrier plate 100 and the supporting sheet 300.
Next, as shown in fig. 6, before removing the temporary carrier 100 in step D, the semiconductor packaging method further includes baking the cured plastic layer 220; the difference in the total thickness of the cured plastic layer 220 is less than or equal to 20um.
In this embodiment, the molding layer 220 has a first thickness h1, and the auxiliary member 310 has a second thickness h2, wherein h1 is 0.1 < h2 < h1 is 0.8. In practice, the first height h1 is, for example, 260um to 280um, and the second height h2 may be between 40um to 200 um. Further, as described above, the edge area 102 of the temporary loading plate 100 has the first width w1, and the auxiliary element 310 has the second width w2, wherein 0.5×w1+.w2+.w1, i.e. the width of the auxiliary element 310 is at least half or more of the width of the edge area 102. In this embodiment, the auxiliary element 310 is annular, so that the second width w2 is the difference between the radii of the inner and outer circles forming the auxiliary element 310. In practice, the first width w1 is, for example, 3000um or more, and the second width w2 is, for example, 1700 to 2970 um. By such a design, the auxiliary member 310 can be completely embedded in the plastic sealing layer 220 and provide a proper supporting effect and a proper flow-limiting effect for the plastic sealing layer 220 on the edge region 102 when the supporting sheet 300 is combined with the temporary carrier plate 100, so as to assist in increasing the thickness of the plastic sealing layer 220 in the edge region 102 and the structural integrity of the plastic sealing layer 220 in the edge region 102.
Next, as shown in fig. 7A and 7B, in step D, the carrier sheet 110 is removed first, and then the temporary bonding film 120 is torn off.
In actual operation, two wafers are respectively formed in the two experimental conditions of arranging the auxiliary member 310 and not arranging the auxiliary member 310 at the corresponding edge region 102 of the supporting sheet 300, and after the temporary carrier 100 is removed (i.e. De-bonding), the two wafers are respectively cut along the warp and weft, and the thickness of the plastic layer 220 is measured uniformly by spot removal along the cutting line. From measurement data, the thickness of the plastic sealing layer 220 on the wafer without the auxiliary member 310 ranges from 250um to 290um, and the Total Thickness Value (TTV) difference is 40um. The thickness range of the plastic sealing layer on the wafer provided with the auxiliary member 310 is 260 um-280 um, and the Total Thickness Value (TTV) difference is 20um. Thus, it is apparent that by providing the auxiliary member 310 on the supporting sheet 300, the overall thickness of the molding layer 220 on the wafer becomes more uniform, the Total Thickness Value (TTV) difference is reduced from 40um to 20um, and the thickness of the edge region of the wafer is significantly increased; in addition, from the appearance, the falling-off condition of the plastic package material on the edge area of the wafer is also greatly improved.
The semiconductor packaging method of the present embodiment can be applied to a wafer level fan-out package of vacuum film, as shown in fig. 8A, after removing the temporary carrier 100, step D further includes wiring (Redistribution layer) 211 and ball drop (ball drop) 212 on the plurality of chips 210. In another embodiment, the semiconductor packaging method can also be applied to multidimensional fan-out packaging integration with wafer level plastic packaging technology, specifically, a high-density rewiring layer (Ultra high density RDLs) can be disposed on the plurality of chips 210, and the high-density rewiring layer is electrically connected with the plurality of chips 210 through a plurality of micro-contacts (micro bumps). Each chip 210 has, for example, a plurality of electrodes, and the high-density redistribution layer is electrically connected to the plurality of electrodes through a plurality of microcontacts. The high-density re-wiring layer may include a dielectric layer and a metal wiring layer distributed within the dielectric layer. Openings may also be provided in the dielectric layer to expose at least a portion of the metal wiring layer, which may be electrically connected to other external circuitry, such as a circuit board (PCB), etc., by, for example, solder balls. The material of the dielectric layer may be benzocyclobutene (BCB) or Polyimide (PI) or other polymer dielectric materials, or polymer dielectric materials with filler. The material of the metal wiring layer may be a single-layer or multi-layer structure of titanium, tiW, copper, an alloy of gold and a metal, or an alloy of titanium, tiW, copper, nickel and gold. In practice, the number of dielectric layers and metal wiring layers included in the high-density re-wiring layer may be set according to the wiring layout requirements of each chip 210. When the high-density re-wiring layer is provided with a plurality of dielectric layers and a plurality of metal wiring layers, the dielectric layers and the metal wiring layers are arranged at intervals one by one, and the metal wiring layers are mutually conducted to form a channel capable of transmitting power supply signals.
As shown in fig. 8B, the semiconductor packaging method further includes dicing the plurality of chips 210 into a plurality of individual packages, and leaving no auxiliary member 310 on each package. In this embodiment, during the dicing of the chips, the auxiliary element 310 corresponds to an edge region (i.e. a wafer ineffective region) that is not left on each chip 210, so that other existing process flows are not affected, and the packaging structure is not affected.
Please refer to fig. 9, which is a schematic diagram of another semiconductor package structure of the present invention. Unlike the single package including one chip 210, in the present embodiment, one semiconductor package includes at least two chips 210', and the at least two chips 210' may be the same or different. That is, the semiconductor package structure of the present embodiment is a multi-chip package structure, and specifically, may be a multi-chip fan-out package structure. The at least two chips 210 'have electrodes 211', the support sheet 300 'may be prefabricated with a high-density redistribution layer 320', the high-density redistribution layer 320 'includes a plurality of metal wiring layers 321' and a plurality of dielectric layers 322', the plurality of metal wiring layers 321' and the plurality of dielectric layers 322 'are arranged at intervals one by one, and the plurality of metal wiring layers 321' are mutually conducted to form a channel capable of transmitting power signals. In practice, the number of metal wiring layers 321' and dielectric layers 322' included in the high-density re-wiring layer 320' may be set according to actual needs.
In step C, the supporting plate 300' is combined with the temporary carrier, and the electrode 211' on each chip 210' is electrically connected to the redistribution layer 320' on the supporting plate 300', and in practice, the electrode 211' and the redistribution layer 320' may be electrically connected through a plurality of microcontacts (Micro-pads) 400. The microcontacts 400 may be solder having a certain height and gaps between microcontacts 400 may be filled with the molding layer 220'. Further, an opening may be disposed on a side of the dielectric layer 322' away from each chip 210' to expose at least a portion of the metal wiring layer 321', and the exposed metal wiring layer 321' may be electrically connected to other external circuits through, for example, solder balls 330 '. Similar to the embodiment shown in fig. 4A and 4B, at least a partial edge of the supporting sheet 300' is provided with an auxiliary member 310', and before the supporting sheet 300' is combined with the temporary carrier plate, a plastic layer 220' is formed to cover the at least two chips 210'; when the support sheet 300 'is combined with the temporary carrier plate, the auxiliary member 310' is embedded in the plastic sealing layer 220 'and at least partially surrounds the at least two chips 210' to provide a supporting effect and a current limiting effect.
In this embodiment, after the step D, the at least two chips 210' are cut into the same package. In this way, the semiconductor package structure is a multi-chip fan-out package structure, and may have at least two chips 210', where the at least two chips 210' are connected through the redistribution layer 320 'on the support sheet 300'.
As shown in fig. 9, the semiconductor package structure further has a underfill (underfill) 500, where the underfill 500 is disposed between each chip 210 'and the supporting plate 300', and the height of the underfill 500 may be equal to the height of the electrode 211 'on each chip 210'. Thereby further assisting in enhancing the strength of the connection between each chip 210' and the support sheet 300' (e.g., the redistribution layer 320 '). In this embodiment, the auxiliary member 310' is at least partially remained on the semiconductor package during the dicing process; in practice, the auxiliary member 310' may not be retained on the semiconductor package structure, depending on the actual requirement.
In addition, the invention also relates to a supporting sheet 300 for packaging the semiconductor, the supporting sheet 300 is used for being combined with a temporary bearing plate 100, the temporary bearing plate 100 is provided with a plurality of chips 210, the temporary bearing plate 100 is provided with a chip layout area 101 and an edge area 102 surrounding the chip layout area 101, and the chips 210 are positioned on the chip layout area 101; the temporary carrier 100 is further provided with a plastic layer 220 formed by a vacuum film pressing process, and the plastic layer 220 covers the chip layout area 101 and the edge area 102; the supporting piece 300 is provided with an annular auxiliary piece 310 corresponding to the edge area 102 of the temporary loading board 100, and when the supporting piece 300 is combined with the temporary loading board 100, the auxiliary piece 310 is embedded into the plastic package layer 220 and surrounds the chip layout area 101 to assist in increasing the thickness of the plastic package layer 220 in the edge area 102.
In practice, the auxiliary element 310 may be a dispensing layer or a film layer, such as an annular organic film layer. Further, the height of the auxiliary element 310 is between 40um and 200um, and the width of the auxiliary element 320 is between 1700um and 2970 um. By such a design, the auxiliary member 310 can be completely embedded in the plastic sealing layer 220 and provide a proper supporting effect and a proper flow-limiting effect for the plastic sealing layer 220 on the edge region 102 when the supporting sheet 300 is combined with the temporary carrier plate 100, so as to assist in increasing the thickness of the plastic sealing layer 220 in the edge region 102 and the structural integrity of the plastic sealing layer 220 in the edge region 102.
According to the semiconductor packaging method, the packaging structure and the supporting sheet for semiconductor packaging, the annular auxiliary piece is arranged on the supporting sheet, when the supporting sheet is combined with the temporary bearing plate, the auxiliary piece is embedded into the plastic sealing layer to achieve the flow limiting and supporting effects of the mold on the plastic sealing material in the similar plastic sealing process, so that the vacuum film pressing process can optimize the forming condition of the edge plastic sealing material on the premise of keeping the original advantages. Therefore, the problem of falling of plastic packaging materials is avoided, the difficulty in operation of a packaging process is reduced, and the production yield is improved.
Of course, the present invention is capable of other various embodiments and its several details are capable of modification and variation in light of the present invention by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (15)

1. A semiconductor packaging method, characterized in that the semiconductor packaging method comprises,
step A, providing a temporary bearing plate, wherein the temporary bearing plate is provided with a plurality of chips, the temporary bearing plate is provided with a chip layout area and an edge area surrounding the chip layout area, and the chips are positioned on the chip layout area;
step B, forming a plastic sealing layer by utilizing a vacuum film pressing process, wherein the plastic sealing layer covers the chip layout area and the edge area;
step C, providing a supporting sheet, wherein the supporting sheet is provided with an annular auxiliary piece corresponding to the edge area of the temporary bearing plate, the supporting sheet is combined with the temporary bearing plate, and the auxiliary piece is embedded into the plastic sealing layer and surrounds the chip layout area to assist in increasing the thickness of the plastic sealing layer in the edge area; and
and D, removing the temporary bearing plate.
2. The method of claim 1, further comprising, after step D, dicing the plurality of chips into a plurality of individual packages, wherein the auxiliary member is not retained on each package.
3. The method of claim 1, wherein in step C, a portion of the molding compound in the molding layer overflows from the edge region when the auxiliary member is embedded in the molding layer, and step C further comprises trimming the molding layer.
4. The method of claim 1, further comprising, prior to step D, bake curing the molding layer; and the difference of the total thickness of the cured plastic sealing layer is less than or equal to 20um.
5. The method of claim 1, wherein the auxiliary component is a dispensing layer or a film layer.
6. The semiconductor package method of claim 1, wherein the molding layer has a first thickness h1 and the auxiliary member has a second thickness h2, wherein h1 is 0.1 < h2 < h1 is 0.8.
7. The semiconductor packaging method according to claim 1 or 6, wherein the edge region has a first width w1 and the auxiliary member has a second width w2, wherein w1 is 0.5 < w2 < w1.
8. The method of claim 1, wherein the height of the auxiliary member is between 40um and 200um, and the width of the auxiliary member is between 1700um and 2970 um.
9. The method of claim 1, wherein step D further comprises, after removing the temporary carrier, routing and ball mounting on the plurality of chips; or, a high-density rewiring layer is arranged on the chips, and the high-density rewiring layer is electrically connected with the chips through a plurality of microcontacts.
10. The semiconductor packaging method according to claim 1, wherein in step a, the temporary carrier plate includes a carrier sheet and a temporary bonding film separable therefrom, the plurality of chips are disposed on the temporary bonding film, and the temporary bonding film is laid on the carrier sheet; step D includes removing the carrier sheet and tearing off the temporary bonding film.
11. The method of claim 1, wherein a redistribution layer is preformed on the supporting sheet, at least two of the plurality of chips have electrodes thereon, and in step C, the redistribution layer is electrically connected to the electrodes when the supporting sheet is combined with the temporary carrier; and D, cutting the at least two chips into the same packaging body.
12. The supporting sheet is used for being combined with a temporary bearing plate, the temporary bearing plate is provided with a plurality of chips, the temporary bearing plate is provided with a chip layout area and an edge area surrounding the chip layout area, and the chips are positioned on the chip layout area; the temporary bearing plate is also provided with a plastic layer formed by a vacuum film pressing process, and the plastic layer covers the chip layout area and the edge area; the support piece corresponds the marginal area of interim loading board is provided with annular auxiliary member, the support piece with interim loading board combines, the auxiliary member embedding in the plastic envelope layer and encircle the chip overall arrangement area is in order to assist to promote the plastic envelope layer in the thickness of marginal area.
13. The support sheet for semiconductor package according to claim 12, wherein the auxiliary member is a dispensing layer or a film-attaching layer.
14. The support sheet for semiconductor package according to claim 12, wherein the height of the auxiliary member is between 40um and 200um, and the width of the auxiliary member is between 1700um and 2970 um.
15. A semiconductor package structure is characterized by comprising,
the support sheet according to any one of claims 12-14, wherein a rewiring layer is pre-provided on the support sheet, and wherein the support sheet has an auxiliary member at least at a partial edge;
at least two chips having electrodes thereon; the electrode is electrically connected with the rewiring layer; and
and the auxiliary piece is embedded in the plastic sealing layer and at least partially surrounds the at least two chips.
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