CN115494932A - Method, system, equipment and medium for reducing load rate of main chip of vehicle controller - Google Patents

Method, system, equipment and medium for reducing load rate of main chip of vehicle controller Download PDF

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CN115494932A
CN115494932A CN202211176666.3A CN202211176666A CN115494932A CN 115494932 A CN115494932 A CN 115494932A CN 202211176666 A CN202211176666 A CN 202211176666A CN 115494932 A CN115494932 A CN 115494932A
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signal
storage block
signals
byte length
area network
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程勇
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Chongqing Changan New Energy Automobile Technology Co Ltd
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Chongqing Changan New Energy Automobile Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3275—Power saving in memory, e.g. RAM, cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L2012/40208—Bus networks characterized by the use of a particular bus standard
    • H04L2012/40215—Controller Area Network CAN
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L2012/40267—Bus for use in transportation systems
    • H04L2012/40273—Bus for use in transportation systems the transportation system being a vehicle

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  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
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  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
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Abstract

The application provides a method, a system, equipment and a medium for reducing load rate of a main chip of a vehicle controller, which comprises the following steps: configuring a storage unit for each path of controller area network signals, wherein the storage unit comprises a first storage block for storing received signals, a second storage block for storing sent signals and a third storage block for storing signals except for sent and received signals, and the first storage block, the second storage block and the third storage block respectively comprise a plurality of caches; multiplexing the caches in the first storage block, the second storage block and the third storage block according to a signal period, a signal identification code or a signal source in each path of the controller area network signal to perform signal processing. The processing resource utilization rate can be effectively improved through cache multiplexing.

Description

Method, system, equipment and medium for reducing load rate of main chip of vehicle controller
Technical Field
The application relates to the field of intelligent automobiles, in particular to a method, a system, equipment and a medium for reducing the load rate of a main chip of a vehicle controller.
Background
At present, with the rapid development of the new energy industry, the market share of new energy vehicles is continuously expanded, and the new energy vehicles play an important role as a whole vehicle controller of a brain of the new energy vehicles. As the degree of informatization and intellectualization of new energy automobiles is continuously deepened, the requirement on the whole automobile controller is also continuously improved, and because the automobile research and development period is longer, the type of a main chip processor is determined, so that how to effectively improve the utilization rate of limited processor resources becomes a current difficult problem.
Disclosure of Invention
In view of the problems in the prior art, the application provides a method, a system, equipment and a medium for reducing the load rate of a main chip of a vehicle controller, and mainly solves the problem that the utilization rate of processor resources is low in the existing method.
In order to achieve the above and other objects, the present application adopts the following technical solutions.
The application provides a method for reducing load rate of a main chip of a vehicle controller, which comprises the following steps:
configuring a storage unit for each path of controller area network signals, wherein the storage unit comprises a first storage block for storing received signals, a second storage block for storing sent signals and a third storage block for storing signals except for sent and received signals, and the first storage block, the second storage block and the third storage block respectively comprise a plurality of caches;
and multiplexing the caches in the first storage block, the second storage block and the third storage block according to the signal period, the signal identification code or the signal source in each path of the controller area network signal to perform signal processing.
In an embodiment of the present application, configuring a storage unit for each of the local area network signals of the controller includes:
acquiring the byte length of each signal in each path of controller local area network signals;
determining the number of the caches in the first storage block according to the byte length of the received signal in each path of controller area network signal;
determining the number of the caches in the second storage block according to the byte length of the transmission signal in each path of controller local area network signal; and (c) a second step of,
and determining the number of the buffers in the third storage block according to the byte length of signals except the received signals and the sent signals in each path of controller area network signals.
In an embodiment of the present application, determining the number of buffers in the first storage block according to the byte length of the received signal in each path of controller area network signal includes:
comparing the byte length of each received signal with a preset first target byte length, and if each received signal contains a signal with the preset first target byte length, taking the cache number corresponding to the first target byte length as the cache number in the first storage block according to the mapping relation between the preset signal byte length and the cache number;
and if the received signals do not contain signals with preset first target byte length, determining the number of the caches in the first storage block according to the longest byte length in the received signals and the mapping relation between the signal byte length and the cache number.
In an embodiment of the present application, determining the number of caches in the second storage block according to the byte length of the transmission signal in each path of controller area network signal includes:
comparing the byte length of each transmission signal with a preset second target byte length, and if each transmission signal contains a signal with the preset second target byte length, taking the cache number corresponding to the second target byte length as the number of caches in the first storage block according to the mapping relation between the preset signal byte length and the cache number;
and if the sending signals do not contain signals with preset second target byte length, determining the number of the caches in the second storage block according to the longest byte length in the sending signals and the mapping relation between the signal byte length and the cache number.
In an embodiment of the present application, multiplexing the buffers in the first storage block, the second storage block, and the third storage block according to a signal period in each path of the controller area network signal includes:
acquiring a signal with a signal period smaller than a preset period threshold value in the controller local area network signal as a small period signal;
distributing the small-period signals to different caches in corresponding storage blocks according to the signal types stored in the first storage block, the second storage block and the third storage block;
and when the two signal periods in the second storage block are the same, configuring a transmission offset for the corresponding signal, so as to complete the transmission of the corresponding signal according to the transmission offset.
In an embodiment of the present application, multiplexing the cache in the first storage block according to a signal identification code in each path of the controller area network signal includes:
acquiring a received signal with the deviation value of the signal identification code within a preset range, and recording the received signal as an adjacent signal;
multiplexing the adjacent signals in the same buffer of the first memory block.
In an embodiment of the present application, multiplexing the buffers in the first storage block, the second storage block, and the third storage block according to a signal source in each path of the controller area network signal includes:
acquiring a signal source of each signal in the controller area network signals;
and multiplexing the signals of which the signal sources belong to the same controller or the same network segment in the same cache of the first storage block, the second storage block or the third storage block.
The present application further provides a system for reducing a load factor of a main chip of a vehicle controller, including:
a storage configuration module, configured to configure a storage unit for each way of controller area network signal, where the storage unit includes a first storage block for storing a received signal, a second storage block for storing a transmitted signal, and a third storage block for storing a signal other than the transmitted and received signal, and the first storage block, the second storage block, and the third storage block respectively include multiple caches;
and the signal multiplexing module is used for multiplexing the caches in the first storage block, the second storage block and the third storage block according to the signal period, the signal identification code or the signal source in each path of the controller area network signal so as to process the signal.
The present application further provides a computer device, comprising: the processor executes the computer program to realize the steps of the method for reducing the load rate of the main chip of the vehicle control unit.
The application also provides a computer-readable storage medium, on which a computer program is stored, and the computer program, when executed by a processor, implements the steps of the method for reducing the load factor of the main chip of the vehicle controller.
As described above, the method, system, device and medium for reducing the load factor of the main chip of the vehicle controller according to the present application have the following beneficial effects.
According to the method and the device, the number of the accommodated controller local area network signals is increased in a cache administration mode, the storage block is predefined based on the signal type, and meanwhile, the problems of unstable signal period and frame loss caused by data collision can be effectively reduced by multiplexing based on the period, the identification code and the signal source.
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Fig. 1 is a schematic flowchart of a method for reducing a load factor of a main chip of a vehicle controller according to an embodiment of the present application.
Fig. 2 is a block diagram of a system for reducing a load factor of a main chip of a vehicle controller according to an embodiment of the present application.
Fig. 3 is a schematic structural diagram of an apparatus according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application is provided by way of specific examples, and other advantages and effects of the present application will be readily apparent to those skilled in the art from the disclosure herein. The present application is capable of other and different embodiments and its several details are capable of modifications and/or changes in various respects, all without departing from the spirit of the present application. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present application, and the drawings only show the components related to the present application and are not drawn according to the number, shape and size of the components in actual implementation, and the type, number and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Referring to fig. 1, the present application provides a method for reducing a load factor of a main chip of a vehicle controller, which includes the following steps.
Step S100, configuring a storage unit for each local area network signal of the controller, where the storage unit includes a first storage block for storing a received signal, a second storage block for storing a transmitted signal, and a third storage block for storing a signal other than the transmitted and received signal, and the first storage block, the second storage block, and the third storage block respectively include a plurality of buffers.
In an embodiment, taking 32 as an example of a MPC5748G (hereinafter referred to as the present chip), the present chip has 3 RAM BLOCKs (hereinafter referred to as BLOCKs) corresponding to each path of a controller area network (hereinafter referred to as CAN) signal, and each BLOCK corresponds to a CAN signal that CAN be processed as follows: if the CAN signal is 8 bytes, 32 such BUFFERs CAN be accommodated; if the CAN signal is 16 bytes, 21 such BUFFERs CAN be accommodated; if the CAN signal is 32 bytes, 12 such BUFFERs CAN be accommodated; if the CAN signal is 64 bytes, 7 such BUFFERs CAN be accommodated. Therefore, normally, each CAN process 21 CAN signals with 64 bytes at most. When the block is used for storing high-byte CAN signals, the capacity of the block is fixed to correspond to the number of BUFFER signals, for example, when the block stores 64-byte CAN signals, the block CAN only store 6 CAN signals (the length is less than or equal to 64 bytes); if 32 bytes of CAN signals are stored, it CAN store only 12 CAN signals (the length is less than or equal to 32 bytes).
In practical engineering application, the length of the CAN signal of each path is often not uniform, there are some 8-byte signals and many 64-byte signals, and if we select each block to store 64 bytes, the situation that the corresponding BUFFER number is not enough occurs. However, BUFFER multiplexing has a problem, which is equivalent to that a plurality of signals occupy one hardware BUFFER for data transmission, and a signal period instability or frame loss situation caused by data collision occurs.
In one embodiment, three BLOCKs are defined as BLOCK _0 (i.e., the first memory BLOCK), BLOCK _1 (i.e., the third memory BLOCK), and BLOCK _2 (i.e., the second memory BLOCK), and the received and transmitted signals are first separated, the received signal is placed in BLOCK _0, the transmitted signal is placed in BLOCK _2, and the remaining transmitted and received signals are placed in BLOCK _1.
In one embodiment, the configuring the storage unit for each way of the signals of the controller area network comprises:
acquiring the byte length of each signal in each path of controller local area network signals;
determining the number of the caches in the first storage block according to the byte length of the received signal in each path of controller area network signal;
determining the number of the caches in the second storage block according to the byte length of the sending signal in each path of controller local area network signals; and the number of the first and second groups,
and determining the number of the caches in the third storage block according to the byte length of signals except the received signals and the sent signals in each path of controller area network signals.
In one embodiment, determining the amount of buffering in the first memory block according to the byte length of the received signal in each way of the controller area network signal includes:
comparing the byte length of each received signal with a preset first target byte length, and if each received signal contains a signal with the preset first target byte length, taking the cache number corresponding to the first target byte length as the number of caches in the first storage block according to the mapping relation between the preset signal byte length and the cache number;
if each of the received signals does not include a signal with a preset first target byte length, determining the number of the caches in the first storage block according to the longest byte length in each of the received signals and the mapping relationship between the signal byte length and the number of the caches.
Specifically, the first target byte length may be configured to be 64 bytes, and if the received signal has 64 bytes, the corresponding BLOCK is defined as a BUFFER of 64 bytes. If the first target byte length is not included, the type of the first storage block is determined by the longest byte.
In one embodiment, determining the amount of buffering in the second storage block according to the byte length of the transmission signal in each way of the controller area network signal includes:
comparing the byte length of each transmission signal with a preset second target byte length, and if each transmission signal contains a signal with the preset second target byte length, taking the cache number corresponding to the second target byte length as the number of caches in the first storage block according to the mapping relation between the preset signal byte length and the cache number;
and if the sending signals do not contain signals with preset second target byte length, determining the number of the caches in the second storage block according to the longest byte length in the sending signals and the mapping relation between the signal byte length and the cache number.
Specifically, the second target byte length may be configured to be 64 bytes, and if the transmission signal has 64 bytes, the corresponding BLOCK is defined as a BUFFER of 64 bytes. If the second target byte length is not included, the type of the first storage block is determined by the longest byte.
In one embodiment, the remaining signal BLOCK _1 may also be defined according to the above manner.
Step S110, multiplexing the buffers in the first storage block, the second storage block, and the third storage block according to a signal period, a signal identification code, or a signal source in each path of the controller area network signal to perform signal processing.
In an embodiment, multiplexing the buffers in the first memory block, the second memory block, and the third memory block according to a signal period in each path of the controller area network signal includes:
acquiring a signal with a signal period smaller than a preset period threshold value in the controller local area network signal as a small period signal;
distributing the small-period signals to different caches in corresponding storage blocks according to the signal types stored in the first storage block, the second storage block and the third storage block;
and when the two signal periods in the second storage block are the same, configuring a sending offset for the corresponding signal so as to complete the sending of the corresponding signal according to the sending offset.
Specifically, since the shorter-cycle CAN signal has a larger influence on the load of the processor, the shorter-cycle signal cannot be multiplexed in one BUFFER at the time of multiplexing. The multiplexing adopts that each BUFFER is given a small period signal, so that the small period signals are not multiplexed in one BUFFER. For the signal transmitted by BLOCK _2, a combination mode of small period and large period is adopted, and the condition of unstable period is reduced by using the difference of the transmission intervals. If the two ID periods multiplexed in BLOCK _2 are the same, an offset needs to be configured between the two IDs, so that a transmission interval exists between the two signals, otherwise, a frame loss situation occurs.
In one embodiment, multiplexing the buffers in the first storage block according to the signal identification code in each path of the controller area network signal includes:
acquiring a received signal with the deviation value of the signal identification code within a preset range, and recording the received signal as an adjacent signal;
multiplexing the adjacent signals in the same buffer of the first memory block.
Specifically, for the signal received in BLOCK _0, signals with similar IDs (signal identification codes) are multiplexed in one BUFFER. Signals with similar IDs may be determined from the code value deviations between the signal representative codes of the signals.
In an embodiment, multiplexing the buffers in the first memory block, the second memory block, and the third memory block according to a signal source in each of the controller area network signals includes:
acquiring signal sources of all signals in the controller area network signals;
multiplexing the signals of which the signal sources belong to the same controller or the same network segment into the same cache of the first storage block, the second storage block or the third storage block.
Specifically, signals from the same controller or the same network segment are multiplexed in one BUFFER.
Referring to fig. 2, the present embodiment provides a system for reducing a load factor of a main chip of a vehicle controller, which is used to execute the method for reducing the load factor of the main chip of the vehicle controller in the foregoing embodiment of the method. Since the technical principle of the system embodiment is similar to that of the method embodiment, repeated description of the same technical details is omitted.
In one embodiment, the system for reducing the load factor of the main chip of the whole vehicle controller comprises: a storage configuration module 10, configured to configure a storage unit for each way of controller area network signal, where the storage unit includes a first storage block for storing a received signal, a second storage block for storing a transmitted signal, and a third storage block for storing a signal other than the transmitted and received signal, and the first storage block, the second storage block, and the third storage block respectively include multiple caches; and a signal multiplexing module 11, configured to multiplex the buffers in the first storage block, the second storage block, and the third storage block according to a signal period, a signal identifier, or a signal source in each path of the controller area network signal to perform signal processing.
The embodiment of the application further provides a device for reducing the load factor of the main chip of the vehicle controller, and the device may include: one or more processors; and one or more machine readable media having instructions stored thereon that, when executed by the one or more processors, cause the apparatus to perform the method of fig. 1. In practical applications, the device may be used as a terminal device, and may also be used as a server, where examples of the terminal device may include: smart phones, tablet computers, electronic book readers, MP3 (moving Picture Experts Group Audio Layer III) players, MP4 (moving Picture Experts Group Audio Layer IV) players, laptop portable computers, car-mounted computers, desktop computers, set-top boxes, smart televisions, wearable devices, and the like, and the embodiments of the present application are not limited to specific devices.
The present application further provides a machine-readable medium, where one or more modules (programs) are stored in the medium, and when the one or more modules are applied to a device, the device may execute instructions (instructions) included in the method for reducing a load rate of a main chip of a vehicle controller in fig. 1 according to the present application. The machine-readable medium can be any available medium that a computer can store or a data storage device including one or more available media integrated servers, data centers, and the like. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid State Disk (SSD)), among others.
Referring to fig. 3, the present embodiment provides a device 80, and the device 80 may be a desktop device, a laptop computer, a smart phone, or the like. In detail, the device 80 comprises at least, connected by a bus 81: a memory 82 and a processor 83, wherein the memory 82 is used for storing a computer program, and the processor 83 is used for executing the computer program stored in the memory 82 to execute all or part of the steps of the method embodiments.
The above-mentioned system bus may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The system bus may be divided into an address bus, a data bus, a control bus, and the like. For ease of illustration, only one thick line is shown, but this is not intended to represent only one bus or type of bus. The communication interface is used for realizing communication between the database access device and other equipment (such as a client, a read-write library and a read-only library). The Memory may include a Random Access Memory (RAM), and may further include a non-volatile Memory (non-volatile Memory), such as at least one disk Memory.
The Processor may be a general-purpose Processor, and includes a Central Processing Unit (CPU), a Network Processor (NP), and the like; the Integrated Circuit may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, a discrete Gate or transistor logic device, or a discrete hardware component.
The above embodiments are merely illustrative of the principles and utilities of the present application and are not intended to limit the application. Any person skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present application. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical concepts disclosed in the present application shall be covered by the claims of the present application.

Claims (10)

1. A method for reducing load rate of a main chip of a vehicle controller is characterized by comprising the following steps:
configuring a storage unit for each path of controller area network signals, wherein the storage unit comprises a first storage block for storing received signals, a second storage block for storing sent signals and a third storage block for storing signals except for sent and received signals, and the first storage block, the second storage block and the third storage block respectively comprise a plurality of caches;
multiplexing the caches in the first storage block, the second storage block and the third storage block according to a signal period, a signal identification code or a signal source in each path of the controller area network signal to perform signal processing.
2. The method for reducing the load factor of the main chip of the vehicle controller according to claim 1, wherein configuring a storage unit for each path of the controller area network signal comprises:
acquiring the byte length of each signal in each path of controller local area network signals;
determining the number of the caches in the first storage block according to the byte length of the received signal in each path of controller area network signal;
determining the number of the caches in the second storage block according to the byte length of the transmission signal in each path of controller local area network signal; and the number of the first and second groups,
and determining the number of the buffers in the third storage block according to the byte length of signals except the received signals and the sent signals in each path of controller area network signals.
3. The method for reducing the load rate of the primary chip of the vehicle controller according to claim 2, wherein determining the number of the buffers in the first storage block according to the byte length of the received signal in each path of the controller area network signal comprises:
comparing the byte length of each received signal with a preset first target byte length, and if each received signal contains a signal with the preset first target byte length, taking the cache number corresponding to the first target byte length as the number of caches in the first storage block according to the mapping relation between the preset signal byte length and the cache number;
and if the received signals do not contain signals with preset first target byte length, determining the number of the caches in the first storage block according to the longest byte length in the received signals and the mapping relation between the signal byte length and the cache number.
4. The method for reducing the load rate of the primary chip of the vehicle controller according to claim 2, wherein determining the number of the buffers in the second storage block according to the byte length of the transmission signal in each path of the controller area network signal comprises:
comparing the byte length of each transmission signal with a preset second target byte length, and if each transmission signal contains a signal with the preset second target byte length, taking the cache number corresponding to the second target byte length as the number of caches in the first storage block according to the mapping relation between the preset signal byte length and the cache number;
and if the sending signals do not contain signals with preset second target byte length, determining the number of the caches in the second storage block according to the longest byte length in the sending signals and the mapping relation between the signal byte length and the cache number.
5. The method for reducing the load factor of the main chip of the vehicle controller according to claim 1, wherein multiplexing the buffers in the first storage block, the second storage block, and the third storage block according to a signal period in each path of the controller area network signal comprises:
acquiring a signal with a signal period smaller than a preset period threshold value in the controller local area network signal as a small period signal;
distributing the small-period signals to different caches in corresponding storage blocks according to the types of the signals stored in the first storage block, the second storage block and the third storage block;
and when the two signal periods in the second storage block are the same, configuring a transmission offset for the corresponding signal, so as to complete the transmission of the corresponding signal according to the transmission offset.
6. The method for reducing the load factor of the main chip of the vehicle controller according to claim 1, wherein multiplexing the buffer in the first storage block according to the signal identification code in each path of the signal in the controller area network signal comprises:
acquiring a received signal of which the deviation value of the signal identification code is within a preset range, and recording the received signal as an adjacent signal;
multiplexing the adjacent signals in the same buffer of the first memory block.
7. The method for reducing the load factor of the primary chip of the vehicle controller according to claim 1, wherein multiplexing the buffers in the first storage block, the second storage block, and the third storage block according to a signal source in each path of the controller area network signal comprises:
acquiring signal sources of all signals in the controller area network signals;
and multiplexing the signals of which the signal sources belong to the same controller or the same network segment in the same cache of the first storage block, the second storage block or the third storage block.
8. The utility model provides a system for vehicle control unit master chip reduces load rate which characterized in that includes:
a storage configuration module, configured to configure a storage unit for each way of controller area network signal, where the storage unit includes a first storage block for storing a received signal, a second storage block for storing a transmitted signal, and a third storage block for storing a signal other than the transmitted and received signal, and the first storage block, the second storage block, and the third storage block respectively include multiple caches;
and the signal multiplexing module is used for multiplexing the caches in the first storage block, the second storage block and the third storage block according to the signal period, the signal identification code or the signal source in each path of the controller local area network signal so as to process the signal.
9. A computer device, comprising: the memory, the processor and the computer program stored on the memory and executable on the processor, wherein the processor implements the steps of the method for reducing the load factor of the main chip of the whole vehicle controller according to any one of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium, on which a computer program is stored, wherein the computer program, when executed by a processor, implements the steps of the method for reducing the load factor of the vehicle controller main chip according to any one of claims 1 to 7.
CN202211176666.3A 2022-09-26 2022-09-26 Method, system, equipment and medium for reducing load rate of main chip of vehicle controller Pending CN115494932A (en)

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