CN115484755A - Manufacturing method of circuit board and circuit board - Google Patents
Manufacturing method of circuit board and circuit board Download PDFInfo
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- CN115484755A CN115484755A CN202110667909.2A CN202110667909A CN115484755A CN 115484755 A CN115484755 A CN 115484755A CN 202110667909 A CN202110667909 A CN 202110667909A CN 115484755 A CN115484755 A CN 115484755A
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4697—Manufacturing multilayer circuits having cavities, e.g. for mounting components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Diaphragms For Electromechanical Transducers (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
A manufacturing method of a circuit board comprises the following steps: providing an inner layer circuit substrate; forming a first intermediate circuit substrate and a second intermediate circuit substrate on the surface of the inner layer circuit substrate, wherein the first intermediate circuit substrate comprises a first intermediate circuit layer, and the first intermediate circuit layer comprises a bearing part and a connecting part; forming through holes penetrating through the first intermediate circuit substrate, the inner layer circuit substrate and the second intermediate circuit substrate, wherein the bearing part protrudes out of the through holes; providing a ceramic plate, placing the ceramic plate in the through hole and placing the ceramic plate on the bearing part; providing an electronic element, placing the electronic element in the through hole and placing the electronic element on the ceramic chip; forming a first outer-layer circuit substrate on the surface of the first middle circuit substrate, wherein the first outer-layer circuit substrate covers the ceramic plate; forming a second outer-layer circuit substrate, wherein the second outer-layer circuit substrate covers the electronic element; and forming a communicating block connected with the ceramic chip on the first outer layer circuit substrate, and forming a conductive hole connected with the electronic element on the second outer layer circuit substrate. The application also provides a circuit board.
Description
Technical Field
The present disclosure relates to the field of circuit board manufacturing, and more particularly, to a circuit board and a manufacturing method thereof.
Background
With the increasing demand of people for various electronic products such as computers, consumer electronics, communications and the like, electronic components in the electronic products are more and more centralized with the diversification of functions of the electronic products. The circuit board is used as a support body and a carrier for electrical connection of electronic components, so that heat dissipation becomes a huge problem in the circuit board industry.
The existing circuit board with embedded components has poor heat dissipation performance due to the limitation of the manufacturing process.
Disclosure of Invention
In view of the above, it is desirable to provide a method for manufacturing a circuit board with good heat dissipation performance and a circuit board, so as to solve the above problems.
A manufacturing method of a circuit board comprises the following steps: providing an inner layer circuit substrate; forming a first intermediate circuit substrate and a second intermediate circuit substrate on two opposite surfaces of the inner layer circuit substrate respectively, wherein the first intermediate circuit substrate comprises a first intermediate circuit layer, and the first intermediate circuit layer comprises a bearing part and a connecting part connected with the bearing part; forming through holes penetrating through the first intermediate circuit substrate, the inner layer circuit substrate and the second intermediate circuit substrate, wherein the bearing part extends in the through holes in a protruding mode; providing a ceramic plate which is arranged in the through hole and is arranged on the bearing part; providing an electronic element, placing the electronic element in the through hole and placing the electronic element on the ceramic chip; forming a first outer layer circuit substrate on the surface of the first middle circuit substrate, wherein the first outer layer circuit substrate covers the ceramic plate; forming a second outer layer circuit substrate on the surface of the second middle circuit substrate, wherein the second outer layer circuit substrate covers the electronic element; and forming a communicating block connected with the ceramic chip on the first outer layer circuit substrate, and forming a conductive hole connected with the electronic element on the second outer layer circuit substrate.
In some embodiments, the step of forming the first and second intermediate circuit substrates comprises: providing a first copper-clad plate and a second copper-clad plate, wherein the first copper-clad plate comprises a first inner dielectric layer and a first copper layer which are arranged in a stacked manner, and the second copper-clad plate comprises a second inner dielectric layer and a second copper layer which are arranged in a stacked manner; covering the first copper-clad plate and the second copper-clad plate on two opposite surfaces of the inner layer circuit substrate respectively; forming a blind hole penetrating through the first copper-clad plate; performing circuit manufacturing on the first copper layer to form a first intermediate circuit layer, and performing circuit manufacturing on the second copper layer to form a second intermediate circuit layer; the first intermediate circuit layer is filled in the blind hole to form the connecting part and form the bearing part protruding out of the connecting part.
In some embodiments, the first outer circuit substrate includes a first outer dielectric layer and a first outer circuit layer, and the communication block is disposed through the first outer dielectric layer and electrically connected to the first outer circuit layer; the second outer layer circuit substrate comprises a second outer layer dielectric layer and a second outer layer circuit layer, and the conductive hole penetrates through the second outer layer dielectric layer and is electrically connected with the second outer layer circuit layer.
In some embodiments, the first outer layer circuit substrate comprises a first outer layer dielectric layer and a third copper layer, and the second outer layer circuit substrate comprises a second outer layer dielectric layer and a fourth copper layer; the manufacturing method further comprises the following steps: and carrying out circuit manufacturing on the third copper layer to form a first outer layer circuit layer and the communicating block penetrating through the first outer layer dielectric layer, and carrying out circuit manufacturing on the fourth copper layer to form a second outer layer circuit layer and the conductive hole penetrating through the second outer layer dielectric layer.
In some embodiments, after the step of providing at least one ceramic sheet disposed in the through hole and on the carrying part, the method further comprises the steps of: and coating heat-conducting glue on the surface of the ceramic chip, which is far away from the first intermediate circuit layer.
A circuit board comprises a first outer layer circuit substrate, a first middle circuit substrate, an inner layer circuit substrate, a second middle circuit substrate and a second outer layer circuit substrate which are sequentially stacked, and further comprises at least one ceramic piece and at least one electronic element, wherein the ceramic piece and the electronic element are stacked and penetrate through the first middle circuit substrate, the inner layer circuit substrate and the second middle circuit substrate, the ceramic piece is located on one side close to the first middle circuit substrate and is electrically connected with the first outer layer circuit substrate through a communicating block, and the electronic element is located on one side close to the second middle circuit substrate and is electrically connected with the second outer layer circuit substrate through a conductive hole; wherein, the circuit board is still including enclosing to be located the ceramic chip with at least partial circumferential heat conduction silica gel of electronic component, first intermediate line base plate includes first intermediate line layer, first intermediate line layer include connecting portion and with the bearing part that connecting portion are connected, bearing part with connecting portion with the ceramic chip is connected, connecting portion with heat conduction silica gel connects.
In some embodiments, the circuit board further includes a thermal conductive paste, and the thermal conductive paste is located between the ceramic sheet and the electronic element.
In some embodiments, the first intermediate circuit substrate comprises a first intermediate dielectric layer and the first intermediate circuit layer arranged in a stack; the second intermediate circuit substrate includes a second intermediate dielectric layer and the second intermediate circuit layer stacked.
In some embodiments, the first outer circuit substrate includes a first outer dielectric layer and a first outer circuit layer, which are stacked, and the communication block is disposed through the first outer dielectric layer and electrically connected to the first outer circuit layer; the second outer circuit substrate comprises a second outer dielectric layer and a second outer circuit layer which are stacked, and the conductive hole penetrates through the second outer dielectric layer and is electrically connected with the second outer circuit layer.
In some embodiments, the connecting portion and the bearing portion are perpendicular to each other.
According to the manufacturing method of the circuit board, the ceramic chip and the electronic element which are connected with each other can be embedded simultaneously, the embedded density of the ceramic chip and the electronic element in the circuit board is large, and the ceramic chip is used for rapidly transferring heat generated by the electronic element, so that the density of the embedded element is improved, and the heat dissipation rate is effectively improved; by providing the first intermediate circuit substrate including the carrier portion and the connection portion connected to the carrier portion, a tendency of separation of the first intermediate circuit layer from the first intermediate dielectric layer can be prevented; the bearing part is directly connected with the connecting part and the surface of the ceramic plate, so that the contact area can be increased, and the heat dissipation efficiency is effectively improved.
Drawings
Fig. 1 is a schematic cross-sectional view of an inner layer circuit substrate according to an embodiment of the present disclosure.
Fig. 2 is a schematic cross-sectional view of the inner-layer circuit substrate shown in fig. 1 after a first copper-clad plate and a second copper-clad plate are respectively stacked on two opposite surfaces of the inner-layer circuit substrate.
Fig. 3 is a schematic cross-sectional view of the first copper-clad plate shown in fig. 2 after blind holes are formed in the surface of the first copper-clad plate.
Fig. 4 is a schematic cross-sectional view of the first and second copper layers shown in fig. 3 after forming a first intermediate circuit layer and a second intermediate circuit layer, respectively.
Fig. 5 is a schematic cross-sectional view of the first intermediate wiring substrate, the inner layer wiring substrate, and the second intermediate wiring substrate shown in fig. 4 after forming a via hole.
Fig. 6 is a schematic cross-sectional view of the through-hole shown in fig. 5 after a ceramic sheet is disposed therein.
Fig. 7 is a schematic cross-sectional view of the ceramic sheet shown in fig. 6 after a thermal conductive adhesive is coated on the surface of the ceramic sheet.
Fig. 8 is a schematic cross-sectional view of the thermal conductive paste of fig. 7 with electronic components disposed on the surface.
Fig. 9 is a schematic cross-sectional view of the first intermediate circuit board and the second intermediate circuit board shown in fig. 8, on the surfaces of which a first outer circuit board and a second outer circuit board are respectively stacked.
Fig. 10 is a schematic cross-sectional view of a circuit board obtained by forming a via connected to the ceramic sheet on the first outer-layer circuit board shown in fig. 9 and forming a conductive hole connected to the electronic component on the second outer-layer circuit board.
Description of the main elements
The following detailed description will further illustrate the present application in conjunction with the above-described figures.
Detailed Description
In order that the above objects, features and advantages of the present application can be more clearly understood, a detailed description of the present application will be given below with reference to the accompanying drawings and detailed description. In addition, the embodiments and features of the embodiments of the present application may be combined with each other without conflict. In the following description, numerous specific details are set forth to provide a thorough understanding of the present application, and the described embodiments are merely a subset of the embodiments of the present application, rather than all embodiments.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes all and any combination of one or more of the associated listed items.
In various embodiments of the present application, for convenience in description and not limitation, the term "coupled" as used in the specification and claims of the present application is not limited to physical or mechanical connections, either direct or indirect. "upper", "lower", "above", "below", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships are changed accordingly.
Referring to fig. 1 to 10, an embodiment of the present application provides a method for manufacturing a circuit board, including the following steps:
step S1: referring to fig. 1, an inner circuit substrate 10 is provided.
The inner circuit substrate 10 includes an inner dielectric layer 11, a first inner circuit layer 12 and a second inner circuit layer 13 on two opposite surfaces of the inner dielectric layer 11, and a portion of the inner dielectric layer 11 is exposed on the surfaces of the first inner circuit layer 12 and the second inner circuit layer 13. The inner-layer circuit substrate 10 further includes a conductive via (not shown) for electrically connecting the first inner-layer circuit layer 12 and the second inner-layer circuit layer 13.
Step S2: referring to fig. 2 to 4, a first intermediate circuit substrate 30 and a second intermediate circuit substrate 40 are respectively formed on two opposite surfaces of the inner circuit substrate 10, wherein the first intermediate circuit substrate 30 includes a first intermediate circuit layer 32, and the first intermediate circuit layer 32 includes a carrying portion 324 and a connecting portion 322 connected to the carrying portion 324.
The step of forming the first intermediate wiring substrate 30 and the second intermediate wiring substrate 40 may include steps S21 to S24.
Step S21: referring to fig. 2, a first copper clad laminate 35 and a second copper clad laminate 45 are provided, the first copper clad laminate 35 includes a first middle dielectric layer 31 and a first copper layer 352 which are stacked, and the second copper clad laminate 45 includes a second middle dielectric layer 41 and a second copper layer 452 which are stacked.
The first copper-clad plate 35 and the second copper-clad plate 45 are both single-sided copper-clad plates.
Step S22: the first copper-clad plate 35 and the second copper-clad plate 45 are respectively covered on two opposite surfaces of the inner layer circuit substrate 10, the first intermediate dielectric layer 31 covers the inner layer dielectric layer 11 and the first inner layer circuit layer 12, and the second intermediate dielectric layer 41 covers the inner layer dielectric layer 11 and the second inner layer circuit layer 13.
Step S23: referring to fig. 3, blind vias 355 are formed through the first copper layer 352 and the first interlayer dielectric layer 31.
Step S24: referring to fig. 4, the first copper layer 352 is patterned to form the first intermediate circuit layer 32, and the second copper layer 452 is patterned to form the second intermediate circuit layer 42; the first intermediate circuit layer 32 fills the blind via 355 to form the connecting portion 322 connected to the first intermediate dielectric layer 31, the first intermediate circuit layer 32 further includes a carrying portion 324 protruding from the connecting portion 322, and the protruding direction of the carrying portion 324 is at an angle, such as a right angle, with the extending direction of the connecting portion 322.
And step S3: referring to fig. 5, a through hole 50 is formed through the first intermediate circuit substrate 30, the inner layer circuit substrate 10 and the second intermediate circuit substrate 40, the connecting portion 322 is exposed to the through hole 50, and the supporting portion 324 protrudes from the through hole 50.
Opening to form the via 50. In the stacking direction of the circuit boards along the line, the surface of the connecting portion 322 is exposed to the through hole 50, and the bearing portion 324 connected with the connecting portion 322 protrudes from the through hole 50.
And step S4: referring to fig. 6, a ceramic sheet 52 is provided and disposed in the through hole 50 and on the supporting portion 324.
The bearing portion 324 and the connecting portion 322 form a bearing structure for bearing the ceramic sheet 52, at least a part of the ceramic sheet 52 is connected to the bearing portion 324, and the bearing portion 324 can be used for supporting the ceramic sheet 52 and preventing the ceramic sheet 52 from falling off from the through hole 50; in the process of supporting the ceramic sheet 52 by the supporting portion 324, when the stress is too large, the first intermediate circuit layer 32 and the first intermediate dielectric layer 31 tend to be separated, and the connecting portion 322 may abut against the ceramic sheet 52 to prevent the first intermediate circuit layer 32 and the first intermediate dielectric layer 31 from being separated.
Step S5: referring to fig. 7 to 8, an electronic component 54 is provided and disposed in the through hole 50 and on the ceramic sheet 52.
The electrical connection end of the electronic component 54 is disposed toward one side of the second intermediate circuit layer 42, so as to be electrically connected with the second intermediate circuit layer 42 later.
Referring to fig. 7, in some embodiments, before the step of disposing the electronic component 54 on the ceramic sheet 52, a thermal conductive adhesive 56 may be further coated on a surface of the ceramic sheet 52 facing away from the first intermediate circuit layer 32. The heat conducting glue 56 is used for bonding the ceramic sheet 52 and the electronic element 54; the heat conducting glue 56 has a heat conducting effect, so that heat generated by the electronic component 54 can be quickly transferred to the ceramic sheet 52, and the ceramic sheet 52 can perform a heat dissipation effect; meanwhile, the heat conducting glue 56 has certain flexibility after being cured, and has a buffering effect, so that the ceramic sheet 52 is prevented from being rigidly contacted with the electronic element 54 to be damaged.
Step S6: referring to fig. 9, a first outer layer circuit substrate 60 is formed on the surface of the first intermediate circuit substrate 30, and the first outer layer circuit substrate 60 covers the ceramic sheet 52; a second outer-layer circuit substrate 70 is formed on the surface of the second intermediate circuit substrate 40, and the second outer-layer circuit substrate 70 covers the electronic element 54.
In the present embodiment, the first outer layer circuit substrate 60 may include a first outer dielectric layer 61 and a third copper layer 65, and the third copper layer 65 may form a first outer layer circuit layer 62 in a subsequent process; the second outer wiring substrate 70 may include a second outer dielectric layer 71 and a fourth copper layer 75, which fourth copper layer 75 may form a second outer wiring layer 72 in subsequent processing. Namely, the first outer layer circuit substrate 60 and the second outer layer circuit substrate 70 are both single-sided copper clad laminates.
In some embodiments, the first outer layer circuit substrate 60 further includes a plurality of metal heat conduction holes (not shown), and each of the bearing portions 324 is connected to the third copper layer 65 through at least one metal heat conduction hole, so as to enhance the heat dissipation capability of the circuit board 100.
In other embodiments, the first outer circuit substrate 60 may also include a first outer dielectric layer 61 and a first outer circuit layer 62; the second outer wiring substrate 70 may also include a second outer dielectric layer 71 and a second outer wiring layer 72.
The first outer dielectric layer 61 is connected with the first intermediate circuit substrate 30 and covers the ceramic sheet 52; the second outer dielectric layer 71 is connected to the second intermediate circuit substrate 40 and covers the electronic component 54.
Step S7: referring to fig. 10, a connection block 85 connected to the ceramic sheet 52 is formed on the first outer layer circuit substrate 60, and a conductive via 86 connected to the electronic component 54 is formed on the second outer layer circuit substrate 70.
Referring to fig. 10 again, the present application further provides a circuit board 100, where the circuit board 100 includes a first outer layer circuit substrate 60, a first middle circuit substrate 30, an inner layer circuit substrate 10, a second middle circuit substrate 40, and a second outer layer circuit substrate 70 stacked in sequence, the circuit board 100 further includes at least one ceramic sheet 52 and at least one electronic element 54 penetrating through the first middle circuit substrate 30, the inner layer circuit substrate 10, and the second middle circuit substrate 40, the ceramic sheet 52 is located at a side close to the first middle circuit substrate 30, the electronic element 54 is located at a side close to the second middle circuit substrate 40, the ceramic sheet 52 is connected to the first outer layer circuit substrate 60 to facilitate rapid heat conduction, and the electronic element 54 is electrically connected to the second outer layer circuit substrate 70 through a conductive hole 86.
The inner circuit substrate 10 includes an inner dielectric layer 11, a first inner circuit layer 12 and a second inner circuit layer 13 on opposite surfaces of the inner dielectric layer 11. The ceramic sheet 52 and/or the electronic component 54 are disposed through the first inner circuit layer 12, the inner dielectric layer 11, and the second inner circuit layer 13.
The first intermediate circuit substrate 30 includes a first intermediate dielectric layer 31 and a first intermediate circuit layer 32, which are stacked, the first intermediate dielectric layer 31 connects the inner dielectric layer 11 and the first inner circuit layer 12, and the first intermediate circuit layer 32 is located on a surface of the first intermediate dielectric layer 31 facing away from the inner circuit substrate 10. The first intermediate circuit layer 32 includes a connection portion 322 and a bearing portion 324 connected to the connection portion 322, the connection portion 322 is disposed through the first intermediate dielectric layer 31 and connected to the ceramic sheet 52, and the bearing portion 324 is located at a periphery of the ceramic sheet 52 away from the electronic element 54 and supports the ceramic sheet 52; the connecting portion 322 and the bearing portion 324 are both connected to the ceramic sheet 52, so as to further improve the heat conduction performance of the ceramic sheet 52.
The second intermediate circuit substrate 40 includes a second intermediate dielectric layer 41 and a second intermediate circuit layer 42, which are stacked, the second intermediate dielectric layer 41 connects the inner dielectric layer 11 and the second inner circuit layer 13, and the second intermediate circuit layer 42 is located on a surface of the second intermediate dielectric layer 41 away from the inner circuit substrate 10.
The first outer circuit substrate 60 includes a first outer dielectric layer 61 and a first outer circuit layer 62, which are stacked, the first outer dielectric layer 61 connects the first intermediate dielectric layer 31 and the first intermediate circuit layer 32, and the first outer circuit layer 62 is located on a surface of the first outer dielectric layer 61 away from the first intermediate circuit substrate 30.
The second outer circuit substrate 70 includes a second outer dielectric layer 71 and a second outer circuit layer 72, which are stacked, the second outer dielectric layer 71 connects the second middle dielectric layer 41 and the second middle circuit layer 42, and the second outer circuit layer 72 is located on a surface of the second outer dielectric layer 71 facing away from the second middle circuit substrate 40.
First outer circuit layer 62 still is connected with intercommunication piece 85, intercommunication piece 85 wears to locate first outer dielectric layer 61, intercommunication piece 85 with ceramic chip 52 lug connection, intercommunication piece 85 still lug connection first outer circuit base plate 60, so that the heat that electronic component 54 produced passes through ceramic chip 52 gives first outer circuit base plate 60 the quick heat that gives off. The second outer layer circuit layer 72 is further connected with the conductive via 86, the conductive via 86 penetrates through the second outer layer dielectric layer 71, the conductive via 86 is electrically connected with the electronic element 54, and the conductive via 86 is further electrically connected with the second intermediate circuit substrate 40.
The circuit board 100 further includes a thermal conductive adhesive 56, and the thermal conductive adhesive 56 is located between the ceramic sheet 52 and the electronic component 54. The heat conducting glue 56 is used for bonding the ceramic sheet 52 and the electronic element 54; the heat conducting glue 56 also has a certain flexibility, and has a buffer effect, so as to prevent the ceramic sheet 52 and the electronic element 54 from being damaged.
The inner dielectric layer 11, the first intermediate dielectric layer 31, the second intermediate dielectric layer 41, the first outer dielectric layer 61, and the second outer dielectric layer 71 may be at least one selected from polypropylene, epoxy resin, polyurethane, phenol resin, urea resin, melamine-formaldehyde resin, unsaturated resin, polyimide, and the like.
According to the manufacturing method of the circuit board 100, the ceramic sheet 52 and the electronic element 54 which are connected with each other can be embedded simultaneously, the embedded density of the ceramic sheet 52 and the electronic element 54 in the circuit board 100 is high, and the ceramic sheet 52 is used for rapidly transferring heat generated by the electronic element 54, so that the density of the embedded element is improved, and the heat dissipation rate is effectively improved; by providing the first intermediate wiring substrate 30 including the carrier portion 324 and the connection portion 322 connected to the carrier portion 324, it is possible to prevent the first intermediate wiring layer 32 from tending to separate from the first intermediate dielectric layer 31; the bearing portion 324 and the connecting portion 322 are directly connected to the surface of the ceramic sheet 52, so that the contact area can be increased, and the heat dissipation efficiency can be effectively improved.
Although the present application has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the spirit and scope of the present application.
Claims (10)
1. The manufacturing method of the circuit board is characterized by comprising the following steps:
providing an inner layer circuit substrate;
forming a first intermediate circuit substrate and a second intermediate circuit substrate on two opposite surfaces of the inner layer circuit substrate respectively, wherein the first intermediate circuit substrate comprises a first intermediate circuit layer, and the first intermediate circuit layer comprises a bearing part and a connecting part connected with the bearing part;
forming through holes penetrating through the first intermediate circuit substrate, the inner layer circuit substrate and the second intermediate circuit substrate, wherein the bearing part extends in the through holes in a protruding mode;
providing a ceramic plate which is arranged in the through hole and is arranged on the bearing part;
providing an electronic element, placing the electronic element in the through hole and placing the electronic element on the ceramic chip;
forming a first outer layer circuit substrate on the surface of the first middle circuit substrate, wherein the first outer layer circuit substrate covers the ceramic sheet; forming a second outer layer circuit substrate on the surface of the second middle circuit substrate, wherein the second outer layer circuit substrate covers the electronic element; and
and forming a communicating block connected with the ceramic chip on the first outer layer circuit substrate, and forming a conductive hole connected with the electronic element on the second outer layer circuit substrate.
2. The method of claim 1, wherein the step of forming the first and second intermediate circuit substrates comprises:
providing a first copper-clad plate and a second copper-clad plate, wherein the first copper-clad plate comprises a first inner dielectric layer and a first copper layer which are arranged in a stacked manner, and the second copper-clad plate comprises a second inner dielectric layer and a second copper layer which are arranged in a stacked manner;
covering the first copper-clad plate and the second copper-clad plate on two opposite surfaces of the inner layer circuit substrate respectively;
forming a blind hole penetrating through the first copper-clad plate; and
carrying out circuit manufacturing on the first copper layer to form the first intermediate circuit layer, and carrying out circuit manufacturing on the second copper layer to form the second intermediate circuit layer; the first intermediate circuit layer is filled in the blind hole to form the connecting part and form the bearing part protruding out of the connecting part.
3. The method for manufacturing a circuit board according to claim 1, wherein the first outer circuit substrate includes a first outer dielectric layer and a first outer circuit layer, and the communication block is disposed through the first outer dielectric layer and electrically connected to the first outer circuit layer;
the second outer layer circuit substrate comprises a second outer layer dielectric layer and a second outer layer circuit layer, and the conductive hole penetrates through the second outer layer dielectric layer and is electrically connected with the second outer layer circuit layer.
4. The method of claim 1, wherein the first outer circuit substrate comprises a first outer dielectric layer and a third copper layer, and the second outer circuit substrate comprises a second outer dielectric layer and a fourth copper layer; the manufacturing method further comprises the following steps:
and carrying out circuit manufacturing on the third copper layer to form a first outer layer circuit layer and the communicating block penetrating through the first outer layer dielectric layer, and carrying out circuit manufacturing on the fourth copper layer to form a second outer layer circuit layer and the conductive hole penetrating through the second outer layer dielectric layer.
5. The method for manufacturing a circuit board according to claim 1, wherein after the step of providing at least one ceramic sheet disposed in the through hole and on the carrier, further comprising the steps of: and coating heat-conducting glue on the surface of the ceramic plate, which is far away from the first intermediate circuit layer.
6. A circuit board is characterized by comprising a first outer layer circuit substrate, a first middle circuit substrate, an inner layer circuit substrate, a second middle circuit substrate and a second outer layer circuit substrate which are sequentially stacked, and further comprising at least one ceramic sheet and at least one electronic element, wherein the ceramic sheet and the electronic element are stacked and penetrate through the inner layer circuit substrate and the second middle circuit substrate of the first middle circuit substrate; wherein, the circuit board is still including enclosing to be located the ceramic chip with at least partial circumferential heat conduction silica gel of electronic component, first intermediate line base plate includes first intermediate line layer, first intermediate line layer include connecting portion and with the bearing part that connecting portion are connected, bearing part with connecting portion with the ceramic chip is connected, connecting portion with heat conduction silica gel connects.
7. The circuit board of claim 6, further comprising a thermally conductive adhesive between the ceramic sheet and the electronic component.
8. The circuit board of claim 6, wherein the first intermediate circuit substrate comprises a first intermediate dielectric layer and the first intermediate circuit layer arranged in a stack; the second intermediate circuit substrate includes a second intermediate dielectric layer and the second intermediate circuit layer, which are stacked.
9. The circuit board of claim 6, wherein the first outer circuit substrate comprises a first outer dielectric layer and a first outer circuit layer, which are stacked, and the communication block is disposed through the first outer dielectric layer and electrically connected to the first outer circuit layer; the second outer circuit substrate comprises a second outer dielectric layer and a second outer circuit layer which are stacked, and the conductive hole penetrates through the second outer dielectric layer and is electrically connected with the second outer circuit layer.
10. The circuit board of claim 6, wherein the connecting portion and the carrier portion are perpendicular to each other.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110667909.2A CN115484755A (en) | 2021-06-16 | 2021-06-16 | Manufacturing method of circuit board and circuit board |
| TW110126152A TWI819335B (en) | 2021-06-16 | 2021-07-15 | Circuit board and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110667909.2A CN115484755A (en) | 2021-06-16 | 2021-06-16 | Manufacturing method of circuit board and circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115484755A true CN115484755A (en) | 2022-12-16 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110667909.2A Pending CN115484755A (en) | 2021-06-16 | 2021-06-16 | Manufacturing method of circuit board and circuit board |
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| Country | Link |
|---|---|
| CN (1) | CN115484755A (en) |
| TW (1) | TWI819335B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117241466A (en) * | 2023-11-13 | 2023-12-15 | 信丰迅捷兴电路科技有限公司 | Liquid cooling circuit board with embedded device and preparation method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9693445B2 (en) * | 2015-01-30 | 2017-06-27 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Printed circuit board with thermal via |
| KR102565119B1 (en) * | 2016-08-25 | 2023-08-08 | 삼성전기주식회사 | Electronic component embedded substrate and manufacturing method threrof |
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2021
- 2021-06-16 CN CN202110667909.2A patent/CN115484755A/en active Pending
- 2021-07-15 TW TW110126152A patent/TWI819335B/en active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117241466A (en) * | 2023-11-13 | 2023-12-15 | 信丰迅捷兴电路科技有限公司 | Liquid cooling circuit board with embedded device and preparation method thereof |
| CN117241466B (en) * | 2023-11-13 | 2024-01-26 | 信丰迅捷兴电路科技有限公司 | Liquid cooling circuit board with embedded device and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| TW202301926A (en) | 2023-01-01 |
| TWI819335B (en) | 2023-10-21 |
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