CN115483201A - 半导体封装 - Google Patents
半导体封装 Download PDFInfo
- Publication number
- CN115483201A CN115483201A CN202210644164.2A CN202210644164A CN115483201A CN 115483201 A CN115483201 A CN 115483201A CN 202210644164 A CN202210644164 A CN 202210644164A CN 115483201 A CN115483201 A CN 115483201A
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- semiconductor
- semiconductor chip
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- chip
- adhesive film
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Abstract
提供了一种半导体封装。该半导体封装包括:封装基板;安装在封装基板上的第一半导体芯片;安装在封装基板上的第二半导体芯片;提供在第一半导体芯片的上表面和第二半导体芯片的上表面上的粘合膜;以及第三半导体芯片,通过粘合膜附接到第一半导体芯片、第二半导体芯片。第一和第二半导体芯片具有不同的高度,并且粘合膜在其接触第一半导体芯片的部分处的厚度不同于粘合膜在其接触第二半导体芯片的部分处的厚度。
Description
技术领域
与示例实施方式一致的方法、装置和***涉及半导体封装,更具体地,涉及***级封装,其中不同类型的半导体芯片被包括在半导体封装中。
背景技术
在电子产品市场中,对轻便和紧凑的便携式设备的需求迅速增加,因此,对于安装在电子产品上的电子部件的需要是必须轻且小型化。为了实现电子部件的轻且小型化,安装在其上的半导体封装需要处理大量数据,同时减小其体积。因此,需要高集成度,并且需要安装在半导体封装上的半导体芯片的单一封装。
发明内容
一个或更多个示例实施方式提供了一种半导体封装,该半导体封装包括具有不同厚度且在其下端的半导体芯片,以在半导体封装的有限结构中有效地保护不同类型的半导体芯片。
示例实施方式所解决的问题不限于上述问题,考虑到以下描述,示例实施方式可以解决未提及的其他问题。
根据一示例实施方式的一方面,一种半导体封装包括:封装基板;安装在封装基板上的第一半导体芯片;安装在封装基板上的第二半导体芯片;提供在第一半导体芯片的上表面和第二半导体芯片的上表面上的粘合膜;以及第三半导体芯片,通过粘合膜附接到第一半导体芯片、第二半导体芯片。从封装基板的上表面到第一半导体芯片的上表面的第一距离不同于从封装基板的上表面到第二半导体芯片的上表面的第二距离,并且粘合膜在其接触第一半导体芯片的部分处的第一厚度不同于粘合膜在其接触第二半导体芯片的部分处的第二厚度。
根据一示例实施方式的一方面,一种半导体封装包括:印刷电路板;通过第一球栅阵列安装在印刷电路板上的第一半导体芯片;通过第二球栅阵列安装在印刷电路板上的第二半导体芯片;提供在第一半导体芯片的上表面和第二半导体芯片的上表面上的粘合膜;以及通过粘合膜附接到第一半导体芯片和第二半导体芯片的第三半导体芯片。第一半导体芯片的接触粘合膜的非有源表面比第二半导体芯片的非有源表面离印刷电路板更远。
根据一示例实施方式的一方面,一种半导体封装包括:彼此分开的多个下半导体芯片,所述多个下半导体芯片包括第一下半导体芯片和第二下半导体芯片;填充所述多个下半导体芯片之间的间隙的模制构件;提供在所述多个下半导体芯片的有源表面和模制构件上的粘合膜;以及提供在粘合膜上的上半导体芯片。第一下半导体芯片比第二下半导体芯片更窄并且具有更小的平面面积。
根据一示例实施方式的一方面,一种半导体封装包括:封装基板;安装在封装基板上的第一半导体芯片;将第一半导体芯片连接到封装基板的第一接合线;在第一半导体芯片周围安装在封装基板上的多个第二半导体芯片;将所述多个第二半导体芯片连接到封装基板的多个第二接合线;以及通过粘合膜附接到第一半导体芯片和所述多个第二半导体芯片的第三半导体芯片。所述多个第二半导体芯片中的每个包括多个堆叠的易失性存储器,第三半导体芯片包括多个堆叠的非易失性存储器,从封装基板的上表面到第一半导体芯片的上表面的第一距离不同于从封装基板的上表面到所述多个第二半导体芯片中的一个的上表面的第二距离,并且粘合膜在其接触第一半导体芯片的部分处的第一厚度不同于粘合膜在其接触第二半导体芯片的部分处的第二厚度。
附图说明
结合附图,从以下描述中将更清楚地理解上述和其他方面、特征和优点,附图中:
图1是根据一示例实施方式的半导体封装的主要部件的平面图;
图2是主要部件的沿着图1中的线X-X'截取的截面图;
图3至图5是图2中的主要部件的放大详细截面图;
图6示出了包括在半导体封装中的半导体芯片的翘曲的示意性截面图;
图7是根据一示例实施方式的半导体封装的主要部件的截面图;
图8是图7中的主要部件的放大详细截面图;
图9是根据一示例实施方式的半导体封装的主要部件的截面图;
图10是根据一示例实施方式的制造半导体封装的方法的工艺顺序的流程图;
图11至图16是示出根据示例实施方式的制造半导体封装的方法的截面图;以及
图17是根据一示例实施方式的半导体封装的示意性配置图。
具体实施方式
在下文中,参考附图详细描述示例实施方式。将理解,当一元件或层被称为“在另一元件或层上”、“连接到”或“联接到”另一元件或层时,它可以直接在所述另一元件或层上、直接连接到或联接到所述另一元件或层,或者可以存在中间元件或层。相比之下,当一元件被称为“直接在另一元件或层上”、“直接连接到”或“直接联接到”另一元件或层时,不存在中间元件或层。当在此使用时,术语“和/或”包括一个或更多个相关列出项目的任何和所有组合。当在一列元素之后时,诸如“……中的至少一个”的表述修饰整列的元素,而不修改该列中的单独元素。例如,表述“a、b和c中的至少一个”应理解为包括仅a、仅b、仅c、a和b两者、a和c两者、b和c两者、或全部a、b和c。
图1是根据一示例实施方式的半导体封装的主要部件的平面图,图2是主要部件的沿着图1中的线X-X'截取的截面图,图3是图2中的区域AA的放大截面图,图4是图2中的区域BB的放大截面图,以及图5是图2中的区域CC的放大截面图。
参考图1至图5,示出了包括封装基板PS、第一、第二和第三半导体芯片100、200和300、模制构件400和外部连接端子500的半导体封装10。
半导体封装10可以具有多个半导体芯片安装在封装基板PS上的结构。在图1和图2中,示出了总共四个半导体芯片安装在封装基板PS上,但是半导体芯片的数量不限于此。
第一和第二半导体芯片100和200可以在封装基板PS的上表面上在彼此交叉的第一水平方向(X方向)和第二水平方向(Y方向)上彼此分开布置,并且第三半导体芯片300可以在垂直于封装基板PS的上表面的垂直方向(Z方向)上以堆叠形状安装在第一和第二半导体芯片100和200上。
为了便于描述,相同类型的半导体芯片可以被视为一个。换句话说,第一、第二和第三半导体芯片100、200和300可以用来表示有三种不同类型的半导体芯片。
在一些示例实施方式中,第一半导体芯片100可以包括非存储器芯片,第二和第三半导体芯片200和300可以包括存储器芯片。第一半导体芯片100可以包括控制器芯片或逻辑芯片,第二半导体芯片200可以包括易失性存储器芯片,第三半导体芯片300可以包括非易失性存储器芯片。然而,第一、第二和第三半导体芯片100、200和300的类型不限于此。
构成第一半导体芯片100的非存储器芯片可以实现为例如控制器、微处理器、图形处理器、信号处理器、网络处理器、芯片组、音频编解码器、视频编解码器、应用处理器、片上***等,但不限于此。微处理器可以包括例如单核或多核。
构成第二半导体芯片200的易失性存储器芯片可以包括例如现有的易失性存储器芯片,诸如动态随机存取存储器(RAM)(DRAM)、静态RAM(SRAM)、晶闸管RAM(TRAM)、零电容器RAM(ZRAM)和双晶体管RAM(TTRAM),以及正在开发的易失性存储器芯片。或者,易失性存储器芯片可以包括高带宽存储器芯片。
构成第三半导体芯片300的非易失性存储器芯片可以包括例如现有的非易失性存储器芯片,诸如闪存、磁性RAM(MRAM)、自旋转移矩RAM(STT-MRAM)、铁电RAM(FRAM)、相变RAM(PRAM)、电阻RAM(RRAM)、纳米管RRAM、聚合物RAM、纳米浮栅存储器、全息存储器、分子电子存储器和绝缘体电阻变化存储器,以及正在开发的非易失性存储器芯片。
在其他示例实施方式中,第一和第三半导体芯片100和300可以包括有源芯片,第二半导体芯片200可以包括虚设芯片。然而,第一、第二和第三半导体芯片100、200和300的类型不限于此。
构成第二半导体芯片200的虚设芯片可以布置在其中有源芯片不在封装基板PS上的空区域中,并且可以用作支撑构件以支撑其他半导体芯片。当第一和第三半导体芯片100和300包括诸如硅晶片的半导体基板时,构成第二半导体芯片200的虚设芯片可以包括相同或相似的材料。
下面给出关于第一、第二和第三半导体芯片100、200和300中的每个的部件的详细描述。
第一半导体芯片100可以包括第一半导体基板101、第一连接焊盘120和第一连接构件130。
第一半导体基板101可以具有有源表面和与有源表面相反的非有源表面。在这种情况下,第一半导体基板101的非有源表面可以包括面向封装基板PS的上表面的面。多个有源/无源部件可以形成在第一半导体基板101的有源表面上,并且第一连接焊盘120可以形成在其上。
第一半导体基板101可以包括例如硅。或者,第一半导体基板101可以包括诸如锗(Ge)的半导体元素,或者诸如硅碳化物(SiC)、镓砷化物(GaAs)、铟砷化物(InAs)和铟磷化物(InP)的化合物半导体。或者,第一半导体基板101可以具有绝缘体上硅(SOI)结构。例如,第一半导体基板101可以包括掩埋氧化物(BOX)层。第一半导体基板101可以包括导电区域,例如掺有杂质的阱或掺有杂质的结构。此外,第一半导体基板101可以具有各种器件隔离结构,诸如浅沟槽隔离(STI)结构。
第一粘合膜110可以在第一半导体基板101的非有源表面和封装基板PS之间。第一半导体芯片100可以通过第一粘合膜110稳定地附接到封装基板PS。第一粘合膜110可以包括例如管芯附接膜(DAF)。DAF可以分为无机粘合剂和聚合物粘合剂,并且可以是无机粘合剂与聚合物粘合剂结合的混合类型。
第一连接焊盘120可以布置在第一半导体基板101的有源表面上,并且可以电连接到第一半导体芯片100中的半导体布线层。半导体布线层可以经由第一连接焊盘120电连接到第一连接构件130。第一连接焊盘120可以包括例如铝(Al)、铜(Cu)、镍(Ni)、钨(W)、铂(Pt)和金(Au)。
第一连接构件130可以电连接到第一半导体芯片100和封装基板PS。第一连接构件130可以包括以球焊方法附接到第一连接焊盘120的接合线。构成接合线的材料可以包括Au、银(Ag)、Cu和Al中的至少一种。在一些示例实施方式中,接合线可以通过使用热压连接方法和超声波连接方法中的任何一种连接到第一连接焊盘120,并且也可以通过使用热声连接方法连接到第一连接焊盘120,热声连接方法将热压连接方法与超声波连接方法相结合。
用于第一半导体芯片100的操作的控制信号、电源信号和接地信号中的至少一个可以经由第一连接构件130从外部提供,或者指示要存储在第一半导体芯片100中的数据的数据信号可以从外部提供,或者指示存储在第一半导体芯片100中的数据的数据信号可以被提供到外部。
如上所述,第二半导体芯片200可以包括易失性存储器芯片,或者在一些情况下,可以包括虚设芯片。因此,针对每种情况描述第二半导体芯片200。
在一示例实施方式中,第二半导体芯片200可以包括第二半导体基板201、第二连接焊盘220和第二连接构件230。第二半导体芯片200可以配置有多个片,并且多个片可以配置为多个第二半导体基板201、202、203和204。多个第二半导体基板201、202、203和204可以构成芯片堆叠,其中第二半导体基板201、202、203和204在垂直方向(Z方向)上堆叠。多个第二半导体基板201、202、203和204可以彼此基本相同。例如,第二半导体芯片200可以包括各自作为易失性存储器芯片工作的多个片,并且可以具有其中多个片被堆叠的结构。
第二半导体基板201可以具有有源表面和与有源表面相反的非有源表面。在这种情况下,第二半导体基板201的非有源表面可以包括面向封装基板PS的上表面的面。多个存储器部件可以形成在第二半导体基板201的有源表面上,并且第二连接焊盘220可以形成在第二半导体基板201的有源表面上。
第二粘合膜210可以在第二半导体芯片200中包括的多个第二半导体基板201、202、203和204中的每两个之间,以及在第二半导体芯片200和封装基板PS之间。第二半导体芯片200可以通过第二粘合膜210稳定地附接到封装基板PS并堆叠在封装基板PS上。第二粘合膜210可以包括例如DAF。
第二连接焊盘220可以布置在第二半导体基板201的有源表面上,并且第二连接构件230可以布置成将第二半导体芯片200电连接到封装基板PS。
在另一示例实施方式中,当第二半导体芯片200包括仅起到支撑构件的作用的虚设芯片时,第二半导体芯片200可以被配置为一个第二半导体基板201。此外,在这种情况下,存储元件、第二连接焊盘220和第二连接构件230可以不形成在第二半导体芯片200中。换句话说,虚设芯片可以像所谓的支石墓(dolmen)结构一样仅起到结构支撑的作用,使得第三半导体芯片300不会掉落或弯曲。
第三半导体芯片300可以包括第三半导体基板301、第三连接焊盘320和第三连接构件330。第三半导体芯片300可以包括多个第三半导体基板301和302。多个第三半导体基板301和302可以构成芯片堆叠,其中第三半导体基板301和第三半导体基板302在垂直方向(Z方向)上堆叠。多个第三半导体基板301和302可以彼此基本相同。例如,第三半导体芯片300可以包括各自作为非易失性存储器芯片工作的多个片,并且可以具有其中多个片被堆叠的结构。
第三半导体基板301可以具有有源表面和与有源表面相反的非有源表面。在这种情况下,第三半导体基板301的非有源表面可以包括面向封装基板PS的上表面的面。多个存储器部件可以形成在第三半导体基板301的有源表面上,并且第三连接焊盘320可以形成在其上。
第三粘合膜310可以布置在第三半导体芯片300的下部上。换句话说,第三半导体芯片300可以布置在第三粘合膜310的上表面上,并且第一和第二半导体芯片100和200可以布置在第三粘合膜310的下表面上。第三半导体芯片300可以通过第三粘合膜310稳定地附接到第一和第二半导体芯片100和200并堆叠在第一和第二半导体芯片100和200上。第三粘合膜310可以包括例如DAF。
第三连接焊盘320可以布置在第三半导体基板301的有源表面上,并且第三连接构件330可以布置成将第三半导体芯片300电连接到封装基板PS。
除了前面的描述之外,第二和第三半导体芯片200和300可以具有与第一半导体芯片100基本相同或相似的特性,因此,省略对第二和第三半导体芯片200和300的详细描述。
在根据示例实施方式的半导体封装10中,第一半导体芯片100中的一个可以在多个第二半导体芯片200之间。此外,第一半导体芯片100中的所述一个的平面面积(即,侧表面面积)可以大于多个第二半导体芯片200中的每个的平面面积(即,侧表面面积)。此外,第三半导体芯片300可以被布置成通过第三粘合膜310堆叠在第一半导体芯片100中的所述一个和所述多个第二半导体芯片200上。结果,第一连接构件130和第二连接构件230可以布置成穿过第三粘合膜310的内部。
在半导体封装10中,多个第二半导体芯片200的侧壁可以在垂直方向(Z方向)上与第三半导体芯片300的侧壁并排布置。多个第二半导体芯片200中的每个的一个侧壁可以在垂直方向(Z方向)上布置在与第三半导体芯片300的一个侧壁相同的平面上,并且另外的多个第二半导体芯片200中的每个的另一个侧壁可以在垂直方向(Z方向)上布置在与第三半导体芯片300的另一个侧壁相同的平面上。然而,第一、第二和第三半导体芯片100、200和300的布置不限于此。
在半导体封装10中,第一半导体芯片100的最上表面100T的水平可以比第二半导体芯片200的最上表面200T的水平高(即,离封装基板PS更远)。因此,第一半导体芯片100的最上表面100T可以比第二半导体芯片200的最上表面200T高出第一间隔T1。在这种情况下,第一间隔T1可以是约20μm至约100μm,但是不限于此。换句话说,第一半导体芯片100的厚度可以大于第二半导体芯片200的厚度。
在半导体封装10中,第三粘合膜310可以形成为使得其面对第一半导体芯片100的最上表面100T的部分是凹入的。如下所述,第三半导体芯片300可以在某个方向上具有翘曲。
由于上述特性,在半导体封装10中,第一半导体芯片100的上部可以被掩埋在第三粘合膜310中。换句话说,第三粘合膜310可以接触第一半导体芯片100的最上表面100T,此外,可以接触第一半导体芯片100的从最上表面100T延伸的侧壁的一部分。此外,第三粘合膜310的接触第一半导体芯片100的部分的第一厚度310T1可以小于第三粘合膜310的接触第二半导体芯片200的部分的第二厚度310T2。
下面给出关于除了第一、第二和第三半导体芯片100、200和300之外的部件的详细描述。
封装基板PS可以作为支撑基板包括主体部分、下保护层和上保护层。封装基板PS可以由作为基底的印刷电路板(PCB)、晶片基板、陶瓷基板、玻璃基板、中介层(interposer)等来形成。根据示例实施方式,封装基板PS可以包括PCB。然而,封装基板PS不限于PCB。
外部连接端子500可以布置在封装基板PS的下表面上在下电极焊盘PS1上。封装基板PS可以经由外部连接端子500电连接到电子产品的模块基板、***板等。
此外,布线可以形成在封装基板PS上,并且布线可以经由连接到封装基板PS的上表面上的上电极焊盘PS2的第一、第二和第三连接构件130、230和330电连接到第一、第二和第三半导体芯片100、200和300。
模制构件400可以围绕第一、第二和第三半导体芯片100、200和300的侧表面、下表面和上表面。为了便于描述,模制构件400的内部在附图中被示为透明的,但是模制构件400不限于此。
模制构件400可以包括环氧模塑料(epoxy molding compound)。环氧模塑料可以具有约15GPa至约30GPa的杨氏模量,和约3ppm至约30ppm的热膨胀系数。模制构件400可以不限于环氧模塑料,而是可以包括各种材料,例如环氧基材料、热固性材料、热塑性材料、紫外线(UV)处理材料等。热固性材料可以包括酚型、酸酐型和胺型固化剂,以及丙烯酸聚合物添加剂。
模制构件400可以通过使用模制底部填充(MUF)工艺形成,因此,提供在第一、第二和第三半导体芯片100、200和300的外周上的材料可以与填充第一、第二和第三半导体芯片100、200和300以及封装基板PS之间的空间的材料相同。
模制构件400可以具有通过使用注射工艺注射到封装基板PS上的适量的模制材料,并且可以通过使用固化工艺形成半导体封装10的轮廓。在使用压力机的压制过程中可以向模制材料施加压力,并且可以形成半导体封装10的轮廓。在这种情况下,可以考虑模制材料的诸如粘度的物理性质来设定工艺条件,诸如模制材料的注射时间和加压时间之间的延迟时间、要注射的模制材料的量、以及加压温度/压力。
模制构件400可以保护第一、第二和第三半导体芯片100、200和300免受诸如污染和冲击的外部影响。在这点上,模制构件400的厚度可以形成为至少围绕所有的第一、第二和第三半导体芯片100、200和300。因为模制构件400完全覆盖封装基板PS,所以模制构件400的宽度可以与半导体封装10的宽度基本相同。
最近,在电子产品市场中,对便携式设备的需求迅速增加,因此,安装在电子产品上的电子部件被持续要求轻且小型化。为了使电子部件轻且小型化,安装在其上的半导体封装10需要处理大量数据,同时减小其体积。
因此,存在对安装在半导体封装10上的半导体芯片进行集成和单一封装的需求。因此,为了在半导体封装10的有限结构中有效地布置半导体芯片,已经应用了***级封装。
然而,在一般的***级封装中,不同类型的半导体芯片彼此非常靠近地布置,并且形成填充其间的空间的模制构件。因此,应力出现在构成封装基板、半导体芯片、粘合构件和模制构件的不同材料之间。因此,当在用于制造半导体封装的制造工艺(例如,固化工艺)期间温度变化时,每个部件不同地收缩或膨胀,这导致每个部件的部分变形。诸如空隙的缺陷可出现在应力最大化的区域(例如,半导体芯片接触粘合构件的区域)。结果,模制构件渗透到空隙中,并且出现裂纹。在随后的工艺(例如,将半导体封装安装在主板上的工艺)中,裂纹可扩展到半导体芯片并导致半导体封装中的缺陷。
为了解决该问题,在根据示例实施方式的半导体封装10中,为了充分抑制由于在第一、第二和第三半导体芯片100、200和300彼此面对的区域中的材料之间的差异而产生的应力,并且最小化第三粘合膜310中的空隙,第一、第二和第三半导体芯片100、200和300可以更有效地布置在封装基板PS上。
在根据示例实施方式的半导体封装10中,考虑到对应于半导体芯片的第三半导体芯片300的翘曲,对应于其下端上的半导体芯片的第一和第二半导体芯片100和200的厚度可以形成为彼此不同。以这种方式,第一和第二半导体芯片100和200与第三粘合膜310之前的粘合面积增加。因此,在固化工艺期间出现的空隙可以被有效地去除。换句话说,可以通过减少与半导体封装10内部的空隙一起出现的裂纹来防止半导体封装10的缺陷。
结果,根据示例实施方式的半导体封装10可以通过减少由于高度集成的***级封装中的裂纹导致的缺陷来提高产品的可靠性和生产率。
图6示出了包括在半导体封装中的半导体芯片的翘曲的示意性截面图。
参考图6,为了便于解释,第三粘合膜310在此可以被包括作为第三半导体芯片300的部件,并且示出了包括第三半导体基板301和附接到第三半导体基板301的第三粘合膜310的第三半导体芯片300的形状。
当在制造第三半导体芯片300的工艺期间温度变化时,构成第三半导体芯片300的材料可收缩或膨胀,并且不同的材料可以以不同的速率收缩或膨胀。这种收缩和膨胀可导致在第三半导体基板301中的诸如弯曲的变形。第三半导体基板301的变形可以被称为翘曲。
由于第三半导体基板301的翘曲,第三半导体芯片300可不平坦,并且可出现在其中心部分和***部分之间的高度差300S和300C。结果,可导致半导体封装(参考图2的10)的如上所述的空隙缺陷和裂纹。
在根据示例实施方式的半导体封装(参考图2的10)中,通过应对对应于其上端的半导体芯片的第三半导体芯片300的翘曲,其下端的半导体芯片的厚度可以形成为彼此不同。以这种方式,通过增加半导体封装(参考图2的10)的下端上的半导体芯片与第三粘合膜310之间的粘合面积,可以有效地去除固化工艺期间出现的空隙。以这种方式,可以通过减少与半导体封装(参考图2的10)中的空隙一起出现的裂纹来防止半导体封装(参考图2的10)的缺陷。
图7是根据示例实施方式的半导体封装的主要部件的截面图,图8是图7中的区域DD的放大截面图。
构成半导体封装20的部件中的大多数和包括在下面将要描述的部件中的材料可以与参考图1至5描述的那些基本相同或相似。因此,为了便于描述,主要描述与上述半导体封装10的不同之处。
一起参考图7和图8,示出了包括封装基板PS、第一、第二和第三半导体芯片100A、200A和300、模制构件400和外部连接端子500的半导体封装20。
在半导体封装20中,第一半导体芯片100A和第二半导体芯片200A可以通过使用球栅阵列(BGA)方法安装在封装基板PS上。
第一半导体芯片100A中包括的第一半导体基板101可以经由具有焊料凸块形状的第一连接构件112(例如,焊料球)电连接到封装基板PS。
第二半导体芯片200A中包括的多个第二半导体基板201、202和203可以经由具有焊料凸块形状的第二连接构件212(例如,焊料球)电连接到封装基板PS。
此外,第二半导体芯片200A可以包括存储器芯片组,该存储器芯片组包括多个第二半导体基板201、202和203,它们是能够在它们之间组合数据的多个片。
第二半导体芯片200A中包括的第二半导体基板201、202和203的数量可以根据半导体封装20的应用而变化。换句话说,第二半导体芯片200A中包括的第二半导体基板201、202和203的数量不限于图8所示的数量。
第二半导体芯片200A中包括的多个第二半导体基板201、202和203中的至少一些可以包括贯穿其中的贯通电极240。贯通电极240可以包括例如贯通硅通路(TSV)。
多个第二半导体基板201、202和203中的每个可以具有有源表面和与有源表面相反的非有源表面。在这种情况下,多个第二半导体基板201、202和203中的每个的有源表面可以包括面对封装基板PS的上表面的表面。
换句话说,在半导体封装20中,与半导体封装(参考图2的10)相比,第一半导体芯片100A和第二半导体芯片200A可以不使用接合线作为连接构件,而是使用焊料球作为连接构件,因此,可以电连接到封装基板PS。
图9是根据示例实施方式的半导体封装30的主要部件的截面图。
构成半导体封装30的部件中的大多数和包括在下面将要描述的部件中的材料可以与参考图1至5描述的那些基本相同或相似。因此,为了便于描述,主要描述与上述半导体封装10的不同之处。
参考图9,示出了包括封装基板PS、第一、第二和第三半导体芯片100、200和300、模制构件400和外部连接端子500的半导体封装30。
在半导体封装30中,第一半导体芯片100中的一个可以位于多个第二半导体芯片200之间。此外,第三半导体芯片300可以被布置成通过第三粘合膜313堆叠在第一半导体芯片100中的所述一个和所述多个第二半导体芯片200上。
在半导体封装30中,第一半导体芯片100的最上表面100T的水平可以比第二半导体芯片200的最上表面200T的水平低(即,更靠近封装基板PS)。因此,第一半导体芯片100的最上表面100T可以比第二半导体芯片200的最上表面200T低第二间隔T2。在这种情况下,第二间隔T2可以是约20μm至约100μm,但不限于此。换句话说,第一半导体芯片100的厚度可以小于第二半导体芯片200的厚度。
在半导体封装30中,第三粘合膜313可以形成为使得其面对第一半导体芯片100的最上表面100T的部分是凸起的。
由于这些特性,在半导体封装30中,第二半导体芯片200的顶部可以掩埋在第三粘合膜313中。换句话说,第三粘合膜313可以接触第二半导体芯片200的最上表面200T,此外,可以接触第二半导体芯片200的从最上表面200T延伸的侧壁的一部分。
换句话说,在半导体封装30中,与半导体封装(参考图2的10)相比,第二半导体芯片200可以形成为比第一半导体芯片100厚,并且第三粘合膜313可以根据其形状布置。
图10是根据一示例实施方式的制造半导体封装的方法S10的工艺顺序的流程图。
参考图10,制造半导体封装的方法S10可以包括第一至第七操作S110至S170的工艺顺序。
当不同地实现一示例实施方式时,特定工艺顺序可以不同于将要描述的顺序来执行。例如,两个连续描述的工艺可以基本上同时执行,或者以与将要描述的顺序相反的顺序执行。
根据示例实施方式的制造半导体封装的方法S10可以包括以下操作,但不限于此。
制造半导体封装的方法S10可以包括准备封装基板的第一操作S110、在准备好的封装基板上安装第一半导体芯片的第二操作S120、在封装基板上在第一半导体芯片的***安装第二半导体芯片的第三操作S130、在第一和第二半导体芯片上定位第三半导体芯片的第四操作S140、将第三半导体芯片附接在第一和第二半导体芯片上的第五操作S150、形成模制构件以围绕第一至第三半导体芯片的第六操作S160、以及在封装基板的下表面上形成外部连接端子的第七操作S170。
下面参考图11至图16详细描述第一至第七操作S110至S170中的每个的技术特征。
图11至图16是示出根据示例实施方式的依照工艺顺序制造半导体封装的方法的截面图。
参考图11,首先,可以在操作S110中准备封装基板PS。
封装基板PS可以作为支撑基板包括主体部分、下保护层和上保护层。封装基板PS可以包括PCB、晶片基板、陶瓷基板、玻璃基板、中介层等。在一示例实施方式中,封装基板PS可以包括PCB。
在PCB中,主体部分可以通过以下来实现:将聚合物材料诸如热固性树脂、环氧树脂或酚醛树脂(诸如阻燃剂4(FR-4)、双马来酰亚胺三嗪(BT)和味之素堆积膜(ABF))挤压到一定厚度,将压制结果形成为薄层,在形成的薄层的两侧涂覆铜层,以及通过图案化形成作为电信号的传输路径的布线。可以通过在主体部分的所有下表面和上表面上(除了上电极焊盘PS2和下电极焊盘PS1之外)掺杂阻焊剂来实现下保护层和上保护层。
PCB可以是其中布线仅形成在其一侧的单面PCB,或者是其中布线形成在其两个表面上的双面PCB。此外,铜层的数量可以通过使用诸如预浸料的绝缘体形成为3层或更多层,并且具有多层结构的PCB可以通过根据形成的铜层的数量形成3条或更多条布线来实现。
参考图12,在操作S120中,可以在准备好的封装基板PS上安装第一半导体芯片100。
第一半导体芯片100可以安装在封装基板PS的中央部分处的芯片安装区域中。第一半导体芯片100可以包括第一半导体基板101、第一连接焊盘和第一连接构件。
第一半导体基板101可以具有有源表面和与有源表面相反的非有源表面。在这种情况下,第一半导体基板101的非有源表面可以包括面对封装基板PS的上表面的面。多个有源/无源元件可以形成在第一半导体基板101的有源表面上。
第一粘合膜110可以在第一半导体基板101的非有源表面和封装基板PS之间。第一半导体芯片100可以通过第一粘合膜110稳定地附接到封装基板PS。
参考图13,在操作S130中,可以在封装基板PS上在第一半导体芯片100的***安装第二半导体芯片200。
多个第二半导体芯片200可以安装在封装基板PS的***部分处的芯片安装区域中。第二半导体芯片200可以包括第二半导体基板201、第二连接焊盘和第二连接构件。
第二半导体基板201可以具有有源表面和与有源表面相反的非有源表面。在这种情况下,第二半导体基板201的非有源表面可以包括面对封装基板PS的上表面的面。多个存储元件可以形成在第二半导体基板201的有源表面上。
第二粘合膜210可以在第二半导体基板201的非有源表面和封装基板PS之间。第二半导体芯片200可以通过第二粘合膜210稳定地附接到封装基板PS。
或者,第二半导体芯片200可以包括虚设芯片。构成第二半导体芯片200的虚设芯片可以布置在其中有源芯片不在封装基板PS上的空区域中,并且可以起到支撑其他半导体芯片的支撑构件的作用。
在一示例实施方式中,第一半导体芯片100的最上表面的水平可以比第二半导体芯片200的最上表面的水平高(即,离封装基板PS更远)。第一半导体芯片100的最上表面可以比第二半导体芯片200的最上表面高约20μm到约100μm的间隔,但是不限于此。换句话说,第一半导体芯片100的厚度可以大于第二半导体芯片200的厚度。
参考图14,在操作S140中,可以在第一和第二半导体芯片100和200上提供第三半导体芯片300。
在第三半导体芯片300提供在第一和第二半导体芯片100和200上之后,可以向第三半导体芯片300施加压力PA。第三半导体芯片300可以包括第三半导体基板301、第三连接焊盘和第三连接构件。
第三半导体基板301可以具有有源表面和与有源表面相反的非有源表面。在这种情况下,第三半导体基板301的非有源表面可以包括面对第一和第二半导体芯片100和200的表面。多个存储元件可以形成在第三半导体基板301的有源表面上。
第三粘合膜310可以布置在第三半导体芯片300的下部。换句话说,第三半导体芯片300可以布置在第三粘合膜310的上表面上,并且第一和第二半导体芯片100和200可以布置在第三粘合膜310的下表面之下。
参考图15,在操作S150中,第三半导体芯片300可以附接在第一和第二半导体芯片100和200上。
第三半导体芯片300可以通过第三粘合膜310稳定地附接到第一和第二半导体芯片100和200并堆叠在第一和第二半导体芯片100和200上。第三粘合膜310可以包括例如DAF。
第三连接焊盘可以布置在第三半导体芯片300的有源表面上,并且第三连接构件可以布置成将第三半导体芯片300电连接到封装基板PS。
在示例实施方式中,第一半导体芯片100的上部可以掩埋在第三粘合膜310中。换句话说,第三粘合膜310可以接触第一半导体芯片100的最上表面,此外,可以接触第一半导体芯片100的从最上表面延伸的侧壁的一部分。此外,第三粘合膜310的接触第一半导体芯片100的部分的厚度可以小于第三粘合膜310的接触第二半导体芯片200的部分的厚度。
参考图16,在操作S160中,可以形成模制构件400以围绕第一、第二和第三半导体芯片100、200和300。
模制构件400可以形成在封装基板PS上,以围绕第一、第二和第三半导体芯片100、200和300的侧表面、下表面和上表面。模制构件400可以由例如环氧模塑料形成。模制构件400可以不限于环氧模塑料,而是可以包括各种材料,例如环氧基材料、热固性材料、热塑性材料、UV处理材料等。
模制构件400的侧表面和上表面可以具有矩形形状。在沿着切割线将封装基板PS切割成分立的半导体封装的过程中,每个分立半导体封装中的模制构件400的侧表面和上表面通常可以具有矩形形状。在模制构件400的侧表面的一部分中,可以形成包括关于半导体封装的信息的标记图案(例如,条形码、数字、字母、符号等)。
再次参考图2,在操作S170中,可以在封装基板PS的下表面上在下电极焊盘PS1上形成外部连接端子500。封装基板PS可以经由要安装到其上的外部连接端子500电连接到电子产品的模块基板、***板等。
通过使用上述制造半导体封装10的方法,可以制造根据示例实施方式的半导体封装10。结果,根据示例实施方式的半导体封装10可以通过减少由于高度集成的***级封装中的裂纹导致的缺陷来提高产品的可靠性和生产率。
图17是根据一示例实施方式的半导体封装1000的示意性配置图。
参考图17,半导体封装1000可以包括微处理器(MPU)1010、存储器1020、接口1030、图形处理器(GPU)1040、功能块(即电路)1050以及连接这些部件的***总线1060。半导体封装1000可以包括微处理器1010和图形处理器1040两者,或者也可以仅包括所述两个部件中的一个。
微处理器1010可以包括核和高速缓存。例如,微处理器1010可以包括多核。多核中的每个核可以具有相同或相似的性能。此外,多核的每个核可以同时激活,也可以有不同的激活时间点。
存储器1020可以存储在微处理器1010的控制下由功能块1050处理的结果等。接口1030可以与外部设备交换信息或信号。图形处理器1040可以执行图形功能。例如,图形处理器1040可以使用视频编解码器编码和/或解码视频,或者处理三维(3D)图形。功能块1050可以执行各种功能。例如,当半导体封装1000是移动设备使用的应用处理器时,一些功能块1050可以执行通信相关功能。
半导体封装1000可以包括上面参考图1至图9描述的半导体封装10、20和30中的任何一个。
虽然已经具体示出和描述了示例实施方式,但是将理解,在不脱离所附权利要求的精神和范围的情况下,可以在此进行在形式和细节上的各种改变。
本申请要求于2021年6月15日向韩国知识产权局提交的第10-2021-0077421号韩国专利申请的优先权,其公开内容通过引用整体结合于此。
Claims (20)
1.一种半导体封装,包括:
封装基板;
安装在所述封装基板上的第一半导体芯片;
安装在所述封装基板上的第二半导体芯片;
粘合膜,提供在所述第一半导体芯片的上表面和所述第二半导体芯片的上表面上;以及
第三半导体芯片,通过所述粘合膜附接到所述第一半导体芯片、所述第二半导体芯片,
其中从所述封装基板的上表面到所述第一半导体芯片的所述上表面的第一距离不同于从所述封装基板的所述上表面到所述第二半导体芯片的所述上表面的第二距离,以及
其中所述粘合膜在其接触所述第一半导体芯片的部分处的第一厚度不同于所述粘合膜在其接触所述第二半导体芯片的部分处的第二厚度。
2.根据权利要求1所述的半导体封装,其中所述第一距离大于所述第二距离,以及
其中所述粘合膜的所述第一厚度小于所述粘合膜的所述第二厚度。
3.根据权利要求2所述的半导体封装,其中所述第一距离比所述第二距离大20μm至100μm。
4.根据权利要求2所述的半导体封装,其中所述粘合膜的面对所述第一半导体芯片的所述上表面的部分是凹入的。
5.根据权利要求2所述的半导体封装,其中所述粘合膜接触所述第一半导体芯片的侧壁。
6.根据权利要求1所述的半导体封装,其中所述第一半导体芯片包括控制器芯片或逻辑芯片,
其中所述第二半导体芯片包括虚设芯片,以及
其中所述第三半导体芯片包括存储器芯片。
7.根据权利要求1所述的半导体封装,还包括:
将所述第一半导体芯片连接到所述封装基板的第一接合线;
将所述第二半导体芯片连接到所述封装基板的第二接合线;以及
将所述第三半导体芯片连接到所述封装基板的第三接合线,
其中所述第一接合线和所述第二接合线穿透所述粘合膜。
8.根据权利要求1所述的半导体封装,其中所述第二半导体芯片和所述第三半导体芯片中的每个的多个片形成芯片堆叠。
9.根据权利要求1所述的半导体封装,其中所述第二半导体芯片包括多个第二半导体芯片,以及
所述第一半导体芯片布置在所述多个第二半导体芯片之间。
10.根据权利要求9所述的半导体封装,还包括模制构件,所述模制构件提供在所述第一半导体芯片、所述多个第二半导体芯片和所述第三半导体芯片中的每个上,并且填充所述第一半导体芯片和所述多个第二半导体芯片之间的所有间隙。
11.一种半导体封装,包括:
印刷电路板;
第一半导体芯片,通过第一球栅阵列安装在所述印刷电路板上;
第二半导体芯片,通过第二球栅阵列安装在所述印刷电路板上;
粘合膜,提供在所述第一半导体芯片的上表面和所述第二半导体芯片的上表面上;以及
第三半导体芯片,通过所述粘合膜附接到所述第一半导体芯片和所述第二半导体芯片,
其中所述第一半导体芯片的接触所述粘合膜的非有源表面比所述第二半导体芯片的接触所述粘合膜的非有源表面离所述印刷电路板更远。
12.根据权利要求11所述的半导体封装,其中所述粘合膜在其接触所述第一半导体芯片的部分处的第一厚度小于所述粘合膜在其接触所述第二半导体芯片的部分处的第二厚度。
13.根据权利要求12所述的半导体封装,其中所述粘合膜接触所述第一半导体芯片的侧壁的一部分。
14.根据权利要求11所述的半导体封装,其中所述第二半导体芯片包括多个虚设半导体芯片,以及
其中所述第一半导体芯片布置在所述多个虚设半导体芯片之间。
15.根据权利要求14所述的半导体封装,还包括模制构件,所述模制构件提供在所述第一半导体芯片、所述多个虚设半导体芯片和所述第三半导体芯片中的每个上,并且填充所述第一半导体芯片和所述多个虚设半导体芯片之间的所有间隙。
16.一种半导体封装,包括:
彼此分开的多个下半导体芯片,所述多个下半导体芯片包括第一下半导体芯片和第二下半导体芯片;
模制构件,填充所述多个下半导体芯片之间的间隙;
粘合膜,提供在所述多个下半导体芯片的有源表面和所述模制构件上;以及
提供在所述粘合膜上的上半导体芯片,
其中所述第一下半导体芯片具有比所述第二下半导体芯片小的厚度。
17.根据权利要求16所述的半导体封装,其中所述第一下半导体芯片的有源表面提供在与所述第二下半导体芯片的有源表面不同的平面上。
18.根据权利要求16所述的半导体封装,其中所述第一下半导体芯片包括有源芯片,以及
其中所述第二下半导体芯片包括虚设芯片。
19.根据权利要求16所述的半导体封装,还包括印刷电路板,
其中所述多个下半导体芯片的非有源表面附接到所述印刷电路板的上表面。
20.根据权利要求19所述的半导体封装,其中所述上半导体芯片包括多个堆叠的非易失性存储器,以及
其中所述多个堆叠的非易失性存储器中的每个经由接合线连接到所述印刷电路板。
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KR10-2021-0077421 | 2021-06-15 | ||
KR1020210077421A KR20220167977A (ko) | 2021-06-15 | 2021-06-15 | 반도체 패키지 |
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CN115483201A true CN115483201A (zh) | 2022-12-16 |
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CN202210644164.2A Pending CN115483201A (zh) | 2021-06-15 | 2022-06-08 | 半导体封装 |
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US (1) | US20220399322A1 (zh) |
KR (1) | KR20220167977A (zh) |
CN (1) | CN115483201A (zh) |
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- 2022-05-02 US US17/734,451 patent/US20220399322A1/en active Pending
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US20220399322A1 (en) | 2022-12-15 |
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