CN115483182A - Packaging structure - Google Patents

Packaging structure Download PDF

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Publication number
CN115483182A
CN115483182A CN202211130421.7A CN202211130421A CN115483182A CN 115483182 A CN115483182 A CN 115483182A CN 202211130421 A CN202211130421 A CN 202211130421A CN 115483182 A CN115483182 A CN 115483182A
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CN
China
Prior art keywords
chip
electrically connected
package structure
thermally conductive
pad
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Pending
Application number
CN202211130421.7A
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Chinese (zh)
Inventor
叶正煜
王程
张娜
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Rongxin Electronic Technology Wuxi Co ltd
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Rongxin Electronic Technology Wuxi Co ltd
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Priority to CN202211130421.7A priority Critical patent/CN115483182A/en
Publication of CN115483182A publication Critical patent/CN115483182A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32258—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

The application relates to a packaging structure, which comprises a heat conduction bonding pad, wherein the heat conduction bonding pad is made of a conductive material; an adhesive layer over the thermally conductive pad, the adhesive layer comprising a thermally conductive and insulating adhesive material; a chip located over the adhesive layer, including a control circuit and a power transistor having a lateral structure, wherein an input or output of the chip is electrically connected with the thermally conductive pad; a plurality of pins, at least a portion of the plurality of pins coupled to the control circuitry and to other terminals of the power transistor; and an encapsulation material surrounding the thermally conductive pad, the adhesive layer, the chip, and the inner lead portions of the plurality of leads; the application also discloses an electronic device comprising the packaging structure.

Description

Packaging structure
Technical Field
The present disclosure relates to the field of chip package design, and particularly to a package structure.
Background
The power distribution chip includes a power transistor at least as a switch, generally used for controlling the on/off of a load, and may be divided into a hot plug chip, a high-side switch chip, a load switch chip, and the like. The power distribution chip is a switching circuit which is commonly applied in production and manufacturing, can save cost, realizes economic and efficient high-current load control, and is widely applied to electronic equipment such as automobile control and industrial lighting.
A conventional power distribution chip includes a control circuit and a power transistor, and the control circuit provides functions of controlling and protecting the power transistor. When the power transistor is turned on, a load current flows through the on-resistance of the power transistor, which generates heat loss in the power transistor. Because the loss of the power distribution chip generates heat greatly, in actual production, a heat conducting bonding pad is usually arranged at the bottom of the chip package and is welded on a heat dissipation bonding pad of an external PCB (printed circuit board), and heat is conducted to the PCB from the power distribution chip, so that the effect of heat dissipation of the power distribution chip is achieved.
With the development of power transistors and related technologies, various structures have appeared in the preparation of power distribution chips, for example, the power transistors in the power distribution chips may adopt laterally structured LDMOS or vertically structured VDMOS or Trench MOS (Trench MOS).
Disclosure of Invention
Aiming at the technical problems in the prior art, the application provides a packaging structure which comprises a heat conduction bonding pad, wherein the heat conduction bonding pad is made of a conductive material; an adhesive layer over the thermally conductive pad, the adhesive layer comprising a thermally conductive and insulating adhesive material; a chip located over the adhesive layer, including a control circuit and a power transistor having a lateral structure, wherein an input or output of the chip is electrically connected with the thermally conductive pad; a plurality of pins, at least a portion of the plurality of pins coupled to the control circuitry and to other terminals of the power transistor; and an encapsulation material surrounding the heat conductive pad, the adhesive layer, the chip, and the inner lead portions of the plurality of leads.
In particular, the chip is a power switch chip.
In particular, the heat conducting pad comprises a base island and a connecting rib which are electrically connected with each other, and the input end or the output end of the chip is electrically connected with the base island or the connecting rib.
In particular, the region of the thermally conductive pad to which the electrical connection is made is at least partially silvered.
In particular, the material of the adhesive layer comprises a material with the insulation strength of more than 5V/um and the thermal conductivity of more than 1W/(m.K).
In particular, one or more steps are included, which are located above and electrically connected to the base island, and the input or output of the chip is electrically connected to the base island through the steps.
In particular, the region of the step where the electrical connection is made is at least partially silvered.
Specifically, the plurality of pins include at least one first pin electrically connected to the heat conducting pad, and the input end or the output end of the chip is electrically connected to the heat conducting pad through the first pin.
Specifically, the first lead only includes an inner lead surrounded by the encapsulating material, and the other leads further include an outer lead exposed from the encapsulating material.
In particular, the thermally conductive pad includes a first portion and a second portion electrically isolated from each other, wherein the chip is located over the first portion; the second portion is electrically connected to an input or output of the chip.
In particular, the first portion of the thermally conductive pad is electrically connected to the output of the chip.
In particular, the heat conducting pad comprises an electrically conductive step above, and the chip is electrically connected with the second part of the heat conducting pad through the step.
In particular, the thermally conductive pad includes a first portion and a second portion electrically isolated from each other, wherein the chip is located over the first portion and the second portion of the thermally conductive pad; the second portion of the thermally conductive pad is electrically connected to the input or output of the chip.
In particular, the first portion of the thermally conductive pad is also electrically connected to an output or input of the chip.
The application further provides an electronic device, which comprises the packaging structure.
By adopting the scheme of the application, the pin number of the power distribution chip can be reduced, the packaging volume is reduced, the packaging cost is reduced, the chip of the power transistor with the transverse structure is compatible with the pin of the chip of the power transistor with the vertical structure, an interface of the chip on a printed circuit board is not required to be additionally designed in the application process, the design and application cost of the circuit board is greatly reduced, and the product competitiveness is improved.
Drawings
Preferred embodiments of the present application will now be described in further detail with reference to the accompanying drawings, in which:
FIG. 1A is a circuit diagram of a power distribution chip;
FIG. 1B is a schematic side cross-sectional view of a power distribution chip fabricated with a lateral structure such as an LDMOS;
FIG. 1C is a schematic side cross-sectional view of a power distribution chip fabricated using a vertical structure such as a VDMOS;
fig. 2A is a schematic front cross-sectional view of a package structure according to an embodiment of the present application;
fig. 2B is a schematic right-side cross-sectional view of a package structure according to an embodiment of the present application;
fig. 2C is a top view of a package structure according to one embodiment of the present application;
fig. 3A is a schematic right side cross-sectional view of a package structure according to another embodiment of the present application;
fig. 3B is a top view of a package structure according to another embodiment of the present application;
fig. 3C is a schematic right side cross-sectional view of a package structure according to another embodiment of the present application;
fig. 3D is a top view of a package structure according to another embodiment of the present application;
fig. 4A is a schematic front cross-sectional view of a package structure according to an embodiment of the present application;
FIG. 4B is a top view of a package structure according to one embodiment of the present application;
fig. 4C is a schematic front cross-sectional view of a package structure according to another embodiment of the present application;
fig. 4D is a top view of a package structure according to another embodiment of the present application; and
fig. 5 is a top view of a package structure according to yet another embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.
In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific embodiments of the application. In the drawings, like numerals describe substantially similar components throughout the different views. Various specific embodiments of the present application are described in sufficient detail below to enable those skilled in the art to practice the teachings of the present application. It is to be understood that other embodiments may be utilized and structural, logical or electrical changes may be made to the embodiments of the present application.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate. For the connection between the units in the drawings, for convenience of description only, it means that at least the units at both ends of the connection are in communication with each other, and is not intended to limit the inability of communication between the units that are not connected. The number of lines between two units is intended to indicate at least the number of signals involved in the communication between the two units or at least the outputs provided, and is not intended to limit the communication between the two units to signals only as shown in the figure.
A transistor may refer to a transistor of any structure, such as a Field Effect Transistor (FET) or a Bipolar Junction Transistor (BJT). When the transistor is a field effect transistor, the transistor can be hydrogenated amorphous silicon, metal oxide, low-temperature polysilicon, an organic transistor, or the like, depending on the channel material. The current carriers are electrons or holes and can be divided into an N-type transistor and a P-type transistor, the control electrode of the current carrier refers to the grid electrode of the field effect transistor, the first electrode can be the drain electrode or the source electrode of the field effect transistor, and the corresponding second electrode can be the source electrode or the drain electrode of the field effect transistor; when the transistor is a bipolar transistor, the control electrode of the transistor refers to a base electrode of the bipolar transistor, the first electrode may be a collector or an emitter of the bipolar transistor, and the corresponding second electrode may be an emitter or a collector of the bipolar transistor. The transistor may be manufactured using amorphous silicon, polysilicon, an oxide semiconductor, an organic semiconductor, an NMOS/PMOS process, or a CMOS process.
The chip described below is a die that does not include a package structure, and a package structure refers to a structure that includes the chip/die and an external packaging material, and the like.
Currently, in practical applications, power distribution chips with different structures need corresponding external circuits with different structures to be matched with the power distribution chips to work because of different structures. To improve the compatibility of different power distribution chips with external circuitry (e.g., external circuitry suitable for use in conventional vertical structure power distribution chip packages), the present application provides a package including a lateral structure power distribution chip that is compatible with conventional vertical structure external circuitry.
Fig. 1A is a circuit diagram of a power distribution chip.
As shown in fig. 1A, the power distribution chip may include at least a control circuit 101 and a power transistor 102. The control circuit 101 includes a plurality of transistors, which may be mainly implemented by CMOS transistors to provide a higher device density, and bipolar transistors and DMOS transistors to reduce the size of the control circuit 101.
DMOS is similar to CMOS device structure, and has active, drain, grid and other electrodes, but the drain terminal breakdown voltage is high. DMOS are mainly of two types, vertical double-diffused MOSFET (vertical double-diffused MOSFET) and lateral double-diffused MOSFET (lateral double-diffused MOSFET).
The power transistor 102 shown in fig. 1A can be manufactured by using LDMOS/VDMOS or trench MOS, because of its high breakdown voltage and high power. According to one embodiment of the present application, the power distribution chip may be a high-side switch chip.
The power distribution chip shown in fig. 1A receives an input signal Vin and an enable signal EN from an external circuit, and generates an output signal Vout to be transmitted to the external circuit. Wherein Vin is the power voltage VDD in the normal operating state. The enable signal EN is used to enable the control circuit 101.
Fig. 1B is a schematic side cross-sectional view of a power distribution chip fabricated with a lateral structure such as an LDMOS. As shown in fig. 1B, the power transistor 102 may be formed on the upper surface of the chip in a lateral configuration such as LDMOS, in conjunction with the control circuit 101. In fig. 1B, the substrate of the power transistor may be a P-type semiconductor prepared by BCD process. As shown in fig. 1B, with the LDMOS in the lateral structure, the gate, the source and the drain are all on the top surface of the chip, and when the circuit flows from the drain to the source, the current is concentrated on the top surface of the chip.
Fig. 1C is a schematic side cross-sectional view of a power distribution chip fabricated using a vertical structure such as a VDMOS. As shown in fig. 1C, the gate and source (in the P-well) of the VDMOS are located on the same plane as the control circuit 101, i.e., on the upper surface of the chip, and the drain is located on the lower surface of the chip and is electrically connected through the N-type semiconductor substrate. As shown in fig. 1C, when current is left from the drain to the source, current is left from the bottom surface of the chip to the top surface of the chip.
As shown in fig. 1B and 1C, a PN junction may be included in the power distribution chip, and in order to avoid that the PN junction is turned on erroneously to affect the normal operation of the circuit, the substrate of the power distribution chip including a lateral structure such as an LDMOS needs to be connected to the system minimum potential, i.e., the ground level. Since the substrate of the power distribution chip including the vertical structure such as the VDMOS is an N-type semiconductor, it is necessary to connect the highest potential of the system, that is, the input signal Vin.
In the packaging process of the power distribution chip, a heat conducting pad is usually disposed on the lower surface of the chip, and the circuit on the upper surface is bonded by a wire. In conventional packaging processes, the thermally conductive pads may be used to supply power to the chip in addition to the function of dissipating heat. Conventional connecting agents incorporate metals in order to meet the requirements, so that the connecting agent can conduct electricity.
For a power distribution chip comprising a lateral structure, such as an LDMOS, the thermally conductive pad may be used to provide a ground level signal GND to the chip substrate. For a power distribution chip comprising a vertical structure such as a VDMOS, the input signal Vin may be provided to the power distribution chip through a thermally conductive pad. This makes the pin arrangement of power distribution chip packages that include vertical structures such as VDMOS and lateral structures such as LDMOS different.
For external circuits or electronic devices that currently fit with power distribution chips that include vertical structures such as VDMOS, current power distribution chips that include lateral structures such as LDMOS are not compatible with external circuits that employ VDMOS power distribution chips due to issues that do not correspond to pin layout.
In addition, the manner of wire bonding has certain limitations, such as a limited number of wires that can be bonded to one lead; the lead diameter is, for example, around 30um, which introduces a considerable resistance value. The pin of the chip also has a resistor, and when current flows through the pin, the current is influenced by the resistor of the pin, so that the heat generation of the chip is increased. Therefore, in the existing package structure of the power distribution chip including the lateral structure such as the LDMOS, both the input terminal Vin and the output terminal Vout are bonded to the leads in the package structure by wire bonding, which is more susceptible to the above-mentioned limitation of wire bonding.
For example, for a power distribution chip with two independent power transistors and control circuits forming two paths, each path requires 3 pins. For chips comprising lateral structures such as LDMOS 3 x 2=12 pins are needed, and for chips comprising vertical structures such as VDMOS 3 x 2=6 pins are needed. The pin number of the chip with the transverse structure far exceeds that of the chip with the vertical structure, so that the packaging volume is large, the packaging cost is high, and the occupied area on a PCB is large.
In order to solve the problems of large packaging volume, high cost and compatibility between the power distribution chip with different structures and an external circuit caused by the pins of the power distribution chip, the application provides a packaging structure, which utilizes the characteristics of relatively large area and relatively small resistance of a heat conduction bonding pad, adjusts the pin layout of the chip with a transverse structure such as LDMOS, reduces the pin number of the chip with the power transistor with the transverse structure, and enables the chip with the transverse structure to be compatible with the external circuit of the chip with the power transistor with the vertical structure.
Fig. 2A is a schematic front cross-sectional view of a package structure according to an embodiment of the present application. As shown in fig. 2A, the package structure may include a heat conducting pad 201 and a chip, where the heat conducting pad 201 provides heat dissipation for the chip and simultaneously electrically connects the chip with an external circuit. The chip is fixed above the heat conductive pad 201 by an adhesive layer 202. According to one embodiment of the present application, the material of the thermally conductive pad 201 includes an electrically conductive material.
According to one embodiment of the present application, the package structure disclosed in the present application may be applied to a chip of a power transistor having a lateral structure, including a power distribution chip. The following description will be given taking an embodiment in which a chip surrounded by a package structure is a power distribution chip as an example. According to other embodiments of the present application, the chip may also be other chips having power transistors in a lateral structure.
According to one embodiment of the present application, a chip may include control circuitry 204-21 and power transistors 204-22. According to an embodiment of the present application, the control circuit 204-21 and the power transistor 204-22 may be fabricated on a common substrate 204-1 during chip fabrication, as shown in FIG. 2A. In some embodiments, the substrate 204-1 may be an integral part of the control circuitry 204-21 and the power transistors 204-22. According to one embodiment of the present application, power transistors 204-22 may include an LDMOS or other lateral structure. According to one embodiment, substrate 204-1 may be connected by conductive vias (not shown) to ground terminals on the top surface of the chip, which are wire bonded to ground pins.
According to an embodiment of the present application, the package structure may further include an adhesive layer 202 located between the heat conducting pad 201 and the chip, and the adhesive layer 202 is in contact with and closely attached to the heat conducting pad 201 and the chip, respectively, to help the chip transfer heat to the heat conducting pad 201, as shown in fig. 2A.
As shown in fig. 2A, the substrate 204-1 of the chip is fixed on the heat conducting pad 201 by an adhesive layer 202, wherein the material of the adhesive layer 202 may be a heat conducting and insulating material. According to an embodiment of the present application, since the power transistor 204-22 employs the lateral structure LDMOS and the substrate is P-type, the substrate 204-1 needs to be grounded, unlike the network of the input signal Vin on the thermal pad 201. The adhesive layer 202 connecting the substrate 204-1 and the heat conducting pad 201 is made of an insulating material to electrically isolate the substrate 204-1 from the heat conducting pad 201.
According to one embodiment of the present application, the material of the adhesive layer 202 may be a good insulation and good thermal conductivity bonding agent, such as LOCTITE ABLESTIK 84-3J-GR of Hankel height (Henkel), insulation strength 31kV/mm, thermal conductivity 3W/(m.K). According to an embodiment of the present application, the adhesive layer 202 using the above-described connecting agent may have a thickness of 20um, and the insulation voltage may be 620V or more.
According to other embodiments of the present application, the material of the adhesive layer 202 may be a material having an insulation strength of at least greater than 5V/um and a thermal conductivity of at least greater than 1W/(m · K). According to an embodiment of the present application, a material insulation voltage of the adhesive layer may be 50V or more.
According to an embodiment of the present application, the package structure may further include a plurality of pins, such as pin 203-1 and pin 203-2, as shown in fig. 2A. The plurality of pins include inner pins, which refer to portions located inside the package structure for electrical connection with the respective terminals, and outer pins, which refer to portions located outside the package structure for electrical connection or soldering with an external circuit.
According to an embodiment of the present application, the output terminal of the power transistor 204-22 may be located in a region B of the region where the power transistor is located, and may be electrically connected to the inner lead of at least a portion of the leads 203-1 by a wire bond 205-1 to transmit the output signal Vout to an external circuit.
According to one embodiment, the input terminal of the power transistor 204-22 may be located in an area a in the power transistor area, electrically connected to the heat conductive pad 201 by means of, for example, a down-bond (down-bond) 205-3, and receive an input signal Vin from an external circuit through the heat conductive pad 201. According to an embodiment of the present application, down bonding as one of the means of wire bonding enables electrically connecting the heat conductive pad 201 and the input terminal in the a region while crossing the insulating adhesive layer 202. According to an embodiment of the present application, the adhesive layer does not cover the entire heat conductive pad 201, so the wire is bonded to the upper surface of the heat conductive pad 201 not covered by the adhesive layer 202.
According to other embodiments of the present application, silver may be plated on at least a portion of the surface of the thermal pad 201 to improve the reliability of the bonding process.
Of course, other layouts for the input and output terminals in the power transistor area may be adopted, and are not limited to the above description. According to an embodiment of the present application, the electrical connection of the input terminal and the output terminal of the power transistor 204-22 can be reversed, the output terminal is electrically connected to the heat conducting pad 201 by means of a down bonding, and the input terminal is electrically connected to the inner lead of the lead 203-1 by means of a wire bonding.
In addition, the electrical connection relationship of the leads 203-1 and 203-2 to the chip bond can be reversed.
As shown in fig. 2A, the package structure may further include an encapsulation material 200, and the encapsulation material 200 covers the heat conducting pad 201 and the chip. According to one embodiment, the encapsulant 200 may have a shape such as a rectangular parallelepiped, although other shapes may be used as desired. According to the embodiment of the present application, the material of the packaging material 200 may be plastic, or other materials meeting the production requirements.
Fig. 2B is a schematic right-side cross-sectional view of a package structure according to an embodiment of the present application. As shown in fig. 2B, the thermal pad may include a base island 201-3, and a plurality of ribs 201-1 and 201-2 electrically connected to the base island. The input terminals of the chip in region a (not shown) of power transistor 204-22 are electrically connected to thermally conductive pad 201-3 by wire bonding. According to other embodiments of the present application, the thermal pad may include only the base island 201-3, and no connecting rib electrically connected to the base island.
Fig. 2C is a top view of a package structure according to one embodiment of the present application. As shown in fig. 2C, the plurality of pins may include, for example, pins 203-1 and 203-2 located on both sides of plastic encapsulant 200. Of course, the pins may be arranged in other ways as desired.
According to one embodiment, the control terminal of the control circuit 204-21 receiving the control signal EN can be electrically connected to the inner pin of at least a portion of the pins 203-2 via the wire bond 205-2, and receive the control signal EN from an external circuit.
According to an embodiment of the present application, a ground terminal in the chip may be coupled to an inner lead of a ground lead (not shown) that is part of 203-2 by wire bonding.
Fig. 3A is a schematic right-side cross-sectional view of a package structure according to another embodiment of the application. According to an embodiment of the present application, the package structure may further include steps 311-1 and 311-2 over the heat conductive pad 301 and electrically connected to the heat conductive pad 301, independently of the chip, as shown in fig. 3A. The steps 311-1 and 311-2 are provided to improve the electrical connection effect of the heat conductive pad 301 with the input terminal in the a region (not shown). According to an embodiment of the present application, the input terminal of the power transistor in the chip may be electrically connected to the steps 311-1 and 311-2 on the heat conducting pad 301 through a wire bonding process. According to an embodiment of the application, the step 311 can enable an arc line generated by a bonding process to be better, reduce stress at a contact position, avoid layering at the contact position, and improve reliability.
According to one embodiment of the present application, the heights of the steps 311-1 and 311-2 may be the same as the heights of the plurality of inner leads.
According to an embodiment of the present application, the steps 311-1 and 311-2 may also be silver plated on at least a portion of the surface contacting the input terminal of the chip to improve the reliability of the bonding process on the step 311.
Fig. 3B is a top view of a package structure according to another embodiment of the present application. As shown in fig. 3B, since the chip needs to pass a large current, the step may have a plurality of steps 311-1 and 311-2, which are located above the heat conducting pad 301 and are used for making electrical connection with the input terminal in the chip a region, so as to reduce chip loss.
Fig. 3C is a right side cross-sectional schematic view of a package structure according to another embodiment of the present application. Fig. 3D is a top view of a package structure according to another embodiment of the present application.
According to another embodiment of the present application, the input terminals in the chip a region may be electrically connected to the ribs 301-1 and 301-2 of the thermal pad 301 by wire bonding, as shown in fig. 3C and 3D. The other end than the input end is electrically connected to the inner lead of at least part of the leads 303-1 and 303-2 by wire bonding.
Fig. 4A is a schematic front cross-sectional view of a package structure according to an embodiment of the present application. Fig. 4B is a top view of a package structure according to one embodiment of the present application. As shown in fig. 4B, region a of the chip is electrically connected to one of the leads 403-1 or at least some of the inner leads of the leads by wire bonding. The inner lead of the lead electrically connected to the a-region is simultaneously electrically connected to the base island 401-3 of the heat conductive pad, as shown in fig. 4A.
According to an embodiment of the present application, the inner pin of the pin electrically connected to the a-region must be electrically connected to the heat conductive pad, and the outer pin thereof is not electrically connected to an external circuit receiving other signals.
According to other embodiments of the present application, the pin electrically connected to the a region may also be one of the pins 403-2 or at least a part of the pins, which is determined according to actual production requirements.
Fig. 4C is a schematic front cross-sectional view of a package structure according to another embodiment of the present application. Fig. 4D is a top view of a package structure according to another embodiment of the present application.
As shown in fig. 4D, the a region of the chip is electrically connected to one of the leads 403-1 or at least a portion of the inner leads of the leads by wire bonding. The inner lead of the lead electrically connected to the a-region is simultaneously electrically connected to the base island 401-3 of the heat conductive pad, as shown in fig. 4C. According to the embodiment of the present application, the leads electrically connected to the a-region are flush with the edge of the packaging material 400 of the package structure, and do not include external leads electrically connected to external circuits exposed outside the packaging material 400, as shown in fig. 4C.
According to the embodiment of the present application, the pin electrically connected to the a region may also be one of the pins 403-2 or at least a part of the pins, which is determined according to actual production requirements.
Fig. 5 is a top view of a package structure according to yet another embodiment of the present application. As shown in fig. 5, the thermally conductive pad may include a first portion 501-1 and a second portion 501-2, the first portion 501-1 and the second portion 501-2 being electrically isolated from each other.
According to one embodiment of the present application, wherein only the first portion 501-1 is in contact with an adhesive layer (not shown) for dissipating heat from the chip. Only the second portion 501-2 is electrically connected to the input terminal in the area of chip a, forming an electrical network for receiving the input signal Vin to external circuitry.
As shown in fig. 5, the input terminal in the chip a region may be electrically connected to the second portion 501-2 by wire bonding, or may be electrically connected by other processes. According to an embodiment of the present application, a portion of the second portion 501-2 of the heat conductive pad contacting the input end of the a-region may be specially processed, for example, a step is formed at a portion of the second portion 501-2 of the heat conductive pad contacting the input end of the a-region and silver is plated on at least a portion of the surface of the contact, so as to reduce the complexity of the process.
According to an embodiment of the present application, the area of the first portion 501-1 of the heat conducting pad may be the same as the projected area of the chip in the vertical direction, or may be larger or smaller than the area of the chip, which is determined according to actual production requirements.
According to other embodiments of the present application, the first portion 501-1 of the thermal pad may also be electrically connected to the chip. According to embodiments of the present application, the electrical signal transmitted by the first portion 501-1 of the thermal pad may be the same as or different from the electrical signal transmitted by the second portion 501-2. For example, the electrical signals transmitted by the first portion 501-1 and the second portion 501-2 of the thermal pad may be input signals Vin, or the first portion may transmit output signals Vout and the second portion may transmit input signals Vin.
The electrical signals transmitted by the first portion 501-1 and the second portion 501-2 may be interchanged or other electrical signals according to other embodiments of the present application.
According to another embodiment of the present application, an adhesive layer (not shown) may be positioned over the first and second portions 501-1 and 501-2 of the thermal pad, in contact with the first and second portions 501-1 and 501-2, respectively. According to one embodiment, only the second portion 501-2 may be electrically connected to the input of the chip, or the first portion 501-1 may be electrically connected to the output and the second portion 501-2 may be electrically connected to the input. According to embodiments of the application, the output or input terminals electrically connected to the first portion 501-1 and the second portion 501-2 may be reversed, with the first portion 501-1 carrying Vin and the second portion 501-2 carrying Vout.
The present application further provides an electronic device comprising a package structure as described above with respect to the above embodiments.
By adopting the scheme of the application, the pin number of the power distribution chip can be reduced, the packaging volume is reduced, the packaging cost is reduced, the chip of the power transistor with the transverse structure is compatible with the pin of the chip of the power transistor with the vertical structure, an interface of the chip on the printed circuit board is not required to be additionally designed in the application process, the design and application cost of the circuit board is greatly reduced, and the product competitiveness is improved.
The above-described embodiments are provided for illustrative purposes only and are not intended to be limiting, and various changes and modifications may be made by those skilled in the art without departing from the scope of the present disclosure, and therefore, all equivalent technical solutions should fall within the scope of the present disclosure.

Claims (15)

1. A package structure, comprising:
the heat conduction bonding pad is made of a conductive material;
an adhesive layer over the thermally conductive pad, the adhesive layer comprising a thermally conductive and insulating adhesive material;
a chip located over the adhesive layer, including a control circuit and a power transistor having a lateral structure, wherein an input or output of the chip is electrically connected with the thermally conductive pad;
a plurality of pins, at least portions of the plurality of pins coupled to the control circuitry and to other terminals of the power transistor; and
and an encapsulation material surrounding the heat conductive pad, the adhesive layer, the chip, and the inner lead portions of the plurality of leads.
2. The package structure of claim 1, wherein
The chip is a power distribution chip.
3. The package structure of claim 1, wherein
The heat conduction bonding pad comprises a base island and a connecting rib which are electrically connected with each other, and the input end or the output end of the chip is electrically connected with the base island or the connecting rib.
4. The package structure of claim 1, wherein
The area where the heat conducting pad is electrically connected is at least partially silvered.
5. The package structure of claim 1, wherein
The material of the adhesive layer comprises a material with the insulation strength of more than 5V/um and the thermal conductivity of more than 1W/(m.K).
6. The package structure of claim 3, further comprising
And one or more steps positioned above and electrically connected with the base island, wherein the input end or the output end of the chip is electrically connected with the base island through the steps.
7. The package structure of claim 6, wherein
The region where the step is electrically connected is at least partially plated with silver.
8. The package structure of claim 1, wherein
The plurality of pins comprise at least one first pin electrically connected with the heat conduction bonding pad, and the input end or the output end of the chip is electrically connected with the heat conduction bonding pad through the first pin.
9. The package structure of claim 8, wherein
The first pins only comprise inner pins surrounded by the packaging material, and the other pins also comprise outer pins exposed out of the packaging material.
10. The package structure of claim 1, wherein
The thermally conductive pad includes a first portion and a second portion electrically isolated from each other, wherein the chip is located over the first portion;
the second portion is electrically connected to an input or output of the chip.
11. The package structure of claim 10, wherein
The first portion of the heat conducting pad is electrically connected with the output end or the input end of the chip.
12. The package structure of claim 10, wherein
The second part of the heat conduction bonding pad comprises an electric conduction step, and the chip is electrically connected with the second part of the heat conduction bonding pad through the step.
13. The package structure of claim 1, wherein
The thermally conductive pad includes a first portion and a second portion electrically isolated from each other, wherein the chip is located over the first portion and the second portion of the thermally conductive pad;
the second portion of the thermally conductive pad is electrically connected to the input or output of the chip.
14. The package structure of claim 13, wherein
The first portion of the thermally conductive pad is also electrically connected to an output or input of the chip.
15. An electronic device comprising the encapsulation structure according to claims 1-14.
CN202211130421.7A 2022-09-16 2022-09-16 Packaging structure Pending CN115483182A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211130421.7A CN115483182A (en) 2022-09-16 2022-09-16 Packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211130421.7A CN115483182A (en) 2022-09-16 2022-09-16 Packaging structure

Publications (1)

Publication Number Publication Date
CN115483182A true CN115483182A (en) 2022-12-16

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211130421.7A Pending CN115483182A (en) 2022-09-16 2022-09-16 Packaging structure

Country Status (1)

Country Link
CN (1) CN115483182A (en)

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