CN115482795A

CN115482795A - Data driver and control method

Info

Publication number: CN115482795A
Application number: CN202211078894.7A
Authority: CN
Inventors: 柯健专; 蔡孟杰
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2022-03-31
Filing date: 2022-09-05
Publication date: 2022-12-16
Also published as: TWI816348B; TW202340945A

Abstract

The present disclosure provides a data driver. The data driver includes a shift register, a logic circuit, and a data latch. The shift register is used for outputting a first output signal. The logic circuit is used for outputting a second output signal according to the first output signal and the reset control signal output by the shift register. The switch of the data latch is used for transmitting the data signal to the internal node according to the second output signal. During the data setting period, when the logic circuit outputs the second output signal with the first logic level according to the first output signal with the enable level, the switch is conducted. During the reset period, the logic circuit outputs a second output signal with a first logic level according to a reset control signal with an enable level, so that the switch is turned on to transmit the data signal to the internal node.

Description

Data driver and control method

Technical Field

The present disclosure relates to a data driver, and more particularly, to a data driver and a control method thereof.

Background

In the current display technology, if the display fails to perform the reset operation during the power-on/power-off reset operation, the gray scale of the display image is not uniform. Therefore, how to improve the reset operation of the data driver is an important issue in the art.

Disclosure of Invention

The present disclosure provides a data driver. The data driver includes a shift register, a first logic circuit, and a data latch. The shift register is used for outputting a first output signal. The first logic circuit is used for outputting a second output signal according to a first output signal and a reset control signal output by the shift register, wherein when one of the first output signal and the reset control signal has an enable level, the first logic circuit outputs the second output signal with a first logic level. The data latch includes a switch. The switch is used for transmitting the data signal to the internal node according to the second output signal. During the data setting period, when the first logic circuit outputs the second output signal with the first logic level according to the first output signal with the enable level, the switch is conducted. During the reset period, the first logic circuit outputs a second output signal with a first logic level according to a reset control signal with an enable level, so that the switch is turned on to transmit the data signal to the internal node.

The present disclosure provides a control method. The control method comprises the following steps. The shift register outputs a first output signal. And outputting a second output signal by the first logic circuit according to the first output signal and the reset control signal output by the shift register, wherein when one of the first output signal and the reset control signal has an enable level, the first logic circuit outputs the second output signal with a first logic level. In the reset period, the first logic circuit outputs a second output signal with a first logic level according to a reset control signal with an enable level. During the reset period, a circuit path between the internal node of the data latch and the output end of the register is conducted according to a second output signal with a first logic level, so that the output of the register is transmitted to the internal node of the data latch.

In summary, the present disclosure utilizes the logic circuit to generate the second output signal according to the reset control signal and the first output signal, and during the reset period, the circuit path between the internal node of the data latch and the output terminal of the register is conducted according to the second output signal, so as to transmit the data signal after the register is reset to the internal node of the data latch.

Drawings

The foregoing and other objects, features, advantages and embodiments of the disclosure will be more readily understood from the following description taken in conjunction with the accompanying drawings in which:

fig. 1 is a schematic diagram of a display device according to an embodiment of the disclosure.

FIG. 2 is a schematic diagram of a data latch according to an embodiment of the present disclosure.

FIG. 3 is a diagram of a register for generating data signals according to an embodiment of the disclosure.

Fig. 4 is a schematic diagram of a logic circuit according to an embodiment of the disclosure.

Fig. 5 is a schematic diagram of a timing sequence of a control signal according to an embodiment of the disclosure.

FIG. 6 is a schematic diagram of a data latch according to an embodiment of the present disclosure.

Detailed Description

The following detailed description of the embodiments with reference to the accompanying drawings is provided to better understand the aspects of the present disclosure, but the embodiments are not intended to limit the scope of the disclosure, the structural operations are not intended to limit the execution sequence thereof, and any structure resulting from the rearrangement of elements and having equivalent functions is intended to cover the scope of the present disclosure. Moreover, the drawings are for illustrative purposes only and are not drawn to scale in accordance with standard and customary practice in the art, and the dimensions of the various features may be arbitrarily increased or reduced for clarity of illustration. In the following description, the same elements will be described with the same reference numerals for easy understanding.

The numbers of elements and signals used in the specification and drawings are numbered with the indices 1 to n, which are used for convenience to refer to individual elements and signals, and are not intended to limit the number of the elements and signals to a specific number. In the specification and drawings, if an element number or a signal number is used without indicating an index of the element number or the signal number, the element number or the signal number is referred to as any unspecified element or signal in an element group or a signal group.

Furthermore, as used herein, the terms "comprising," including, "" having, "" containing, "and the like are open-ended terms that mean" including, but not limited to. Further, as used herein, "and/or" includes any and all combinations of one or more of the associated listed items.

When an element is referred to as being "connected" or "coupled," it can be referred to as being "electrically connected" or "electrically coupled. "connected" or "coupled" may also be used to indicate that two or more elements are in mutual engagement or interaction. Moreover, although terms such as "first," "second," "8230," etc. may be used herein to describe various elements, such terms are only used to distinguish one element or operation from another element or operation described in similar technical terms.

Referring to fig. 1, fig. 1 is a schematic view of a display device 100 according to an embodiment of the disclosure. As shown in fig. 1, the display device 100 includes a gate driver 110, a data driver 120, and a pixel array 130.

In some embodiments, the gate driver 110 includes decoders GDEC [1] GDEC [ z ]. The decoders GDEC [1] to GDEC [ z ] are each electrically coupled to the pixels PIX of the same pixel row (pixel line) of the pixel array 130 for controlling whether the data setting path of the pixels PIX of the pixel row is turned on, so that the corresponding pixel data is transmitted to the corresponding pixels PIX of the pixel row through the aforementioned path. In some embodiments, the pixels PIX may be implemented by a Pixel In Pixel Memory (Memory In Pixel), and the gate driver 110 may conduct paths to the corresponding data lines DY [1] to DT [ y ] of all the pixels to reset all the pixels PIX during power on/off of the display apparatus 100. In this case, if the potential reset of the data line fails, the embedded pixel memory retains the original potential, so that the gray scale of the display screen is not uniform.

Therefore, in order to improve the uniformity of the display when the display performs the reset operation during the power on/off period, the present disclosure resets the potentials of the data lines DY [1] -DY [ y ] by the data driver 120, so that each pixel in the pixel array 130 can complete the reset operation via the data lines DY [1] -DY [ y ], thereby improving the gray uniformity of the display during the reset period. How to control the data driver 120 to perform the reset operation will be described in detail in the following embodiments.

The data driver 120 includes a shift register circuit 122, a data latch circuit 124, and logic circuits 126[1] - [ 126 ] - [ x ]. Shift register circuit 122 includes shift registers HSR [1] to HSR [ x ], where "x" can be any positive integer. In some embodiments, the "x" may be implemented by 26. However, in other embodiments, "x" may be implemented by 48, 52, or other positive integers. Therefore, the present disclosure is not limited thereto.

Shift register HSR [1]]～HSR[x]Are electrically coupled to the logic circuit 126[ 2 ], [1]]～126[x]And generates and transmits a first output signal OUT [1]]～OUT[x]To the logic circuit 126[ 2 ], [1]]～126[x]So that the logic circuit 126[1], []～126[x]According to a first output signal OUT [1]]～OUT[x]Generates a second output signal HSR _ out [1]]～HSR_out[x]And a third output signal

The logic circuit 126[1 ]. About 126[ x ] is electrically coupled to the data latch circuit 124 to transfer the second output signal HSR _ out [1] to HSR _ out [ x ] to the data latch circuit 124. The data latch circuit 124 includes a data latch 128[ 2 ], [1] to [ 128 ], [ y ].

The data latches 128[1] - [ 128 ] are respectively connected to the data lines DY [1] - [ DY [ y-1] to supply pixel data to the corresponding pixels PIX in the pixel row via the data lines DY [1] - [ DY [ y-1] respectively in accordance with the pixel row scanned by the gate driver 110, wherein "y" may be any positive integer. In some embodiments, the "y" may be implemented by 208, however, in other embodiments, "y" may be implemented by 312, 416, or other positive integers. Therefore, the present disclosure is not limited thereto.

Note that the number of data latches in a set (e.g., data latch 128[1 ])]～128[a]Wherein the data latch 128[ a ]]Not shown in the drawing) times the number of shift registers is equivalent to the total number of data latches. In other words, the aforementioned number "a" of data latches in a group is multiplied by the number of shift registersThe total number "x" is equal to the total number "y" of data latches. For example, the data latch 128 of the same set of data 1]～128[a]Are all used to receive the second output signal HSR _ out [1]]And a third output signal

To simultaneously supply pixel voltage to data line DY [1]]～DY[a]. In some embodiments, "a" may be implemented by 8. However, in other embodiments, "a" may be implemented by 4, 16, or 24 or other positive integers. Therefore, the present disclosure is not limited thereto.

Similarly, the data latch 128[ alpha ] +1 of the other set]～128[2a]Are all used to receive the second output signal HSR _ out [2 ]]And a third output signal

To simultaneously supply the pixel voltage to the data line DY [ a + 1]]～DY[2a]。

Referring to FIG. 2, FIG. 2 is a schematic diagram of a data latch 228[ n ] according to an embodiment of the present disclosure. The data latch 128[1] to 128[ y ] shown in FIG. 1 can each be implemented by the data latch 228[ n ] shown in FIG. 2, where n can be any positive integer. Accordingly, the data line [ n ] connected by the data latch 228[ n ] corresponds to one of the data lines DY [1] to DY [ y ] shown in FIG. 1.

As shown in FIG. 2, data latch 228[ n ] comprises a switch 230 and a feedback circuit 240. The switch 230 in this disclosure is implemented as a transmission gate. In other embodiments, one skilled in the art can replace the transmission gate in the present disclosure with a P-type mosfet switch or an N-type mosfet switch and adjust the control signal accordingly, and can achieve the same functions as the embodiments of the present disclosure.

Specifically, the switch 230 includes a transistor 232 and a transistor 234. The first terminals of the

transistors

232 and 234 are used for receiving the data signal SI _ D [ p ]]And gate terminals of the

transistors

232 and 234 are respectively for receiving the third output signal

And a second output signal HSR _ out [ m [ ]]. Third output signal

Is the second output signal HSR _ out [ m ]]The reverse signal of (2).

The transistor 232 is implemented as a P-type transistor, the transistor 234 is implemented as an N-type transistor, and the transistor 232 and the transistor 234 are based on the third output signal

And a second output signal HSR _ out [ m [ ]]Are simultaneously turned on or off.

Thus, when the second output signal HSR _ out [ m ] has a high logic level, the switch 230 is turned on to transmit the data signal SI _ D [ p ] to the internal node N1 via the

transistors

232 and 234.

In the embodiment of fig. 2, the feedback circuit 240 is implemented by a Clocked-CMOS Logic Gate (Clocked-CMOS Logic Gate). Feedback circuit 240 includes transistors 242,244,246, and 248.

In architecture, the transistors 242,244,246, and 248 are electrically connected in series between the system high voltage terminal VDD and ground. Specifically, the

transistors

242 and 244 are electrically connected in series between the system high voltage terminal VDD and the internal node N1. The first terminal of the transistor 242 is electrically coupled to the system high voltage terminal VDD, the second terminal of the transistor 242 is electrically coupled to the first terminal of the transistor 244, and the gate terminal of the transistor 242 is configured to receive the second output signal HSR _ out [ m ]. Also, the

transistors

242 and 244 may be implemented by P-type transistors.

The

transistors

246 and 248 are electrically connected in series between ground and the internal node N1. A second terminal of the transistor 248 is grounded, a first terminal of the transistor 248 is electrically coupled to the second terminal of the transistor 246, and a gate terminal of the transistor 248 is configured to receive the third output signal

Also, the

transistors

246 and 248 may be implemented by N-type transistors.

Since the transistor 242 can be implemented by a P-type transistor and the transistor 248 can be implemented by an N-type transistor, the second output signal HSR _ out [ m ] is output]When the logic level is low, the transistor 242 turns on the circuit path from the system high voltage terminal VDD to the first terminal of the transistor 244, and the second output signal HSR _ out [ m ] is asserted]Third output signal in reverse direction

With a high logic level, the transistor 248 turns on the circuit path from ground to the second terminal of the transistor 246.

The second terminal of the transistor 244 and the first terminal of the transistor 246 are electrically coupled to the internal node N1, and the gate terminals of the

transistors

244 and 246 are electrically coupled to the node N2. If the second output signal HSR _ out [ m ] has a low logic level, the switch 230 is turned off and the

transistors

242 and 248 are turned on. At this time, the level of the node N2 turns on one of the

transistors

244 and 246 and turns off the other of the

transistors

244 and 246, thereby transmitting the potential of the system high voltage VDD to the internal node N1 through the

transistors

242 and 244 or transmitting the potential of the ground terminal to the internal node N1 through the

transistors

246 and 248 according to the level of the node N2.

Thus, the feedback circuit 240 latches the potential of the internal node N1 when the second output signal HSR _ out [ m ] has a low logic level.

Referring to FIG. 3, FIG. 3 shows an embodiment of the present disclosure for generating a data signal SI _ D [ p ]]Register RES [ p ]]Schematic representation of (a). Register RES [ p ]]Includes pins "D", "C" and "R" for receiving Input data, clock signal CLK and reset signal in reverse direction to enable signal SCS

To generate the data signal SI _ D [ p ] according to the above-mentioned signals]. In some embodiments, the inverter INV is electrically coupled to the register RES [ p ]]Pin "R" for converting the enable signal SCS into the reset signal

And inputs a reset signal

To register RES [ p ]]Pin "R".

Referring to FIG. 4, FIG. 4 is a schematic diagram of a logic circuit 426[ 2 ], [ m ], an embodiment of the present disclosure. As shown in FIG. 4, the logic circuit 426[ m ] includes

logic circuits

428 and 434. Each of the logic circuits 126[1 ]. About 126[ x ] shown in FIG. 1 can be implemented by the logic circuit 426[ m ] shown in FIG. 4, wherein "m" can be any positive integer.

Functionally, both

logic circuits

428 and 434 receive and respond to the first output signal OUT [ m ]]And a reset control signal ALLCLEAR outputting second output signals HSR _ out [ m ] respectively]And a third output signal

Wherein the first output signal OUT [ m ]]Corresponding to the first output signal OUT [1] in FIG. 1]～OUT[x]One of them.

Specifically, the logic circuit 428 includes a nor gate 430 and an inverter 432. The NOR gate 430 is used for receiving the first output signal OUT [ m ] and a reset control signal ALLCLEAR. If at least one of the first output signal OUT m and the reset control signal all is at an enable level (e.g., a high logic level), the output of the nor gate 430 is at a low logic level, and the inverter INV electrically coupled to the output of the nor gate 430 generates the second output signal HSR _ OUT m having a high logic level. On the other hand, if at least one of the first output signal OUT [ m ] and the reset control signal all clear has a low logic level, the output of the nor gate 430 is at a high logic level, and the inverter INV generates the second output signal HSR _ OUT [ m ] having a low logic level.

The logic circuit 434 includes a nor gate 436. The NOR gate 436 is used for receiving the first output signal OUT [ m ]]And resetting the control signal ALLCLEAR if the first output signal OUT [ m ]]And at least one of the reset control signals ALLCLEAR has a high logic level, the NOR gate 436 will generate a third output having a low logic levelOutput signal

On the other hand, if the first output signal OUT [ m ]]With a low logic level, the NOR gate 436 generates a third output signal with a high logic level

Please refer to fig. 1 to 5. Fig. 5 is a schematic diagram of a timing sequence of a control signal according to an embodiment of the disclosure. As shown in fig. 5, an operation cycle of the display device 100 from power-on to power-off is divided into four periods, which are an initialization period T1, a sustain period T2, a data setting period T3, a reserved period T4, and a reset period T5. It should be noted that the time lengths of the periods in fig. 5 are only for illustration and are not intended to limit the disclosure.

During the initialization period T1, the enable signal SCS has a second logic level (e.g., a low logic level) to enable the signal

Has a first logic level (e.g., a high logic level) to register RES [ p ]]A reset operation is performed.

During the asserted period T2, the enable signal SCS has a high logic level to enable the signal

Has a low logic level, thereby stopping the register RES [ p ]]A reset operation is performed.

During the data setting period T3, the register RES [ p ] generates and outputs the data signal SI _ D [ p ] to the data latch 128[ n ] according to the Input data Input and the clock signal CLK. At this time, if third output signal HRS _ out [ m ] has a high logic level, switch 230 of data latch 128[ N ] will be turned on and data signal SI _ D [ p ] will be transferred to internal node N1 of data latch 128[ N ]. On the other hand, if the third output signal HRS _ out [ m ] has a low logic level, switch 230 of data latch 128[ N ] will be closed, and feedback circuit 240 of data latch 128[ N ] will be actuated accordingly, thereby latching the potential of internal node N1.

For example, in the data signal SI _ D [ p ]]During the period with data voltage D (1), when the shift register HSR [1]]The generated first output signal OUT [ m ]]Having a high logic level, the logic circuit 426[ m ]]According to a first output signal OUT [ m ]]The generated second output signal HSR _ out [ m ]]Will have a high logic level. Accordingly, with the second output signal HSR _ out [ m ]]Third output signal in reverse direction

Having a low logic level.

At this time, the second output signal HSR _ out [ m ] having a high logic level]And a third output signal having a low logic level

Will respectively conduct the data latch 128[ n ]]

Transistors

232 and 234 in switch 230 to couple data signal SI _ D p]The data voltage D (1) of (2) is transmitted to the data latch 128[ n ]]And converts the data voltage D (1) to be transmitted to the data line DY [ N ] via the inverting amplifiers 252,254,256, and 258 electrically connected in series with the internal node N1]The data voltage DV (1).

In the data latch 128[ n ]]After the potential of the internal node N1 of (2) is set to the data voltage D (1), the shift register HSR [ m ] is set]The generated first output signal OUT [ m ]]Will be pulled down to the low logic level, the logic circuit 426[ 2 ], [ m ]]Correspondingly generates a second output signal HSR _ out [ m ] with a low logic level]And a third output signal having a high logic level

So that the data latch 128[ n ]]According to the second output signal HSR _ out [ m ]]And a third output signal

The data voltage D (1) is latched. The operation of the feedback circuit 240 has been described in the previous embodiments, and therefore, the detailed description thereof is omitted。

As another example, during the data setup period T3, if the data signal SI _ D [ p ]]Has a data voltage D (q) and is applied to a shift register HSR [1]]The generated first output signal OUT [ m ]]When having a high logic level, the logic circuit 426[ m ]]According to a first output signal OUT [ m ]]The second output signal HSR _ out [ m ] is generated]With a high logic level. Accordingly, with the second output signal HSR _ out [ m ]]Third output signal in reverse direction

Having a low logic level.

Will respectively conduct the data latch 128[ n ]]

Transistors

232 and 234 in switch 230 to couple data signal SI _ D p]Is transmitted to data latch 128[ n ], [ data voltage D (q) ]]And converts the data voltage D (q) to be transmitted to the data line DY [ N ] via the inverting amplifiers 252,254,256, and 258 electrically connected in series with the internal node N1]The data voltage DV (q).

In data latch 128[ n ]]After the potential of the internal node N1 of (2) is set to the data voltage D (q), the shift register HSR [ m ] is set]The generated first output signal OUT [ m ]]Will be pulled down to the low logic level, the logic circuit 426[ 2 ], [ m ]]Correspondingly generates a second output signal HSR _ out [ m ] with a low logic level]And a third output signal having a high logic level

The data voltage D (q) is latched. The operation of the feedback circuit 240 is described in the previous embodiments, and therefore, the description thereof is omitted.

During the reserved period T4, due to the first outputSignal OUT [ m ]]And the reset control signal ALLCLEAR both have a low logic level, the logic circuit 426[ m ]]Generating a second output signal HSR _ out [ m ] having a low logic level]The latch operation is maintained, and the data line DY [ n ] is enabled]Still with the data voltage DV (q). On the other hand, during the reserved period T4, since the enable signal SCS has a low logic level, the register RES [ p ]]Will be based on the reset signal in the reverse direction of the enable signal SCS

Reset to output data signal SI _ D [ p ] with low logic level]。

During the reset period T5, the data signal SI _ D [ p ] has a low logic level because the enable signal SCS is still maintained at a low logic level. Also, since the reset control signal ALLCLEAR has a high logic level, the logic circuit 426[ m ] generates the second output signal HSR _ out [ m ] having a high logic level to turn on the switch 230 in the data latch 228[ N ] to transmit the data signal SI _ D [ p ] having a low logic level to the internal node N1, thereby resetting the potentials of the internal node N1 and the data line DY [ N ].

In other words, during the reset period T5, the switch 230 is turned on according to the second output signal HSR _ out [ m ] having a high logic level to turn on the circuit path between the internal node N1 of the data latch 228[ N ] and the output terminal of the register RES [ p ], and transmits the data signal SI _ D [ p ] having a low logic level after the register RES [ p ] is reset to the internal node N1 of the data latch 228[ N ], thereby resetting the potential of the data line DY [ N ] to a low logic level.

At this time, due to the third output signal

With a low logic level, the transistor 248 in the feedback circuit 240 is turned off, thereby turning off the circuit path from the ground to the second terminal of the transistor 246. Thus, at the beginning of the reset period T5, no matter whether the transistor 246 is turned on or not, the potential of the ground terminal is not transmitted to the internal node N1 through the transistor 248.

Also, since the second output signal HSR _ out [ m ] has a high logic level, the transistor 242 in the feedback circuit 240 is turned off, thereby turning off the circuit path from the system high voltage terminal VDD to the first terminal of the transistor 244. Thus, at the beginning of the reset period T5, no matter whether the transistor 244 is turned on or not, the potential of the system high voltage terminal VDD is not transmitted to the internal node N1 through the transistor 242, which results in a failure of the reset operation.

In some embodiments, the gate driver 110 turns on all the pixels PIX to the corresponding data lines DY [1] -DY [ n ] during the reset period T5, and the data lines DY [1] -DY [ n ] transmit the low logic level voltage as the data voltage to all the pixels PIX at the same time, so that all the pixels PIX of the display apparatus 100 are reset during the reset period T5, thereby improving the uniformity of the image of the display apparatus 100.

Referring to FIG. 6, FIG. 6 is a schematic diagram of a data latch 628[ n ] according to an embodiment of the present disclosure. As shown in FIG. 6, data latch 628[ n ] comprises a switch 630 and a feedback circuit 640. The data latch 128[1] to 128[ y ] shown in FIG. 1 can each be implemented by the data latch 628[ n ] shown in FIG. 6, where n can be any positive integer.

The switch 630 includes a transistor 232 and a transistor 234. The connection and operation of the switch 630 shown in fig. 6 are similar to the switch 230 shown in fig. 2, and therefore are not repeated herein.

In the embodiment of fig. 6, the feedback circuit 640 is implemented by a Transmission gate (Transmission gate). Specifically, the feedback circuit 640 includes a transistor 642 and a transistor 644. Transistor 642 is implemented as a P-type transistor and transistor 644 is implemented as an N-type transistor. Structurally, the

transistors

642 and 644 are connected in parallel between the internal nodes N1 and N2.

Functionally, the gate terminal of the transistor 642 is configured to receive the second output signal HSR _ out [ m [ ]]The gate terminal of the transistor 644 is for receiving the third output signal in the inverse direction

So that the

transistors

642 and 644 can output the second output signal HSR _ out [ m [ ]]Are simultaneously turned on or off.

Specifically, if the second output signal HSR _ out [ m ] has a high logic level, the switch 630 is turned on and the feedback circuit 640 is turned off. On the other hand, if the second output signal HSR _ out [ m ] has a low logic level, the switch 630 is turned off, and the feedback circuit 640 is turned on to latch the potential of the internal node N1 and transmit the potential of the internal node N1 to the data line DY [ N ] through the inverting amplifiers 622 and 624.

The remaining operation and function of the data latch 628[ n ] are substantially similar to those of the data latch 228[ n ], and thus will not be described in detail herein.

In summary, the present disclosure uses the logic circuit 426[ m ] to generate the second output signal HSR _ OUT [ m ] according to the reset control signal ALL and the first output signal OUT [ m ], and during the reset period T5, to turn on the circuit path between the internal node N1 of the data latch 228[ N ] and the output terminal of the register RES [ p ] according to the second output signal HSR _ OUT [ m ], so as to transmit the reset data signal SI _ D [ p ] of the register RES [ p ] to the internal node N1 of the data latch 228[ N ], thereby resetting the data latch 228[ N ]. Thus, the potential of the data line DY [ n ] is reset.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Description of the symbols

In order to make the above and other objects, features, advantages and embodiments of the present disclosure more comprehensible, the following symbols are provided:

100: display device

110: gate driver

120: data driver

122: shift register circuit

124: data latch circuit

126[ 2 ], [1] to 126[ x ],426[ m ]: logic circuit

128 2 [1] to 128[ y ],228[ n ],628[ n ]: data latch

130: pixel array

230,630: switch with a switch body

232,234,242,244,246,248,632,634,642,644 transistors

240,640: feedback circuit

252,254,256,258,652,654: inverting amplifier

430,436: NOR gate

432: reverser

N1: internal node

N2: node point

OUT [1] to OUT [ x ], OUT [ m ]: first output signal

HSR _ out [1] to HSR _ out [ x ], HSR _ out [ m ]: second output signal

Third output signal

ALLCLEAR: reset control signal

HSR < 1 > -HSR < x >: shift register

DY [1] DY [ y ]: data line

D (1) to D (q), DV (1) to DV (q): data voltage

GDEC [1] to GDEC [ z ]: decoder

RES [ p ]: register with a plurality of registers

SI _ D [ p ]: data signal

Input: input signal

CLK: clock signal

SCS: enable signal

Reset signal

INV: reverser

T1: during initialization

T2: during the sustain period

T3: data setting period

T4: during a reservation

T5: during reset

Claims

1. A data driver, comprising:

a shift register for outputting a first output signal;

a first logic circuit for outputting a second output signal according to the first output signal and a reset control signal outputted from the shift register, wherein the first logic circuit outputs the second output signal having a first logic level when one of the first output signal and the reset control signal has an enable level; and

a data latch, comprising:

a switch for transmitting a data signal to an internal node according to the second output signal, wherein:

during the data setting period, when the first logic circuit outputs the second output signal with the first logic level according to the first output signal with the enable level, the switch is conducted; and

during a reset period, the first logic circuit outputs the second output signal with the first logic level according to the reset control signal with the enable level, so that the switch is turned on to transmit the data signal to the internal node.

2. The data driver of claim 1, comprising:

a register for generating the data signal according to input data, a clock signal and a reset signal, wherein during a reset period, the flip-flop outputs the data signal having a second logic level according to the reset signal having the enable level, and the switch of the data latch is turned on according to the second output signal to transmit the data signal having the second logic level to the internal node.

3. The data driver of claim 1, wherein the data latch further comprises:

a feedback circuit for latching the potential of the internal node according to the second output signal, wherein:

during the reset period, the first logic circuit outputs the second output signal with the first logic level according to the reset control signal with the enable level to turn off the feedback circuit.

4. The data driver of claim 3, wherein during the data setup:

when the first logic circuit outputs the second output signal with the first logic level according to the first output signal with the enable level, the feedback circuit is turned off; and

when the first logic circuit outputs the second output signal with a second logic level according to the first output signal with a forbidden energy level and the reset control signal, the feedback circuit is started.

5. The data driver of claim 3, wherein the feedback circuit is electrically coupled between the internal node of the data latch and an output.

6. The data driver of claim 3, wherein the feedback circuit is implemented by a transmission gate or a sequential control-complementary metal oxide semiconductor logic circuit.

7. The data driver of claim 1, wherein the switching is performed by a transmission gate.

8. The data driver of claim 1, further comprising:

a second logic circuit for outputting a third output signal according to the first output signal and a reset control signal outputted from the shift register, wherein the second logic circuit outputs the third output signal having a second logic level when one of the first output signal and the reset control signal has an enable level.

9. The data driver of claim 8, wherein the switch is configured to transmit the data signal to the internal node according to the third output signal, wherein:

during the data setting period, when the second logic circuit outputs the third output signal having the second logic level according to the first output signal having the enable level, the switch is turned on; and

during the reset period, the second logic circuit outputs the third output signal with the second logic level according to the reset control signal with the enable level to turn on the switch.

10. A control method, comprising:

outputting a first output signal by a shift register;

outputting a second output signal by a first logic circuit according to the first output signal and a reset control signal output by the shift register, wherein when one of the first output signal and the reset control signal has an enable level, the first logic circuit outputs the second output signal having a first logic level;

outputting, by the first logic circuit, the second output signal having the first logic level in accordance with the reset control signal having the enable level during a reset period; and

during the reset, a circuit path between an internal node of a data latch and an output of a register is turned on according to the second output signal having the first logic level to transfer an output of the register to the internal node of the data latch.