CN115474914A

CN115474914A - Pulse diagnosis instrument

Info

Publication number: CN115474914A
Application number: CN202210960838.XA
Authority: CN
Inventors: 杨晓达; 丁正; 陈振华; 徐佳; 宋丹玫; 苏萌; 黄凯; 张积坤
Original assignee: Service Oriented Manufacturing Research Institute Hangzhou Co ltd
Current assignee: Service Oriented Manufacturing Research Institute Hangzhou Co ltd
Priority date: 2022-08-11
Filing date: 2022-08-11
Publication date: 2022-12-16

Abstract

The application relates to a pulse diagnosis instrument, which comprises a host, at least two first measuring assemblies and at least two second measuring assemblies. The first measuring component is used for acquiring a first sound signal under the pressure of a first target area of a human body, and the first target area comprises an area of a part to be diagnosed and is larger than the area of the part to be diagnosed; the second measurement assembly is used for acquiring a second sound signal of a second target area of the human body; and the host is used for obtaining a first measurement result according to the first sound signal and obtaining a second measurement result according to the second sound signal. The pulse diagnosis instrument has high accuracy and stability of measurement results and rich diversity of the measurement results.

Description

Pulse diagnosis instrument

Technical Field

The application relates to the technical field of medical instruments, in particular to a pulse diagnosis instrument.

Background

The pulse diagnosis instrument in the prior art is used for compressing the artery of a detected part of a human body through air, converting weak pulse changes in light, medium and heavy states into electric signals by using a pressure sensor, and then obtaining signal waveforms through signal processing.

However, the pulse diagnosis instrument in the prior art has an error in the measured part at each measurement, which causes the test to be very unstable, and the obtained test result is inaccurate.

Disclosure of Invention

Therefore, it is necessary to provide a pulse diagnosis apparatus with accurate test result, high stability and rich diversity for the above technical problems.

In a first aspect, the present application provides a pulse diagnosis instrument, which includes a host, at least two first measurement assemblies and at least two second measurement assemblies;

the first measuring component is used for acquiring a first sound signal under the pressure of a first target area of a human body, and the first target area comprises an area of a part to be diagnosed and is larger than the area of the part to be diagnosed;

the second measurement component is used for acquiring a second sound signal of a second target area of the human body;

and the host is used for obtaining a first measurement result according to the first sound signal and obtaining a second measurement result according to the second sound signal.

In one embodiment, the host comprises a processor, a conversion module, a voltage management module and an air pressure regulation module, wherein the conversion module, the voltage management module and the air pressure regulation module are all connected with the processor;

the voltage management module is used for controlling the voltage of the processor to rise and fall;

the air pressure adjusting module is used for controlling the first measuring assembly to add or release pressure to the first target area;

the conversion module is used for converting the first sound signal into a first digital signal and converting the second sound signal into a second digital signal;

the processor is configured to obtain the first measurement result according to the first digital signal, and obtain the second measurement result according to the second digital signal.

In one embodiment, the voltage management module comprises a power on/off module, a voltage boosting and reducing control module, a first voltage reducing module, a second voltage reducing module and a first power supply module;

the startup and shutdown module, the voltage boosting and reducing control module, the first voltage reducing module, the second voltage reducing module and the first power supply module are all connected with the processor.

In one embodiment, the pulse diagnosis instrument comprises two first measurement assemblies, and the two first measurement assemblies are connected with the air pressure regulation module.

In one embodiment, the air pressure regulation module comprises a second power supply module, a first air pressure regulation submodule and a second air pressure regulation submodule, wherein the first air pressure regulation submodule is connected with one of the two first measurement assemblies, and the second air pressure regulation submodule is connected with the other of the two first measurement assemblies.

In one embodiment, the first air pressure regulating submodule comprises a first air pressure detection module, a first driving module, a first air pump module, a first air escape valve module and a first air escape valve fine adjustment module;

the second air pressure adjusting submodule comprises a second air pressure detecting module, a second driving module, a second air pump module, a second air escape valve module and a second air escape valve fine adjustment module.

In one embodiment, the host further comprises a power supply detection module and a voltage acquisition module, and the power supply detection module and the voltage acquisition module are both connected with the processor.

In one embodiment, the power supply detection module includes a first detection sub-module, a second detection sub-module, a third detection sub-module, a fourth detection sub-module, a fifth detection sub-module, a sixth detection sub-module, and a seventh detection sub-module.

In one embodiment, the host further comprises a USB-TYPE module, an external power on/off module, a battery interface module, an extension indication module, a status indication module, a debug button module, a display module, a storage module, and a bluetooth module, wherein the USB-TYPE module, the external power on/off module, the battery interface module, the extension indication module, the status indication module, the debug button module, the display module, the storage module, and the bluetooth module are all connected to the processor;

the second measurement component is connected with the USB-TYPE module.

In one embodiment, the first measuring assembly comprises a pressure belt, and the length of the pressure belt is 3 cm-15 cm;

the second measurement assembly includes a stethoscope.

The pulse diagnosis instrument comprises a host, at least two first measuring assemblies and at least two second measuring assemblies. The first measuring component is used for acquiring a first sound signal under the pressure of a first target area of a human body, and the first target area comprises an area of a part to be diagnosed and is larger than the area of the part to be diagnosed; the second measurement assembly is used for acquiring a second sound signal of a second target area of the human body; and the host is used for obtaining a first measurement result according to the first sound signal and obtaining a second measurement result according to the second sound signal. The first target area comprises the area of the part to be diagnosed and is larger than the area of the part to be diagnosed, the first measuring assembly can collect the first sound signal which is amplified and pressed in a larger range, and therefore the accuracy and the stability of the measuring result of the pulse diagnosis instrument can be improved. In addition, the second sound signal of the second target area of the human body is acquired by the second measuring assembly, so that the diversity of measuring results can be enriched.

Drawings

Fig. 1 is a schematic structural diagram of a pulse diagnosis instrument provided in an embodiment of the present application;

FIG. 2 is a block diagram of a host computer according to an embodiment of the present application;

FIG. 3 is a circuit diagram of a processor in one embodiment of the present application;

FIG. 4 is a circuit diagram of a conversion module in one embodiment of the present application;

FIG. 5 is a block diagram of a voltage management module in an embodiment of the present application;

FIG. 6 is a circuit diagram of a power on/off module in an embodiment of the present application;

FIG. 7 is a circuit diagram of a buck-boost control module in an embodiment of the present application;

FIG. 8 is a circuit diagram of a first buck module in one embodiment of the present application;

FIG. 9 is a circuit diagram of a second buck module in one embodiment of the present application;

FIG. 10 is a circuit diagram of a first power module in one embodiment of the present application;

FIG. 11 is a block diagram of an exemplary embodiment of an air pressure adjustment module;

FIG. 12 is a circuit diagram of a second power module in one embodiment of the present application;

FIG. 13 is a circuit diagram of a first air pressure detection module in one embodiment of the present application;

FIG. 14 is a circuit diagram of a first driver module in one embodiment of the present application;

FIG. 15 is a circuit diagram of a first air pump module in an embodiment of the present application;

FIG. 16 is a circuit diagram of a first bleed valve module in accordance with one embodiment of the present application;

FIG. 17 is a circuit diagram of a first bleed valve trim module according to an embodiment of the present application;

FIG. 18 is a circuit diagram of a second air pressure detection module in an embodiment of the present application;

FIG. 19 is a circuit diagram of a second driver module in one embodiment of the present application;

FIG. 20 is a circuit diagram of a second air pump module in one embodiment of the present application;

FIG. 21 is a circuit diagram of a second bleed valve module in accordance with one embodiment of the present application;

FIG. 22 is a circuit diagram of a second bleed valve trim module in accordance with an embodiment of the present application;

FIG. 23 is a block diagram of a power detection module in accordance with an embodiment of the present application;

FIG. 24 is a circuit diagram of a first detection submodule in an embodiment of the present application;

FIG. 25 is a circuit diagram of a second detection submodule according to an embodiment of the present application;

FIG. 26 is a circuit diagram of a third detection submodule according to an embodiment of the present application;

FIG. 27 is a circuit diagram of a fourth detection submodule in an embodiment of the present application;

FIG. 28 is a circuit diagram of a fifth detection submodule in an embodiment of the present application;

FIG. 29 is a circuit diagram of a sixth detection submodule in an embodiment of the present application;

FIG. 30 is a circuit diagram of a seventh detection sub-module in an embodiment of the present application;

FIG. 31 is a circuit diagram of a voltage acquisition module in an embodiment of the present application;

FIG. 32 is a block diagram of a host computer according to an embodiment of the present application;

FIG. 33 is a circuit diagram of a Bluetooth module in one embodiment of the present application;

FIG. 34 is a circuit diagram of a USB-TYPE module in an embodiment of the present application;

FIG. 35 is a circuit diagram of an external power on/off module according to an embodiment of the present application;

FIG. 36 is a circuit diagram of a battery interface module in an embodiment of the present application;

FIG. 37 is a circuit diagram of an extended indicating module in one embodiment of the present application;

FIG. 38 is a circuit diagram of a status indication module in one embodiment of the present application;

FIG. 39 is a circuit diagram of a debug button module in an embodiment of the present application;

FIG. 40 is a circuit diagram of a display module in one embodiment of the present application;

FIG. 41 is a circuit diagram of an external memory submodule in an embodiment of the present application;

FIG. 42 is a circuit diagram of an internal memory submodule in an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

In one embodiment, as shown in fig. 1, fig. 1 is a schematic structural diagram of a pulse diagnosis instrument provided in the embodiment of the present application. The pulse diagnosis instrument comprises a host machine 100, at least two first measuring assemblies 200 and at least two second measuring assemblies 300.

The first measuring component 200 is configured to collect a first sound signal generated by compressing and releasing a first target area of a human body, where the first target area includes an area of a part to be diagnosed and is larger than the area of the part to be diagnosed. A second measurement component 300 for acquiring a second sound signal of a second target region of the human body. It should be noted that the first target region may be, but is not limited to, a section of an arm or a leg, the second target region may be, but is not limited to, a heart region, a chest region, or a certain point of an abdomen, and the diagnostic region may be a point where the arm or the leg can measure a pulse. The first measurement component 200 is used for collecting the sound signals of the first target area, the area of the first target area is large, the first measurement component 200 can collect the signals with wide range of positions to be measured, the accuracy and the stability of the measurement result of the pulse diagnosis instrument can be enhanced, the pulse diagnosis instrument of the embodiment collects the sound signals of the second target area by using the second measurement component 300 besides collecting the sound signals of the first target area, and the diversity of sampling data of the pulse diagnosis instrument can be enriched.

The host 100 is configured to obtain a first measurement result according to the first sound signal and obtain a second measurement result according to the second sound signal. The host 100 of this embodiment can also analyze and display the first measurement result and the second measurement result, specifically, the data monitoring and health management software included in the host 100 is used to process the sound signal, analyze the signal data, display the analysis result, and give a health management suggestion.

In one embodiment, as shown in fig. 2, fig. 2 is one of the structural block diagrams of the host 100 in one embodiment of the present application, and the host 100 includes a processor 400, a conversion module 500, a voltage management module 600, and a pressure regulation module 700, where the conversion module 500, the voltage management module 600, and the pressure regulation module 700 are all connected to the processor 400.

The voltage management module 600 is configured to control voltage increase and decrease of the processor 400; the air pressure adjusting module 700 is configured to control the first measuring assembly 200 to apply and release pressure to the first target area; a conversion module 500, configured to convert the first sound signal into a first digital signal, and convert the second sound signal into a second digital signal; the processor 400 is configured to obtain a first measurement result according to the first digital signal and obtain a second measurement result according to the second digital signal.

In one embodiment, as shown in fig. 3, fig. 3 is a circuit diagram of a processor 400 in an embodiment of the present application, where the processor 400 is provided with chips U10A and U10B of model STM32F429VIT6, and an interface CN10, a capacitor C58, a capacitor C59, a capacitor C60, a capacitor C61, a capacitor C62, a capacitor C63, a capacitor C64, a capacitor C65, a capacitor C66, a capacitor C67, a capacitor C68, a capacitor C69, a capacitor C70, a capacitor C71, a capacitor C72, a capacitor C94, a capacitor C95, a capacitor BAT1, a resistor R73, a resistor R74, a patch resistor LR7, a crystal oscillator X1, a crystal oscillator X2, a zener diode D4, a zener diode D7, and a reset switch SW4.

Specifically, one end of a capacitor C71 is connected to pin 73 of the chip U10A, the other end of the capacitor C71 is grounded, one end of a capacitor C72 is connected to pin 49 of the chip U10A, the other end of the capacitor C71 is grounded, one end of a resistor R73 is connected to pin 70 of the chip U10A, one end of a resistor R74 is connected to pin 71 of the chip U10A, one end of a capacitor C94 is connected to one end of the crystal oscillator X2, the other end of the capacitor C94 is grounded, one end of a capacitor C95 is connected to the other end of the crystal oscillator X2, the other end of the capacitor C95 is grounded, one end of the crystal oscillator X2 is connected to pin 8 of the chip U10A, the other end of the crystal oscillator X2 is connected to pin 9 of the chip U10A, one end of a capacitor C58 is connected to pin 1, the other end of a capacitor C58 is grounded, one end of a capacitor C59 is connected to the other end of the crystal oscillator X1, one end of the crystal oscillator X1 is connected to pin 12 of the chip U10A, the other end of the chip X1 is connected to pin 13 of the chip U10A, pin 1 of interface CN10 is connected with 3V power supply, pin 2 of interface CN10 is connected with pin 72 of chip U10A, pin 3 of interface CN10 is connected with pin 76 of chip U10A, pin 3 of interface CN10 is connected with pin 94 of chip U10A, pins 5 and 6 of interface CN10 are grounded, one end of capacitor C67 is connected with the negative pole of zener diode D4, the other end of capacitor C67 is grounded, the other end of zener diode D4 is connected with the positive pole of capacitor BAT1, the negative pole of capacitor BAT1 is grounded, the negative pole of zener diode D7 is connected with the negative pole of zener diode D4, the positive pole of zener diode D7 is connected with 3V power supply, one end of capacitor C60 is connected with the positive pole of zener diode D7, the other end of capacitor C60 is grounded, one end of capacitor C61 is connected with the positive pole of zener diode D7, the other end of capacitor C61 is grounded, one end of capacitor C62 is connected with the positive pole of zener diode D7, the other end of capacitor C62 is grounded, one end of a capacitor C63 is connected with the anode of a voltage stabilizing diode D7, the other end of the capacitor C63 is grounded, one end of a capacitor C64 is connected with the anode of the voltage stabilizing diode D7, the other end of the capacitor C64 is grounded, one end of a capacitor C65 is connected with the anode of the voltage stabilizing diode D7, the other end of the capacitor C65 is grounded, one end of a capacitor C66 is connected with the anode of the voltage stabilizing diode D7, the other end of the capacitor C66 is grounded, a pin 6 of a chip U10B is connected with the cathode of a voltage stabilizing diode D4, one ends of a capacitor C69, a capacitor C68 and a chip resistor LR7 are all connected with a pin 22 of the chip U10B, the other ends of the capacitor C69 and the capacitor C68 are grounded, the other end of the chip resistor LR7 is connected with a 3V power supply, the pins 11, 19, 28, 50, 75 and 100 of the chip U10B are connected with the 3V power supply, the pins 10, 27, 74, 99 and 20 of the chip U10B are grounded, one end of the capacitor C70 is connected with the pin 14 of the chip U10A, the other end of the capacitor C70 is grounded, the 2 nd position of the reset switch SW4 is connected with the pin 14 of the chip U10A, and the 1 st position, the 3 rd position, the 4 th position and the 5 th position of the reset switch SW4 are grounded.

Referring to fig. 4, fig. 4 is a circuit diagram of a conversion module 500 according to an embodiment of the present application, in which the conversion module 500 includes a chip U1, capacitors C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, a chip resistor LR1, a chip resistor LR2, a chip resistor LR3, a variable resistor MIC _ R1, a variable resistor MIC _ R2, a test interface JP1, a test interface T2, a test interface T3, a test interface T4, a test interface T5, and a test interface T6.

Specifically, one end of a capacitor C1, one end of a capacitor C2 and one end of a chip resistor LR1 are all connected with a pin 26 of a chip U1, the other end of the capacitor C1 and the other end of the capacitor C2 are all grounded, one end of a capacitor C3, one end of a capacitor C4 and one end of a chip resistor LR2 are all connected with a pin 31 of the chip U1, the other end of the capacitor C3 and the other end of the capacitor C4 are all grounded, the other end of the chip resistor LR2 is connected with the other end of the chip resistor LR1, one end of a capacitor C8, one end of a capacitor C9 and one end of a chip resistor LR3 are all connected with a pin 14 of the chip U1, the other end of the capacitor C8 and the other end of the capacitor C9 are all grounded, a pin 13 of the chip U1 is connected with a pin 14 of the chip U1, pins 12, 24, 33 and 28 of the chip are all grounded, a pin 7 of the chip U1 is connected with a pin 3 of the chip U10A, a pin 8 of the chip U1 is connected with a pin 4 of the chip U10A, and a pin 9 of the chip U1 is connected with a pin 2, pin 10 of chip U1 is connected to pin 5 of chip U10A, pin 11 of chip U1 is connected to pin 1 of chip U10A, pin 16 of chip U1 is connected to pin 92 of chip U10A, pin 17 of chip U1 is connected to pin 93 of chip U10A, one end of resistor R5 is connected to pin 16 of chip U1, one end of resistor R6 is connected to pin 17 of chip U1, one end of resistor R7 is connected to pin 18 of chip U1, the other end of resistor R7 is grounded, one end of resistor R2 is connected to pin 3 of chip U1, the other end of resistor R2 is grounded, one end of resistor R3 is connected to pin 6 of chip U1, the other end of resistor R3 is grounded, one end of capacitor C5 is connected to pin 1 of chip U1, one end of resistor R1 and 2 nd position of resistor variable MIC _ R1 are connected to the other end of capacitor C5, the other end of resistor R1 is connected to 1 st position of variable MIC _ R1, and one end of capacitor C6 is connected to pin 2 of chip U1, the other end of the capacitor C6 is connected with the 3 rd position of the variable resistor MIC _ R1, one end of the capacitor C7 is connected with the 4 th pin of the chip U1, one end of the resistor R4 and the 2 nd position of the variable resistor MIC _ R2 are both connected with the other end of the capacitor C7, the other end of the resistor R4 is connected with the 1 st position of the variable resistor MIC _ R2, one end of the capacitor C10 is connected with the 5 th pin of the chip U1, the other end of the capacitor C10 is connected with the 3 rd position of the variable resistor MIC _ R2, one end of the capacitor C11 is connected with the 19 th pin of the chip U1, one end of the capacitor C12 is connected with the 20 th pin of the chip U1, the other end of the capacitor C11, the other end of the capacitor C12, one end of the resistor R12 and the 2 nd pin of the test interface JPA are all connected with one end of the capacitor C17, the other end of the resistor R12 is connected with the 29 th pin of the chip U10A, the other end of the capacitor C17 is grounded, one end of the capacitor C15 is connected with the 32 th pin of the chip U1, one end of a capacitor C14 is connected with a pin 27 of a chip U1, the other end of a capacitor C15 and the other end of the capacitor C14 are grounded, one end of a resistor R8 and one end of a resistor R10 are connected with a pin 32 of the chip U1, one end of a resistor R9 and one end of a capacitor C13 are connected with the other end of the resistor R8 and a test interface T1, the other end of the resistor R9 and the other end of the capacitor C13 are connected with a pin 1 of the test interface JP1, one end of a resistor R11 and one end of a capacitor C16 are connected with the other end of the resistor R10 and a test interface T2, the other end of the resistor R11 and the other end of the capacitor C16 are connected with a pin 1 of the test interface JP1, a pin 3 of the test interface JP1 is connected with a pin 1 of the test interface JP1, a pin T3 of the test interface T1 is connected with a pin 32 of the chip U1, a test interface T4 is connected with a pin 26 of the chip U1, a test interface T5 is connected with a pin 31 of the chip U1, and a test interface T6 is connected with a pin 14 of the chip U1.

In one embodiment, as shown in fig. 5, fig. 5 is a block diagram of a voltage management module 600 in an embodiment of the present application, and the voltage management module 600 includes a power on/off module 610, a buck-boost control module 620, a first buck module 630, a second buck module 640, and a first power supply module 650. Specifically, the power on/off module 610, the buck-boost control module 620, the first voltage reduction module 630, the second voltage reduction module 640, and the first power supply module 650 are all connected to the processor 400. The power on/off module 610 is configured to control power on or off of the host 100, the voltage step-up/step-down control module 620 is configured to control voltage step-up and step-down of the processor 400, the first voltage step-down module 630 and the second voltage step-down module 640 are configured to control voltage step-down of the processor 400, and the first power supply module 650 is configured to supply power to the processor 400.

As shown in fig. 6, fig. 6 is a circuit diagram of a switching module 610 in an embodiment of the present application, where the switching module 610 is provided with a chip U6, a resistor R26, a resistor R30, a resistor R31, a resistor R32, a resistor R33, a resistor R34, a resistor R35, a resistor R37, a resistor R38, a resistor R39, a resistor R40, a capacitor C23, a capacitor C24, a capacitor C34, a capacitor C36, a capacitor C37, a capacitor C38, a capacitor C39, a capacitor C40, a zener diode D3, a light emitting diode LED3, an inductor L4, a test interface T7, a test interface T9, a test interface T10, a test interface T13, a transistor Q3, and a reset switch SW3.

Specifically, pin 1 of chip U6 is connected to pin 24 of chip U6, pin 24 of chip U6 and one end of capacitor C36 are both connected to 5V voltage, the other end of capacitor C36 and one end of resistor R31 are both grounded, the other end of resistor R31 is connected to pin 10 of chip U6, one end of resistor R26 is connected to pin 4 of chip U6, test interface T10 and the negative electrode of LED3 are both connected to the other end of resistor R26, the positive electrode of LED3 is connected to a system power supply, one end of resistor R32 is connected to pin 2 of chip U6, the other end of resistor R32 is connected to pin 3 of chip U6, pin 8 of chip U6 is grounded, pin 5 of chip U6 is connected to pin 47 of chip U10A, pin 6 of chip U6 is connected to pin 48 of chip U10A, pin 7 of chip U6 is connected to pin 51 of chip U10A, pin 9 of chip U6 is connected to pin 52 of chip U10A, one end of resistor R37 is connected to pin 5 of chip U6, and pin 38 of resistor R6 is connected to pin 38 of chip U6, one end of a resistor R39 is connected with a pin 7 of a chip U6, the other end of the resistor R37, the other end of a resistor R38 and the other end of the resistor R39 are connected with 3V voltage, one end of a capacitor C23, one end of a capacitor C24 and a test interface T7 are connected with a pin 23 of the chip U6, the other end of the capacitor C23 and the other end of the capacitor C24 are grounded, one end of a capacitor C34 is connected with a pin 21 of the chip U6, the other end of the capacitor C34, a pin 20 of the chip U6 and a pin 19 of the chip U6 are connected with one end of an inductor L4, the other end of the inductor L4, a pin 16 of the chip U6, a pin 15 of the chip U6, a test interface T9, one end of the capacitor C37 and one end of the capacitor C38 are connected with system voltage, the other end of the capacitor C37, the other end of the capacitor C38, one end of the capacitor C39 and one end of a resistor R35 are grounded, the other end of the resistor R35, the other end of the resistor R35, a pin 22 of the chip U6 and one end of the resistor R40 are connected with the test interface T3, the other end of the resistor R40, the pin 18 of the chip U6, the pin 17 of the chip U6 and the pin 25 of the chip U6 are all grounded, the 1 st position of the reset switch is connected with the pin 12 of the chip U6, the 2 nd position of the reset switch is connected with the pin 13 of the chip U6, the pin 14 of the chip U6 is connected with the pin 13 of the chip U6, one end of the zener diode D3 is connected with the pin 12 of the chip U6, one ends of the resistor R33 and the capacitor C40 are both connected with the other end of the zener diode D3, one end of the resistor R34 and the end B of the triode Q are both connected with the other end of the resistor R33, the other end of the capacitor C40, the other end of the resistor R34 and the end E of the triode Q are all grounded, the end C of the triode Q and one end of the resistor R30 are both connected with the pin 77 of the chip U10A, and the other end of the resistor R30 is connected with 3V voltage.

As shown in fig. 7, fig. 7 is a circuit diagram of the buck-boost control module 620 according to an embodiment of the present application, and the buck-boost control module 620 is provided with a chip U4, a chip U5, a capacitor C25, a capacitor C26, a capacitor C27, a capacitor C28, a capacitor C29, a capacitor C30, a capacitor C31, a capacitor C32, a capacitor C33, a capacitor C35, a resistor R24, a resistor R25, a resistor R27, a resistor R28, a resistor R29, an inductor L1, an inductor L2, an inductor L3, a zener diode D1, and a zener diode D2.

Specifically, one end of the capacitor C26, one end of the capacitor C27, one end of the zener diode D2, one end of the inductor L3, and 3 pins of the chip U5 are all connected to the system voltage, the other end of the capacitor C26, the other end of the capacitor C27, the other end of the zener diode D2, one end of the resistor R29, pin 1 of the chip U5, pin 5 of the chip U5, pin 9 of the chip U5, one end of the resistor R27, one end of the capacitor C29, one end of the capacitor C30, one end of the capacitor C28, one end of the capacitor C31, pin 2 of the photo U4, one end of the capacitor C35, one end of the capacitor C32, one end of the capacitor C33, and one end of the resistor R28 are all grounded, the other end of the resistor R29 is connected to pin 2 of the chip U5, pin 4 of the chip U5 is connected to pin 85 of the chip U10A, pin 8 of the chip U5 and one end of the zener diode D1 are all connected to the other end of the inductor L3, the other end of zener diode D1, the one end of resistance R24, the other end of electric capacity C29, the other end of electric capacity C30, the other end of electric capacity C28, the other end of electric capacity C31, 4 feet of chip U4, 5V voltage is all connected to 1 foot and test interface T8 of chip U4, the other end of resistance R24 and the other end of resistance R27 all are connected with 6 feet of chip U5, the other end of electric capacity C36 and the one end of inductance L2 are all connected with the other end of inductance L1 are connected to one end and the 3 feet of chip U4 of inductance L1, the other end of inductance L2, the other end of electric capacity C32, the other end of electric capacity C33, 3V voltage is all connected to one end of resistance R25 and one end of electric capacity C25, the other end of resistance R28 and the other end of resistance R25 all are connected with 5 feet of chip U4.

As shown in fig. 8, fig. 8 is a circuit diagram of the first voltage-reducing module 630 in an embodiment of the present application, the first voltage-reducing module 630 is provided with a chip IC1, a capacitor C42, a capacitor C43, a capacitor C44, a capacitor C46, and a test interface T11, one end of the capacitor C44 and one end of the pin 1 of the chip IC1 are both connected to a voltage of 5V, pin 3 of the chip IC1 is connected to pin 95 of the chip U10A, pin 5 of the photo IC1, the test interface T11, one end of the capacitor C43, and one end of the capacitor C42 are both connected to a voltage of 3V, the other end of the capacitor C44, pin 2 of the chip IC1, one end of the capacitor C46, the other end of the capacitor C43, and the other end of the capacitor C42 are all grounded, and the other end of the capacitor C46 is connected to pin 4 of the chip IC 1.

As shown in fig. 9, fig. 9 is a circuit diagram of the second voltage-reducing module 640 in an embodiment of the present application, the second voltage-reducing module 640 is provided with a chip U7, a resistor R36, a resistor R41, a capacitor C45, a capacitor C41, a capacitor C47, and a chip resistor LR4, one end of the chip resistor LR4 is connected to a voltage of 5V, the other end of the chip resistor LR4 and one end of the capacitor C45 are connected to a pin 8 of the chip U7, the other end of the capacitor C45, a pin 4 of the chip U7, a pin 9 of the chip U7, one end of the capacitor C48, one end of the resistor R41, and one end of the capacitor C47 are all grounded, the other end of the capacitor C48 is connected to a pin 6 of the chip U7, a pin 5 of the chip U7 is connected to a pin 95 of the chip U10A, one end of the resistor R36, the other end of the resistor R41, and one end of the capacitor C41 are all connected to a pin 2 of the chip U7, a pin 1 of the chip U7, the other end of the resistor R36, the other end of the capacitor C41, the test interface T12, and the other end of the capacitor C47 are all connected to a voltage of the chip U3V.

As shown in fig. 10, fig. 10 is a circuit diagram of a first power supply module 650 in an embodiment of the present application, the first power supply module 650 is provided with a chip U8, a chip U9, a capacitor C49, a capacitor C50, a capacitor C51, a capacitor C52, a capacitor C53, a capacitor C54, a capacitor C55, a capacitor C56, a capacitor C57, a resistor R42, a resistor R43, a resistor R44, a patch resistor LR5, and a ground test point TP1, one end of the patch resistor LR5 is connected to a voltage of 5V, the other end of the patch resistor LR5, one end of the capacitor C51, and one end of the capacitor C52 are connected to pin 2 of the chip U9, the other end of the capacitor C51, the other end of the capacitor C52, pin 4 of the chip U9, one end of the capacitor C56, one end of the capacitor C49, one end of the capacitor C50, one end of the capacitor C57, one end of the capacitor C54, one end of the capacitor C53, one end of the capacitor C55, and one end of the resistor R44, and pin 4 of the chip U8 are all grounded, the other end of the capacitor C56 is connected with the 5 pins of the chip U9, the 6 pins of the chip U9, the other end of the capacitor C49, the other end of the capacitor C50 and one end of the resistor R43 are connected with the 21 pins of the chip U10B, the other end of the resistor R43, the other end of the resistor R44 and the other end of the capacitor C57 are connected with the 3 pins of the chip U8, the 2 pins of the chip U8, the 6 pins of the chip U8, the other end of the capacitor C53 and one end of the resistor R42 are connected with the 27 pins of the chip U1, the 7 pins of the chip U8 and the other end of the capacitor C54 are connected with 5V voltage, the other end of the resistor R42 and the other end of the capacitor C55 are connected with the 17 pins of the chip U10A, and the grounding test point TP1 is grounded.

In one embodiment, the pulse diagnosis apparatus includes two first measurement assemblies 200, and both first measurement assemblies 200 are connected to the air pressure adjusting module 700.

As shown in fig. 11, fig. 11 is a block diagram of an air pressure adjusting module 700 according to an embodiment of the present disclosure, where the air pressure adjusting module 700 includes a second power supply module 710, a first air pressure adjusting submodule 720, and a second air pressure adjusting submodule 730, the first air pressure adjusting submodule 720 is connected to one of the two first measuring assemblies 200, and the second air pressure adjusting submodule 730 is connected to the other of the two first measuring assemblies 200.

Specifically, the second power supply module 710 is configured to supply power to the first air pressure adjusting submodule 720 and the second air pressure adjusting submodule 730, and the first air pressure adjusting submodule 720 and the second air pressure adjusting submodule 730 are configured to adjust the air pressure of the corresponding first measurement assembly 200.

In one embodiment, the first air pressure regulating submodule 720 includes a first air pressure detecting module 721, a first driving module 722, a first air pump module 723, a first air bleed valve module 724, and a first air bleed valve trim module 725; the second air pressure adjusting sub-module 730 includes a second air pressure detecting module 731, a second driving module 732, a second air pump module 733, a second air release valve module 734 and a second air release valve fine tuning module 735. The first air pressure detecting module 721 and the second air pressure detecting module 731 are used for detecting the air pressure of the corresponding first measuring assembly 200, and the first driving module 722 and the second driving module 732 are used for driving the corresponding air pump module, the air release valve module and the air release valve fine tuning module to correspondingly control the first measuring assembly 200 to perform air filling, air releasing and air release fine tuning.

As shown in fig. 12, fig. 12 is a circuit diagram of a second power supply module 710 in an embodiment of the present application, the second power supply module 710 is provided with a chip U12, an interface Q7, a capacitor C84, a capacitor C85, a capacitor C86, a capacitor C87, a capacitor C88, a capacitor C89, a resistor C68, a resistor C69, a resistor C70, a resistor C71, a zener diode D5, a zener diode D6, a transistor Q8, a test interface T23, and a test interface T24, one end of the capacitor C88, one end of the capacitor C89, a pin 8 of the interface Q7, a pin 7 of the interface Q7, a pin 6 of the interface Q7, a pin 5 of the interface Q7, and one end of the resistor R69 are all connected with a voltage of 5V, the other end of the capacitor C88, the other end of the capacitor C89, the end of the transistor E, the anode of the zener diode D5, one end of the capacitor C85, one end of the capacitor C86, one end of the capacitor C87, one end of the pin 9 of the chip U12, a pin 3 of the chip U12, the anode of the zener diode D6, one end of the resistor R70, and one end of the capacitor C84, the other end of the resistor R69 and the end C of the triode are connected with the pin 4 of the interface Q7, one end of the resistor R71 is connected with the pin 98 of the chip U10A, the other end of the resistor R71 is connected with the end B of the triode Q8, the cathode of the voltage stabilizing diode, the pin 1 of the interface Q7, the pin 2 of the interface Q7, the pin 3 of the interface Q7 and the other end of the capacitor C85, the other end of the capacitor C86, the other end of the capacitor C87 and the pin 8 of the chip U12 are connected with the test interface T23, the test interface T23 is connected with 5V voltage, the pin 5 of the chip U12 is connected with the pin 97 of the chip U10A, the pin 2 of the chip U12 and the other end of the resistor R70 are connected with one end of the resistor R68, the pin 1 of the chip U12, the cathode of the voltage stabilizing diode D6, the other end of the resistor R68 and the other end of the capacitor C84 are connected with the test interface T24, and the test interface T24 is connected with 3V voltage.

As shown in fig. 13, fig. 13 is a circuit diagram of the first air pressure detecting module 721 in an embodiment of the present application, the first air pressure detecting module 721 is provided with a chip U13, a capacitor C90 and a capacitor C91, a pin 3 of the chip U13 is grounded, a pin 2 of the chip U13 is connected to the test interface T12, a pin 4 of the chip U13 and one end of the capacitor C90 are connected to 3V voltage, a pin 6 of the chip U13, the other end of the capacitor C90 and one end of the capacitor C91 are grounded, and the other end of the capacitor C91 is connected to a pin 5 of the chip U13.

As shown in fig. 14, fig. 14 is a circuit diagram of a first driving module 722 in an embodiment of the present application, the first driving module 722 is provided with an interface Q9, pins 1, 2, and 3 of the interface Q9 are all connected to pin 67 of the chip U10A, pins 4 and 5 of the interface Q9 are all connected to pin 43 of the chip U10A, pins 6 and 7 of the interface Q9 are all connected to pin 44 of the chip U10A, pin 8 of the interface Q9 is connected to ground, and pin 9 of the interface Q9 is connected to the test interface T23.

As shown in fig. 15, fig. 15 is a circuit diagram of a first air pump module 723 in an embodiment of the present application, the first air pump module 723 is provided with an interface CN3, pins 3 and 4 of the interface CN3 are grounded, pins 14, 15, and 16 of an interface Q9 are all connected to pin 1 of the interface CN3, and pin 2 of the interface CN3 is connected to a test interface T24.

As shown in fig. 16, fig. 16 is a circuit diagram of a first air bleed valve module 724 according to an embodiment of the present application, the first air bleed valve module 724 is provided with an interface CN4, pins 3 and 4 of the interface CN4 are grounded, pins 12 and 13 of the interface Q9 are both connected to pin 1 of the interface CN4, and pin 2 of the interface CN4 is connected to a test interface T23.

As shown in fig. 17, fig. 17 is a circuit diagram of a first deflation valve trimming module 725 in an embodiment of the present application, the first deflation valve trimming module 725 is provided with an interface CN5, pins 3 and 4 of the interface CN5 are grounded, pins 10 and 11 of the interface Q9 are both connected to pin 1 of the interface CN5, and pin 2 of the interface CN5 is connected to a test interface T23.

As shown in fig. 18, fig. 18 is a circuit diagram of a second air pressure detecting module 731 in an embodiment of the present application, where the second air pressure detecting module 731 is provided with a chip U14, a capacitor C92, and a capacitor C93, a pin 3 of the chip U14 is grounded, a pin 2 of the chip U14 is connected to the test interface T12, a pin 4 of the chip U14 and one end of the capacitor C92 are connected to a 3V voltage, a pin 6 of the chip U14, the other end of the capacitor C92, and one end of the capacitor C93 are grounded, and the other end of the capacitor C93 is connected to a pin 5 of the chip U14.

As shown in fig. 19, fig. 19 is a circuit diagram of a second driver module 732 in an embodiment of the present application, where the second driver module 732 is provided with an interface Q10, pins 1, 2, and 3 of the interface Q10 are all connected to pin 66 of a chip U10A, pins 4 and 5 of the interface Q10 are all connected to pin 45 of the chip U10A, pins 6 and 7 of the interface Q10 are all connected to pin 46 of the chip U10A, pin 8 of the interface Q10 is connected to ground, and pin 9 of the interface Q10 is connected to a test interface T23.

As shown in fig. 20, fig. 20 is a circuit diagram of the second air pump module 733 in an embodiment of the present application, the second air pump module 733 is provided with an interface CN6, pins 3 and 4 of the interface CN6 are grounded, pins 14, 15 and 16 of the interface Q10 are all connected to pin 1 of the interface CN6, and pin 2 of the interface CN6 is connected to the test interface T24.

As shown in fig. 21, fig. 21 is a circuit diagram of a second air release valve module 734 according to an embodiment of the present application, the second air release valve module 734 is provided with an interface CN7, pins 3 and 4 of the interface CN7 are grounded, pins 12 and 13 of the interface Q10 are both connected to pin 1 of the interface CN7, and pin 2 of the interface CN7 is connected to a test interface T23.

As shown in fig. 22, fig. 22 is a circuit diagram of a second bleed valve fine tuning module 735 according to an embodiment of the present invention, the second bleed valve fine tuning module 735 is provided with an interface CN8, pins 3 and 4 of the interface CN8 are grounded, pins 10 and 11 of the interface Q10 are both connected to pin 1 of the interface CN8, and pin 2 of the interface CN8 is connected to a test interface T23.

In one embodiment, the host 100 further includes a power supply detection module 800 and a voltage acquisition module 900, and both the power supply detection module 800 and the voltage acquisition module 900 are connected to the processor 400. Specifically, the power supply detection module 800 is configured to detect a power supply condition of the entire host 100, and the voltage collection module 900 is configured to collect voltages of modules included in the entire host 100.

As shown in fig. 23, fig. 23 is a block diagram of a power supply detection module 800 according to an embodiment of the present application, and the power supply detection module 800 includes a first detection sub-module 810, a second detection sub-module 820, a third detection sub-module 830, a fourth detection sub-module 840, a fifth detection sub-module 850, a sixth detection sub-module 860, and a seventh detection sub-module 870.

As shown in fig. 24, fig. 24 is a circuit diagram of a first detection sub-module 810 in an embodiment of the present application, the first detection sub-module 810 is provided with a resistor R48, a resistor R51, a capacitor C76, and a test interface T15, one end of the capacitor C76, one end of the resistor R48, and one end of the resistor R51 are all connected to the pin 35 of the chip U10A, the other end of the capacitor C76 and the other end of the resistor R51 are all grounded, and the other end of the resistor R48 is connected to the anode of the light emitting diode LED 3.

As shown in fig. 25, fig. 25 is a circuit diagram of a second detection sub-module 820 in an embodiment of the present application, where the second detection sub-module 820 is provided with a resistor R49, a resistor R52, a capacitor C77, and a test interface T16, one end of the capacitor C77, one end of the resistor R49, and one end of the resistor R52 are all connected to pin 30 of the chip U10A, the other end of the capacitor C77 and the other end of the resistor R52 are all grounded, and the other end of the resistor R49 is connected to the test interface T12.

As shown in fig. 26, fig. 26 is a circuit diagram of a third detection submodule 830 in an embodiment of the present application, the third detection submodule 830 is provided with a resistor R59, a resistor R63, a capacitor C79, and a test interface T18, one end of the capacitor C79, one end of the resistor R63, and one end of the resistor R59 are all connected to the pin 33 of the chip U10A, and the other end of the capacitor C79 and the other end of the resistor R63 are all grounded.

As shown in fig. 27, fig. 27 is a circuit diagram of a fourth detection sub-module 840 according to an embodiment of the present application, where the fourth detection sub-module 840 is provided with a resistor R60, a resistor R64, a capacitor C80, and a test interface T19, one end of the capacitor C80, one end of the resistor R60, and one end of the resistor R64 are all connected to the pin 32 of the chip U10A, the other end of the capacitor C80 and the other end of the resistor R64 are all grounded, and the other end of the resistor R60 is connected to the ungrounded end of the capacitor C33.

As shown in fig. 28, fig. 28 is a circuit diagram of a fifth detection sub-module 850 in an embodiment of the present application, the fifth detection sub-module 850 is provided with a resistor R58, a resistor R67, a capacitor C81, and a test interface T20, one end of the capacitor C81, one end of the resistor R58, and one end of the resistor R67 are all connected to pin 34 of the chip U10A, the other end of the capacitor C81 and the other end of the resistor R67 are all grounded, and the other end of the resistor R58 is connected to the test interface T8.

As shown in fig. 29, fig. 29 is a circuit diagram of a sixth detection sub-module 860 in an embodiment of the present application, where the sixth detection sub-module 860 is provided with a resistor R61, a resistor R65, a capacitor C82, and a test interface T21, one end of the capacitor C82, one end of the resistor R61, and one end of the resistor R65 are all connected to pin 31 of the chip U10A, the other end of the capacitor C82 and the other end of the resistor R65 are all grounded, and the other end of the resistor R61 is connected to the test interface T11.

As shown in fig. 30, fig. 30 is a circuit diagram of a seventh detection submodule 870 in an embodiment of the present application, the seventh detection submodule 870 is provided with a resistor R62, a resistor R66, a capacitor C83, and a test interface T22, one end of the capacitor C83, one end of the resistor R62, and one end of the resistor R66 are all connected to the 36 pin of the chip U10A, the other end of the capacitor C83 and the other end of the resistor R66 are all grounded, and the other end of the resistor R62 is connected to the test interface T24.

As shown in fig. 31, fig. 31 is a circuit diagram of a voltage acquisition module 900 according to an embodiment of the present disclosure, the voltage acquisition module 900 is provided with a resistor R50, a resistor R53, a resistor R54, a resistor R55, a resistor R56, a resistor R57, a capacitor C78, a transistor Q5, a transistor Q6, and a test interface T17, one end of the capacitor C78, one end of the resistor R54, one end of the resistor R57, and the test interface T17 are all connected to pin 18 of the chip U10A, the other end of the capacitor C78, the other end of the resistor R57, the E end of the transistor Q6, and one end of the resistor R56 are all grounded, the other end of the resistor R54 is connected to pin C of the transistor Q5, one end of the resistor R50 and one end of the resistor R53 are all connected to pin B of the transistor Q5, the other end of the resistor R53 is connected to pin C of the transistor Q6, the other end of the resistor R56 and one end of the resistor R55 are all connected to pin B of the transistor Q6, the other end of the chip U10A pin 86 is connected to the resistor Q5.

In one embodiment, as shown in fig. 32, fig. 32 is a block diagram of the host 100 according to an embodiment of the present invention, the host 100 further includes a USB-TYPE module 1000, an external power on/off module 1100, a battery interface module 1400, an extension indication module 1300, a status indication module 1500, a debug button module 1600, a display module 1200, a storage module 1800, and a bluetooth module 1700, the USB-TYPE module 1000, the external power on/off module 1100, the battery interface module 1400, the extension indication module 1300, the status indication module 1500, the debug button module 1600, the display module 1200, the storage module 1800, and the bluetooth module 1700 are all connected to the processor 400, and the second measurement component 300 is connected to the USB-TYPE module 1000.

Specifically, the bluetooth module 1700 is used for the host 100 to perform information transmission with an external device. The USB-TYPE module 1000 uses a USB2.0 protocol for data transmission, charging and connection with the second measurement component 300, and the external connection power on/off module 1100, the battery interface module 1400, the extension indication module 1300, the status indication module 1500, the debug button module 1600, the display module 1200 and the storage module 1800 have the same function corresponding to their names, and are not described herein again.

As shown in fig. 33, fig. 33 is a circuit diagram of a bluetooth module 1700 in an embodiment of the present application, and the bluetooth module 1700 is provided with a chip U11, a resistor R45, a resistor R46, a resistor R47, a capacitor C73, a capacitor C74, a capacitor C75, a transistor Q4, a test interface T14, an interface JP2, and a light emitting diode LED4.

Specifically, one end of a capacitor C73, one end of a resistor R46 and an E end of the triode are all connected to 3V voltage, the other end of the resistor R46 and one end of a resistor R47 are all connected to a B end of the triode Q4, the other end of the resistor R47 is connected to a pin 42 of the chip U10A, the C end of the triode Q4, one end of a capacitor C74, one end of a capacitor C75 and the test interface T14 are all connected to a pin 12 of the chip U11, the other end of the capacitor C73, the other end of the capacitor C74 and the other end of the capacitor C75 are all grounded, a pin 2 of the interface JP2 is connected to a pin 36 of the chip U11, pins 3, 1 and 13 of the interface JO2 are all connected to a pin 35 of the chip U11, one end of the resistor R45 is connected to a pin 32 of the chip U11, the other end of the resistor R45 is connected with the anode of the light-emitting diode LED4, the cathode of the light-emitting diode LED4 is grounded, pins 21 and 22 of the chip U11 are grounded, pin 1 of the chip U11 is connected with pin 26 of the chip U10A, pin 2 of the chip U11 is connected with pin 25 of the chip U10A, pin 3 of the chip U11 is connected with pin 24 of the chip U10A, pin 4 of the chip U11 is connected with pin 23 of the chip U10A, pin 9 of the chip U11 is connected with pin 84 of the chip U10A, pin 10 of the chip U11 is connected with pin 83 of the chip U10A, and pin 11 of the chip U11 is connected with pin 82 of the chip U10A.

As shown in fig. 34, fig. 34 is a circuit diagram of a USB-TYPE module 1000 in an embodiment of the present application, the USB-TYPE module 1000 is provided with an interface USB1, a resistor R15, and a resistor R16, one end of the resistor R15 is connected to the A5 pin of the interface USB1, one end of the resistor R16 is connected to the B5 pin of the interface USB1, the other end of the resistor R16, the B1a12 pin of the interface USB1, the 1 pin of the interface USB1, the 2 pin of the interface USB1, the 3 pin of the interface USB1, and the 4 pin of the interface USB1 are all grounded, the A4B9 pin of the interface USB1 and the B4 A9 pin of the interface USB1 are both connected to the other end of the resistor R59, the A6 pin of the interface USB1 is connected to the 71 pin of the chip U10A, the A7 pin of the interface USB1 is connected to the 70 pin of the chip U10A, the B6 pin of the interface USB1 is connected to the 71 pin of the chip U10A, and the B7 pin of the chip U10A of the interface USB1 is connected to the 71 pin of the chip U10A.

As shown in fig. 35, fig. 35 is a circuit diagram of an external power on/off module 1100 in an embodiment of the present application, where the external power on/off module 1100 is provided with an interface CN1, a pin 1 of the interface CN1 is connected to a pin 13 of a chip U6, a pin 2 of the interface CN1 is connected to a pin 12 of the chip U6, and pins 3 of the interface CN1 and pins 4 of the interface CN1 are both grounded.

As shown in fig. 36, fig. 36 is a circuit diagram of a battery interface module 1400 in an embodiment of the present application, where the battery interface module 1400 is provided with an interface CN2, a pin 1 of the interface CN2 is connected to a pin 13 of a chip U6, a pin 2 of the interface CN2 is connected to a pin 11 of the chip U6, and a pin 3 of the interface CN2 is grounded.

As shown in fig. 37, fig. 37 is a circuit diagram of an extended indication module 1300 in an embodiment of the present application, where the extended indication module 1300 is provided with an interface FPC1, pins 1, 7, and 8 of the interface FPC1 are all grounded, pin 2 of the interface FPC1 is connected to pin 64 of a chip U10A, pin 3 of the interface FPC1 is connected to pin 63 of the chip U10A, pin 4 of the interface FPC1 is connected to pin 69 of the chip U10A, and pin 5 of the interface FPC1 is connected to pin 68 of the chip U10A.

As shown in fig. 38, fig. 38 is a circuit diagram of a status indication module 1500 in an embodiment of the present application, the status indication module 1500 is provided with a resistor R13, a resistor R14, a resistor R72, a light emitting diode B, a light emitting diode G, and a light emitting diode R, one end of the resistor R13 is connected to a negative electrode of the light emitting diode B, the other end of the resistor R13 is connected to a pin 65 of the chip U10A, one end of the resistor R14 is connected to a negative electrode of the light emitting diode G, the other end of the resistor R14 is connected to a pin 68 of the chip U10A, one end of the resistor R72 is connected to a negative electrode of the light emitting diode R, the other end of the resistor R13 is connected to a pin 69 of the chip U10A, and an anode of the light emitting diode B, the anode of the light emitting diode G, and the anode of the light emitting diode R are all connected to a pin 6 of the interface FPC 1.

As shown in fig. 39, fig. 39 is a circuit diagram of the debug button module 1600 in an embodiment of the present application, the debug button module 1600 is provided with a debug button SW1 and a debug button SW2, the 2 nd position of the debug button SW1 is connected to pin 63 of the chip U10A, the 1 st position, the 3 rd position, the 4 th position and the 5 th position of the debug button SW1 are all grounded, the 2 nd position of the debug button SW2 is connected to pin 64 of the chip U10A, and the 1 st position, the 3 rd position, the 4 th position and the 5 th position of the debug button SW2 are all grounded.

As shown in fig. 40, fig. 40 is a circuit diagram of a display module 1200 in an embodiment of the present application, the display module 1200 is provided with an interface Q1, an interface CN9 of types HY2.0-8P, a resistor R17, a resistor R18, a capacitor C19, a capacitor C20, and a transistor Q2, one end of the capacitor C19, one end of the capacitor C20, one end of the resistor R17, 5 pins of the interface QI, 6 pins of the interface QI, 7 pins of the interface QI, and 8 pins of the interface QI are all connected to a test interface T8, the other end of the capacitor C19, the other end of the capacitor C20, an E terminal of the transistor Q2, one end of the capacitor C18, 7 pins of the interface CN9, and 8 pins of the interface CN9 are all grounded, 4 pins of the interface Q1 and the other end of the resistor R17 are all connected to a C terminal of the transistor Q2, one end of the resistor R18 is connected to a B terminal of the transistor Q2, and 1 pin of the interface Q1, 2 pin of the interface CN9, 3 pin of the interface CN9, and the other end of the interface CN9 are all connected to a pin of the interface CN9, and the interface CN9 of the interface CN10 pin of the chip a pin of the interface CN10 pin of the interface CN9 are connected to a chip a pin 5 pin of the interface CN10 pin of the chip.

Specifically, the memory module 1800 is provided with an external memory submodule and an internal memory submodule, which are both connected to the processor 400. The external storage submodule and the internal storage submodule are used for storing data information.

As shown in fig. 41, fig. 41 is a circuit diagram of an external memory sub-module according to an embodiment of the present application, the external memory sub-module includes a chip U3, a resistor R19, a resistor R20, a resistor R21, a resistor R22, and a resistor R23, one end of the resistor R19, one end of the resistor R20, one end of the resistor R21, one end of the resistor R22, one end of the resistor R23, and 8 pins of the chip U3 are all connected to VDD 3V3, the other end of the resistor R19 is connected to pin 1 of the chip U3, the other end of the resistor R20 is connected to pin 2 of the chip U3, the other end of the resistor R21 is connected to pin 7 of the chip U3, the other end of the resistor R22 is connected to pin 6 of the chip U3, the other end of the resistor R23 is connected to pin 5 of the chip U3, pin 4 of the chip U3 is grounded, pin 1 pin of the chip U3 is connected to pin 89 pin of the chip U10A, pin 2 of the chip U3 is connected to pin 90 of the chip U10A, pin 7 of the chip U3 is connected to pin 54 of the chip U10A, and pin 6 pin of the chip U3 is connected to pin 82 of the chip U10A chip U3 a chip.

As shown in fig. 42, fig. 42 is a circuit diagram of an internal storage sub-module in an embodiment of the present application, the internal storage sub-module is provided with a chip U2 and a capacitor C21, one end of the capacitor C21 and a pin 8 of the chip U2 are both connected to VDD 3V3, the other end of the capacitor C21 and a pin 4 of the chip U2 are both grounded, a pin 1 of the chip U2 is connected to a pin 79 of the chip U10A, a pin 2 of the chip U2 is connected to a pin 39 of the chip U10A, a pin 3 of the chip U2 is connected to a pin 40 of the chip U10A, a pin 5 of the chip U2 is connected to a pin 38 of the chip U10A, a pin 6 of the chip U2 is connected to a pin 37 of the chip U10A, and a pin 7 of the chip U2 is connected to a pin 41 of the chip U10A.

In the present application, the parameters of the electronic components included in the circuits of the processor 400 and all modules included in the host 100 are marked in the drawings, and the parameters of the electronic components without marks are corresponding parameters in the drawings, and can be specifically set by those skilled in the art according to actual situations. It should be further noted that, a person in the art may specifically adjust parameters of the electronic component marked in the drawings according to actual situations, and the parameters of the electronic component in the present application are not limited to the parameters shown in the drawings.

In one embodiment, the first measurement component 200 is a pressure band having a length of 3cm to 15cm, and the second measurement component 300 is a stethoscope. The sound signal of adopting the pressure zone that length is 3cm ~ 15cm to measure first target area can promote detection stability and accuracy, adopts the stethoscope to gather the sound signal of certain point of heart position or thorax position promptly second target area can richen the variety of testing result.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. The pulse diagnosis instrument is characterized by comprising a host, at least two first measuring assemblies and at least two second measuring assemblies;

2. The pulse diagnosis instrument according to claim 1, wherein: the host comprises a processor, a conversion module, a voltage management module and an air pressure regulation module, wherein the conversion module, the voltage management module and the air pressure regulation module are all connected with the processor;

3. The pulse diagnosis instrument according to claim 2, wherein the voltage management module comprises a power on/off module, a voltage increasing and decreasing control module, a first voltage decreasing module, a second voltage decreasing module and a first power supply module;

4. The pulse diagnosis instrument according to claim 3, wherein the pulse diagnosis instrument comprises two first measurement assemblies, both of which are connected with the air pressure regulation module.

5. The pulse diagnosis instrument according to claim 4, wherein the air pressure adjusting module comprises a second power supply module, a first air pressure adjusting submodule and a second air pressure adjusting submodule, the first air pressure adjusting submodule is connected with one of the two first measuring assemblies, and the second air pressure adjusting submodule is connected with the other of the two first measuring assemblies.

6. The pulse diagnosis instrument according to claim 5, wherein the first air pressure regulating submodule comprises a first air pressure detecting module, a first driving module, a first air pump module, a first air escape valve module and a first air escape valve fine adjustment module;

7. The pulse diagnosis instrument according to claim 6, wherein the host further comprises a power supply detection module and a voltage acquisition module, and both the power supply detection module and the voltage acquisition module are connected to the processor.

8. The pulse diagnosis instrument according to claim 7, wherein the power supply detection module comprises a first detection sub-module, a second detection sub-module, a third detection sub-module, a fourth detection sub-module, a fifth detection sub-module, a sixth detection sub-module and a seventh detection sub-module.

9. The pulse diagnosis instrument according to claim 8, wherein the host further comprises a USB-TYPE module, an external power on/off module, a battery interface module, an extension indication module, a status indication module, a debug button module, a display module, a storage module, and a bluetooth module, and the USB-TYPE module, the external power on/off module, the battery interface module, the extension indication module, the status indication module, the debug button module, the display module, the storage module, and the bluetooth module are all connected to the processor;

the second measurement component is connected with the USB-TYPE module.

10. The pulse diagnosis instrument according to any one of claims 1 to 9, wherein the first measuring assembly comprises a pressure belt, the length of the pressure belt is 3cm to 15cm;

the second measurement assembly includes a stethoscope.