CN115473426A - Circuit for preventing output crosstalk for rectifier bridge multiplexing - Google Patents

Circuit for preventing output crosstalk for rectifier bridge multiplexing Download PDF

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CN115473426A
CN115473426A CN202210997839.1A CN202210997839A CN115473426A CN 115473426 A CN115473426 A CN 115473426A CN 202210997839 A CN202210997839 A CN 202210997839A CN 115473426 A CN115473426 A CN 115473426A
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output
comparator
pmos tube
selector
pmos
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CN115473426B (en
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郭建平
陈宇棠
罗宇萱
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Sun Yat Sen University
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Sun Yat Sen University
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J50/00—Circuit arrangements or systems for wireless supply or distribution of electric power
    • H02J50/10—Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling
    • H02J50/12—Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling of the resonant type
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0083—Converters characterised by their input or output configuration
    • H02M1/009—Converters characterised by their input or output configuration having two or more independently controlled outputs
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M7/219—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Rectifiers (AREA)

Abstract

The invention discloses a rectifier bridge multiplexing output crosstalk prevention circuit.A crosstalk prevention circuit is arranged on the basis of a rectifier bridge multiplexing circuit, and the conduction of a body diode of a first PMOS (P-channel metal oxide semiconductor) tube is inhibited when the body diode of a transistor of a second output branch is conducted through a self-adaptive body biasing module, so that the output crosstalk problem caused by the conduction and leakage of the body diode of the first PMOS tube when the body diode of the transistor of the second output branch is conducted is solved, and the output voltage is stabilized; the voltage is stored when the second end of the alternating current source outputs low level through the charging and discharging module, when the second end of the alternating current source outputs high level, the first driving input voltage is higher than the voltage output by the second end of the alternating current source through discharging, the phenomenon of mistaken opening of the first PMOS tube does not occur when the body diode of the transistor of the second output branch circuit is conducted, output crosstalk caused by the problem of electric leakage of mistaken opening of the first PMOS tube is solved, and output voltage is further stabilized.

Description

Circuit for preventing output crosstalk for rectifier bridge multiplexing
Technical Field
The invention relates to the field of integrated circuits, in particular to a circuit for preventing output crosstalk of rectifier bridge multiplexing.
Background
Compared with wired energy transmission, the wireless energy transmission system has the characteristics of using boundaries, supplying power one to many and the like, and is more and more frequently used in the fields of biological medical treatment and the like. In recent years, compared with a conventional inductive wireless energy transfer system, a resonant wireless energy transfer system has higher flexibility and practicability. The working principle of the resonant wireless energy transfer system is as follows: the method comprises the following steps that firstly, a wireless energy transmitting circuit drives a transmitting resonant circuit to generate alternating-current resonant voltage through a power amplifier; secondly, alternating current voltage on the transmitting resonant circuit is coupled to the receiving resonant circuit; and thirdly, the energy receiving circuit (receiving end circuit) converts the alternating voltage on the receiving resonant circuit into direct current output voltage to provide stable energy supply for subsequent circuit modules.
Due to the rapid development of electronic products, the types and the number of power sources required by the electronic products are increasing. In a receiving end circuit of a series-series resonant wireless energy transmission system, a rectifier bridge multiplexing circuit is adopted, and a single rectifier bridge is utilized to realize the conversion from single alternating current input to a plurality of direct current outputs so as to meet the requirements of current electronic products and greatly reduce the complexity, power consumption and area of the circuit. However, the multiplexing of the rectifier bridge causes the problem of output crosstalk between output voltages, which in extreme cases even causes the lower output voltage to be unable to stabilize voltage, thereby causing the whole system to be unable to work normally.
Disclosure of Invention
In order to solve the above technical problem, an embodiment of the present invention provides a circuit for preventing output crosstalk in a multiplexing manner for a rectifier bridge.
The technical scheme adopted by the embodiment of the invention is as follows:
a kind of bridge rectifier multiplexes and defends the circuit of the output crosstalk, apply to the receiving end circuit of the wireless energy transmission system of series-series resonance type, including:
the rectifier bridge multiplexing circuit comprises an alternating current source, a first output branch and a second output branch, wherein the input ends of the first output branch and the second output branch are connected with the second end of the alternating current source, the output end of the first output branch is used for outputting a first power supply, the output end of the second output branch is used for outputting a second power supply, the first power supply is smaller than the second power supply, the first output branch comprises a first PMOS (P-channel metal oxide semiconductor) tube and a first driver, the output end of the first driver is connected with the grid electrode of the first PMOS tube, the drain electrode of the first PMOS tube is connected with the second end of the alternating current source, the source electrode of the first PMOS tube is the output end of the first output branch, and the alternating current source is an equivalent input source of a receiving end circuit of a series-series resonant wireless energy transmission system which inputs the rectifier bridge multiplexing circuit;
the output crosstalk prevention circuit comprises an adaptive body biasing module and a charge and discharge module, wherein the adaptive body biasing module is used for inhibiting the conduction of a body diode of a first PMOS (P-channel metal oxide semiconductor) tube when the body diode of a transistor of the second output branch is conducted, the charge and discharge module is used for storing voltage when a second end of the alternating current source outputs low level, and the charge and discharge module is used for enabling the input voltage of the first driver to be higher than the voltage output by the second end of the alternating current source through discharging when the second end of the alternating current source outputs high level.
As an optional implementation manner, the first output branch further includes a first comparator, a first selector, a first capacitor, and a first resistor;
the drain electrode of the first PMOS tube is connected with the inverting input end of the first comparator, the output end of the first comparator is connected with the input end of the first selector, the output end of the first selector is connected with the first input end of the first driver, the source electrode of the first PMOS tube is connected with the positive phase input end of the first comparator, the positive phase input end of the first comparator is connected with the first end of the first capacitor, the first end of the first capacitor is connected with the first end of the first resistor, and the second end of the first capacitor and the second end of the first resistor are respectively grounded.
As an optional implementation manner, the second output branch includes a second PMOS transistor, a second driver, a second selector, a second comparator, a second capacitor, and a second resistor;
the second end of the alternating current source is connected with the drain electrode of the second PMOS tube, the drain electrode of the second PMOS tube is connected with the inverting input end of the second comparator, the output end of the second comparator is connected with the input end of the second selector, the output end of the second selector is connected with the second driving input end, the second driving output end is connected with the grid electrode of the second PMOS tube, the source electrode of the second PMOS tube is connected with the positive phase input end of the second comparator, the positive phase input end of the second comparator is connected with the first end of the second capacitor, the first end of the second capacitor is connected with the first end of the second resistor, the second end of the second capacitor and the second end of the second resistor are respectively grounded, and the source electrode of the second PMOS tube is connected with the output end of the second output branch circuit.
As an optional implementation manner, the rectifier bridge multiplexing circuit further includes a third PMOS transistor, a third driver, a third selector, a third comparator, a first NMOS transistor, a fourth driver, a fourth selector, a fourth comparator, a second NMOS transistor, a fifth driver, a fifth selector, a fifth comparator, a sixth comparator, and a seventh comparator;
a first end of the alternating current source is connected with a drain electrode of the third PMOS transistor, a drain electrode of the third PMOS transistor is connected with an inverting input end of the third comparator, an output end of the third comparator is connected with an input end of the third selector, an output end of the third selector is connected with an input end of the third driver, an output end of the third driver is connected with a gate electrode of the third PMOS transistor, a source electrode of the third PMOS transistor is connected with a positive-phase input end of the third comparator, and a positive-phase input end of the third comparator is connected with a source electrode of the second PMOS transistor;
a first end of the alternating current source is connected with a drain electrode of the first NMOS transistor, a drain electrode of the first NMOS transistor is connected with an inverting input terminal of the fourth comparator, an output terminal of the fourth comparator is connected with an input terminal of the fourth selector, an output terminal of the fourth selector is connected with an input terminal of the fourth driver, an output terminal of the fourth driver is connected with a gate electrode of the first NMOS transistor, a source electrode of the first NMOS transistor is connected with a positive-phase input terminal of the fourth comparator, a positive-phase input terminal of the fourth comparator is connected with a source electrode of the second NMOS transistor, a source electrode of the second NMOS transistor is connected with a positive-phase input terminal of the fifth comparator, a positive-phase input terminal of the fifth comparator is grounded, an output terminal of the fifth comparator is connected with an input terminal of the fifth selector, an output terminal of the fifth selector is connected with an input terminal of the fifth driver, an output terminal of the fifth driver is connected with a gate electrode of the second NMOS transistor, a drain electrode of the second NMOS transistor is connected with an inverting input terminal of the fifth comparator, and an inverting input terminal of the fifth comparator is connected with a drain electrode of the PMOS transistor;
a first reference voltage is input to a positive phase input end of the sixth comparator, an inverted input end of the sixth comparator is connected with the source electrode of the first PMOS transistor, an output end of the sixth comparator is connected with an input end of the first selector, and an output end of the sixth comparator is connected with an input end of the fifth selector;
a second reference voltage is input to a positive phase input end of the seventh comparator, an inverted input end of the seventh comparator is connected to a source electrode of the second PMOS transistor, an output end of the seventh comparator is connected to an input end of the second selector, an output end of the sixth comparator is connected to an input end of the third selector, and an output end of the sixth comparator is connected to an input end of the fourth selector.
As an optional implementation, the adaptive body bias module includes a fourth PMOS transistor and a fifth PMOS transistor;
the source electrode of the fourth PMOS tube is connected with the source electrode of the first PMOS tube, the source electrode of the first PMOS tube is connected with the grid electrode of the fifth PMOS tube, the source electrode of the fifth PMOS tube is connected with the grid electrode of the fourth PMOS tube, the grid electrode of the fourth PMOS tube is connected with the drain electrode of the first PMOS tube, the substrate of the first PMOS tube is connected with the drain electrode of the fourth PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the fifth PMOS tube.
As an optional implementation manner, the charge and discharge module includes a third capacitor;
the first end of the third capacitor is connected with the second input end of the first driver, and the second end of the third capacitor is connected with the drain electrode of the first PMOS tube;
the third capacitor stores voltage when the second end of the alternating current source outputs low level, and enables the input voltage of the first driver to be higher than the voltage output by the second end of the alternating current source through discharging when the second end of the alternating current source outputs high level.
As an optional implementation manner, the charge and discharge module further includes a unidirectional conducting component;
and the source electrode of the second PMOS tube is connected with the first end of the third capacitor through the one-way conduction assembly.
As an alternative embodiment, the unidirectional conducting component comprises a diode;
the anode of the diode is connected with the source electrode of the second PMOS tube, and the cathode of the diode is connected with the first end of the third capacitor.
According to the rectifier bridge multiplexing output crosstalk prevention circuit, the output crosstalk prevention circuit is arranged on the basis of the rectifier bridge multiplexing circuit, and the body diode conduction of the first PMOS tube is restrained when the body diode of the transistor of the second output branch is conducted through the self-adaptive body biasing module of the output crosstalk prevention circuit, so that the output crosstalk problem caused by the conduction and leakage of the body diode of the first PMOS tube when the body diode of the transistor of the second output branch is conducted is solved, and the output voltage is stabilized; the charging and discharging module of the output crosstalk prevention circuit stores voltage when the second end of the alternating current source outputs low level, the first driving input voltage is higher than the voltage output by the second end of the alternating current source through discharging when the second end of the alternating current source outputs high level, the phenomenon of mistaken opening of a first PMOS (P-channel metal oxide semiconductor) tube does not occur when a body diode of a transistor of a second output branch circuit is conducted, output crosstalk caused by the problem of electric leakage of mistaken opening of the first PMOS tube is solved, and output voltage is further stabilized.
Drawings
Fig. 1 is a schematic circuit connection diagram of a rectifier bridge multiplexing output crosstalk prevention circuit according to an embodiment of the present invention;
fig. 2 is a schematic diagram illustrating an output crosstalk principle of a rectifier bridge multiplexing circuit according to an embodiment of the present invention;
fig. 3 is a waveform diagram showing a functional simulation of the rectifier bridge multiplexing output crosstalk prevention circuit according to the embodiment of the present invention.
Reference numerals are as follows: I.C. A AC An alternating current source; CMP (chemical mechanical polishing) 1 The first comparator; CMP (chemical mechanical polishing) 2 A second comparator; CMP (chemical mechanical polishing) 3 A third comparator; CMP (chemical mechanical polishing) 4 A fourth comparator; CMP (chemical mechanical polishing) 5 A fifth comparator; CMP (chemical mechanical polishing) 6 A sixth comparator; CMP (chemical mechanical polishing) 7 A seventh comparator; b is 1 The first drive; b is 2 A second drive; b 3 And a third drive; b is 4 The fourth drive; b is 5 The fifth drive; mux 1 A first selector; mux 2 A second selector; mux 3 A third selector; mux 4 A fourth selector; mux 5 A fifth selector; m is a group of P1 The first PMOS tube; m is a group of P2 A second PMOS tube; m is a group of P3 The third PMOS tube; m PA A fourth PMOS tube; m is a group of PB A fifth PMOS tube; m N1 The first NMOS tube; m N2 A second NMOS tube; c 1 A first capacitor; c 2 A second capacitor; c 3 A third capacitor; r is 1 A first resistor; r 2 A second resistor; d 1 A diode; v REFL A first reference voltage; v REFH A second reference voltage; 101. an adaptive body bias module; 102. a charge-discharge module.
Detailed Description
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first," "second," "third," and "fourth," etc. in the description and claims of this application and in the accompanying drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein may be combined with other embodiments.
In a receiving end circuit of a series-series resonant wireless energy transmission system, a rectifier bridge multiplexing circuit is adopted, and a single rectifier bridge is utilized to realize conversion from single alternating current input to multiple direct current outputs so as to meet the requirements of current electronic products, and the complexity, power consumption and area of the circuit are greatly reduced. However, the multiplexing of the rectifier bridge causes the problem of output crosstalk between output voltages, which in extreme cases even causes the lower output voltage to be unable to stabilize voltage, thereby causing the whole system to be unable to work normally. Therefore, the embodiment of the invention provides a rectifier bridge multiplexing output crosstalk prevention circuit, wherein the output crosstalk prevention circuit is arranged on the basis of the rectifier bridge multiplexing circuit, and the self-adaptive body bias module of the output crosstalk prevention circuit inhibits the conduction of the body diode of the first PMOS tube when the body diode of the transistor of the second output branch is conducted, so that the output crosstalk problem caused by the conduction and leakage of the body diode of the first PMOS tube when the body diode of the transistor of the second output branch is conducted is solved, and the output voltage is stabilized; the charging and discharging module of the anti-output crosstalk circuit stores voltage when the second end of the alternating current source outputs low level, the first driving input voltage is higher than the voltage output by the second end of the alternating current source through discharging when the second end of the alternating current source outputs high level, the phenomenon of mistaken opening of the first PMOS tube is avoided when the body diode of the transistor of the second output branch circuit is conducted, output crosstalk caused by the problem of electric leakage caused by mistaken opening of the first PMOS tube is solved, and output voltage is further stabilized.
As shown in fig. 1, an embodiment of the present invention provides a circuit for preventing output crosstalk in a multiplexing rectifier bridge, which is applied to a receiving end circuit of a series-series resonant wireless energy transmission system, and includes:
the rectifier bridge comprises an AC current source I AC The alternating current power supply I comprises a first output branch circuit and a second output branch circuit, wherein the input ends of the first output branch circuit and the second output branch circuit are connected with the alternating current power supply I AC The second end of the first output branch is connected, the output end of the first output branch is used for outputting a first power supply, the output end of the second output branch is used for outputting a second power supply, the first power supply is smaller than the second power supply, and the first output branch comprises a first PMOS (P-channel metal oxide semiconductor) tube M P1 And a first drive B 1 The first drive B 1 And the output end of the first PMOS tube M P1 The grid electrode of the first PMOS tube M is connected with the grid electrode of the second PMOS tube M P1 And the alternating current source I AC The second end of the first PMOS tube M is connected with the first end of the second PMOS tube M P1 The source electrode of the first output branch circuit is the output end of the first output branch circuit, and the alternating current source I AC Inputting an equivalent input source of the rectifier bridge multiplexing circuit into a receiving end circuit of the series-series resonant wireless energy transmission system;
the output crosstalk prevention circuit comprises an adaptive body bias module 101 and a charging and discharging module 102, wherein the adaptive body bias module 101 is used for inhibiting the first PMOS transistor M when a body diode of a transistor of the second output branch is conducted P1 Body twoThe pole tube is conducted, and the charge and discharge module 102 is used for supplying the alternating current I AC The charging and discharging module 102 is used for storing voltage when the second end of the alternating current source I outputs low level AC When the second terminal of (B) outputs a high level, the first driver (B) is driven by discharging 1 Input voltage V of BOOST Higher than the AC current source I AC Voltage V output from the second terminal IN2 。
Wherein the first power supply represents the output voltage V of the first output branch OL The second power supply represents the output voltage V of the second output branch OH 。
Referring to fig. 2, the output crosstalk reasons of the rectifier bridge multiplexing circuit include:
1) Since the first PMOS tube M P1 Body diode D of P1 And a second PMOS transistor M P2 Body diode D of P2 And a second PMOS transistor M P2 When the second PMOS transistor M delays the gate control signal P2 Body diode D of P2 When conducting, the first PMOS tube M P1 Body diode D of P1 A forward voltage of V at both ends OH +0.7-V OL So that the first PMOS transistor M P1 Body diode D of P1 And is also turned on. Because the first PMOS tube M P1 Body diode D of P1 The differential pressure at two ends is higher than that of the second PMOS tube M P2 Body diode D of P2 Large voltage difference between two ends, AC current source I AC The output current flows to the output end of the first output branch circuit, so that the voltage V output by the output end of the first output branch circuit OL Failure of voltage stabilization;
2) When the second PMOS transistor M P2 Body diode D of P2 When conducting, the first PMOS transistor M P1 The source-drain exchange will occur, at this time, the first PMOS tube M P1 Has a source gate voltage of V OH +0.7-V OH The first PMOS transistor M P1 At the conducting edge. At the moment, the first PMOS tube M P1 Source-drain voltage of V OH -V OL Far greater than that of the second PMOS tube M P2 Source-drain voltage of, thus, the alternating current source I AC The output current flows to the output end of the first output branch circuit, so that the first outputVoltage V output by branch output terminal OL The voltage stabilization fails.
Based on the reason for the output crosstalk of the rectifier bridge multiplexing circuit, the embodiment of the invention arranges the output crosstalk prevention circuit on the basis of the rectifier bridge multiplexing circuit, and the self-adaptive body bias module 101 of the output crosstalk prevention circuit inhibits the first PMOS transistor M when the body diode of the transistor of the second output branch circuit is conducted P1 The body diode of the second output branch is conducted, so that the problem that the body diode of the transistor of the second output branch is conducted when the first PMOS transistor M is conducted is solved P1 The body diode is conducted and leakage is caused to cause the output crosstalk problem, so that the output voltage is stabilized; alternating current source I through charging and discharging module 102 of output crosstalk prevention circuit AC The second terminal of (1) stores the voltage when outputting a low level, in an alternating current source I AC When the second terminal of (2) outputs a high level, the first drive B is enabled by discharging 1 Input voltage V of BOOST Higher than AC current source I AC Voltage V output from the second terminal IN2 So that the first PMOS transistor M is conducted when the body diode of the transistor of the second output branch circuit is conducted P1 The phenomenon of false opening does not occur, thereby solving the problem of the first PMOS tube M P1 The output crosstalk caused by the leakage problem of the false turn-on further stabilizes the output voltage.
Referring to fig. 1 (a), in one embodiment of the present invention, the first output branch further comprises a first comparator CMP 1 First selector Mux 1 A first capacitor C 1 And a first resistor R 1 ；
The first PMOS tube MP 1 And the first comparator CMP 1 Is connected to the inverting input terminal of the first comparator CMP 1 And said first selector Mux 1 Is connected to the input of the first selector Mux 1 And the first driver B 1 The first input end of the first PMOS tube MP is connected with the first input end of the second PMOS tube MP 1 And the first comparator CMP 1 Is connected to the positive input terminal of the first comparator CMP 1 Is connected with the first capacitor C 1 Is connected to the first terminal of the first capacitor C 1 First end of and the firstA first end of the resistor R1 is connected with the first capacitor C 1 And the first resistor R 1 Respectively, to ground.
Referring to fig. 1 (a), as an alternative embodiment, the second output branch includes a second PMOS transistor M P2 And a second drive B 2 A second selector Mux 2 A second comparator CMP 2 A second capacitor C 2 And a second resistor R 2 ；
The alternating current source I AC Second end of the second PMOS transistor M P2 Is connected with the drain electrode of the second PMOS tube M P2 And the second comparator CMP 2 Is connected to the inverting input terminal of the second comparator CMP 2 And the second selector Mux 2 Is connected to the input of the second selector Mux 2 And the second drive B 2 Is connected to the input of the second drive B 2 And the output end of the second PMOS tube M P2 The grid electrode of the second PMOS tube M is connected with the grid electrode of the first PMOS tube M P2 And the second comparator CMP 2 Is connected to the non-inverting input terminal of the second comparator CMP 2 And the positive phase input end of the second capacitor C 2 Is connected to the first terminal of the second capacitor C 2 First terminal of and the second resistor R 2 Is connected to the first terminal of the second capacitor C 2 And the second terminal of (2) and the second resistor R 2 The second ends of the PMOS tubes M are respectively grounded, and the second PMOS tube M P2 The source of the first output branch and the output end of the second output branch.
Wherein the first resistor R 1 And a second resistor R 2 Is a load resistor. When the second resistor R is used 2 For the most heavy load, the first resistor R 1 When the load is the lightest load, the rectifier bridge multiplexing circuit is in the most extreme condition.
It can be understood that the function of the output crosstalk prevention circuit of the embodiment of the present invention is not affected by the first resistor R 1 Load condition and second resistance R 2 A limitation of the load condition.
With continued reference to FIG. 1 (a), as an alternative embodiment, the rectifier bridgeThe multiplexing circuit also comprises a third PMOS tube M P3 And the third drive B 3 A third selector Mux 3 A third comparator CMP 3 A first NMOS transistor M N1 Fourth drive B 4 And a fourth selector Mux 4 The fourth comparator CMP 4 A second NMOS transistor M N2 The fifth drive B 5 Fifth selector Mux 5 The fifth comparator CMP 5 A sixth comparator CMP 6 And a seventh comparator CMP 7 ；
The alternating current source I AC First end of the PMOS transistor M and the third PMOS transistor M P3 Is connected with the drain electrode of the third PMOS tube M P3 And the third comparator CMP 3 Is connected to the inverting input terminal of the third comparator CMP 3 And the third selector Mux 3 Is connected to the input of the third selector Mux 3 And the third driver B 3 Is connected to the input of the third drive B 3 And the output end of the third PMOS tube M P3 Is connected with the grid electrode of the third PMOS tube M P3 And the third comparator CMP 3 Is connected to the positive input terminal of the third comparator CMP 3 The positive phase input end of the second PMOS tube M P2 Is connected to the source of (a);
the alternating current source I AC First end of (D) and the first NMOS tube M N1 The drain electrode of the first NMOS tube M is connected with the drain electrode of the second NMOS tube M N1 And the fourth comparator CMP 4 Is connected to the inverting input terminal of the fourth comparator CMP 4 And the fourth selector Mux 4 Is connected to the input terminal of the fourth selector Mux 4 And the fourth drive B 4 Is connected to the input of the fourth drive B 4 And the output end of the first NMOS tube M N1 Is connected with the grid of the first NMOS tube M N1 And the fourth comparator CMP 4 Is connected to the positive input terminal of the fourth comparator CMP 4 The positive phase input end of the first NMOS tube M and the second NMOS tube M N2 Is connected with the source electrode of the second NMOS tube M N2 Source electrode of andfifth comparator CMP 5 Is connected to the positive input terminal of the fifth comparator CMP 5 Is grounded, the fifth comparator CMP 5 And the fifth selector Mux 5 Is connected to the input of the fifth selector Mux 5 And the output terminal of (B) and the fifth driver (B) 5 Is connected to the input of the fifth drive B 5 And the output end of the second NMOS tube M N2 Is connected with the grid of the first NMOS tube M N2 And the fifth comparator CMP 5 Is connected to the inverting input terminal of the fifth comparator CMP 5 And the inverting input end of the first PMOS tube M P1 Is connected with the drain electrode of the transistor;
the sixth comparator CMP 6 The positive phase input terminal of the first voltage converter inputs a first reference voltage V REFL The sixth comparator CMP 6 And the inverting input end of the first PMOS tube M P1 The sixth comparator CMP 6 And said first selector Mux 1 Is connected to the input of the sixth comparator CMP 6 And the fifth selector Mux 5 The input ends of the two-way valve are connected;
the seventh comparator CMP 7 The positive phase input end of the first voltage converter inputs a second reference voltage V REFH The seventh comparator CMP 7 And the inverting input end of the second PMOS tube M P2 The source connection of the seventh comparator CMP 7 And the second selector Mux 2 Is connected to the input of the sixth comparator CMP 6 And the third selector Mux 3 Is connected to the input of the sixth comparator CMP 6 And the fourth selector Mux 4 Is connected to the input terminal of the controller.
Referring to fig. 1 (b), as an alternative embodiment, the adaptive body bias module 101 includes a fourth PMOS transistor M PA And a fifth PMOS transistor M PB ；
The fourth PMOS tube M PA Source electrode of and the first PMOS tube M P1 The source electrode of the first PMOS tube M is connected P1 Source electrode of and the fifth PMOS tubeM PB Is connected with the grid of the fifth PMOS tube M PB Source electrode of and the fourth PMOS tube M PA The grid electrode of the fourth PMOS tube M is connected PA Grid of and the first PMOS tube M P1 Is connected with the drain electrode of the first PMOS tube M P1 And the fourth PMOS tube M PA Is connected with the drain electrode of the fourth PMOS tube M PA Drain electrode of and the fifth PMOS tube M PB Is connected to the drain of (1).
With continued reference to fig. 1 (b), as an alternative embodiment, the charging and discharging module 102 includes a third capacitor C 3 ；
The third capacitor C 3 First end of and the first drive B 1 Is connected to the third input terminal of the first capacitor C, the third capacitor C 3 Second end of the PMOS transistor M and the first PMOS transistor M P1 Is connected with the drain electrode of the transistor;
the third capacitor C 3 At the AC current source I AC Is at a low level, stores a voltage when the second terminal of the AC power supply I outputs a low level AC When the second terminal of (B) outputs a high level, the first driver (B) is driven by discharging 1 Input voltage V of BOOST Higher than the AC current source I AC Voltage V output from the second terminal IN2 。
In particular, when the alternating current source I AC When the second terminal of (2) outputs a high level, the third capacitor C 3 First drive B 1 Input voltage V of BOOST Raised to be greater than an alternating current source I AC Voltage V output from the second terminal IN2 So that the first PMOS transistor M P1 The source-gate voltage of (1) is less than zero, so that the first PMOS tube M P1 The phenomenon of false opening can not occur, and then the problem of the first PMOS tube M is solved P1 And the problem of output crosstalk caused by false turn-on.
It is understood that, in the embodiment of the present invention, when the first PMOS transistor M is used P1 In normal operation, the gate voltage is zero, so the first driver B 1 Input voltage V of BOOST The lifting of the transistor does not cause the first PMOS transistor M P1 The on-resistance of the first PMOS transistor M is increased and maintained P1 Small conduction voltage drop, no influence on series-series connectionConversion efficiency of a resonant wireless energy transmission system.
As an optional implementation manner, the charge and discharge module 102 further includes a unidirectional conducting component;
the second PMOS tube M P2 Through the unidirectional conducting component and the third capacitor C 3 Is connected.
Wherein, in the embodiment of the present invention, the unidirectional conducting component comprises a diode D 1 ；
The diode D 1 And the positive electrode of the second PMOS tube M P2 The source of the diode D is connected 1 And the third capacitor C 3 Is connected to the first end of the first housing.
FIG. 3 shows a functional simulation waveform diagram of the rectifier bridge multiplexing output crosstalk prevention circuit according to the embodiment of the present invention, where the simulation condition is the first resistor R 1 For the lightest load, the second resistor R 2 The load is the heaviest, namely, the receiving end circuit of the series-series resonant wireless energy transmission system is in the most extreme condition. As can be seen from fig. 3, the output crosstalk prevention circuit for multiplexing a rectifier bridge according to the embodiment of the present invention not only solves the problem of the first PMOS transistor M through the adaptive body bias module 101 P1 The body diode conducts output crosstalk caused by leakage, and the first drive B is also lifted 1 Input voltage V of BOOST Solves the problem of a first PMOS tube M P1 Output crosstalk caused by false turn-on. As shown in FIG. 3, the simulation result shows that the first PMOS transistor M P1 The source-drain current is obviously reduced to the level which does not influence the output voltage stabilization, and the third capacitor C 3 After a charging period, the output voltage V of the first output branch OL The voltage is in a descending trend, and the voltage stabilization output is successfully realized.
While the preferred embodiments of the present invention have been illustrated and described, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (8)

1. A kind of bridge rectifier multiplexes and defends the circuit of the output crosstalk, characterized by, apply to the receiving end circuit of the wireless energy transmission system of series-series resonance type, including:
the rectifier bridge multiplexing circuit comprises an alternating current source, a first output branch and a second output branch, wherein the input ends of the first output branch and the second output branch are connected with the second end of the alternating current source, the output end of the first output branch is used for outputting a first power supply, the output end of the second output branch is used for outputting a second power supply, the first power supply is smaller than the second power supply, the first output branch comprises a first PMOS (P-channel metal oxide semiconductor) tube and a first driver, the output end of the first driver is connected with the grid electrode of the first PMOS tube, the drain electrode of the first PMOS tube is connected with the second end of the alternating current source, the source electrode of the first PMOS tube is the output end of the first output branch, and the alternating current source is an equivalent input source of a receiving end circuit of a series-series resonant wireless energy transmission system which inputs the rectifier bridge multiplexing circuit;
the output crosstalk prevention circuit comprises an adaptive body biasing module and a charge and discharge module, wherein the adaptive body biasing module is used for inhibiting the conduction of a body diode of a first PMOS (P-channel metal oxide semiconductor) tube when the body diode of a transistor of the second output branch is conducted, the charge and discharge module is used for storing voltage when a second end of the alternating current source outputs low level, and the charge and discharge module is used for enabling the input voltage of the first driver to be higher than the voltage output by the second end of the alternating current source through discharging when the second end of the alternating current source outputs high level.
2. The circuit of claim 1, wherein the first output branch further comprises a first comparator, a first selector, a first capacitor, and a first resistor;
the drain electrode of the first PMOS tube is connected with the inverting input end of the first comparator, the output end of the first comparator is connected with the input end of the first selector, the output end of the first selector is connected with the first input end of the first drive, the source electrode of the first PMOS tube is connected with the positive input end of the first comparator, the positive input end of the first comparator is connected with the first end of the first capacitor, the first end of the first capacitor is connected with the first end of the first resistor, and the second end of the first capacitor and the second end of the first resistor are respectively grounded.
3. The circuit of claim 2, wherein the second output branch comprises a second PMOS transistor, a second driver, a second selector, a second comparator, a second capacitor, and a second resistor;
the second end of the alternating current source is connected with the drain electrode of the second PMOS tube, the drain electrode of the second PMOS tube is connected with the inverting input end of the second comparator, the output end of the second comparator is connected with the input end of the second selector, the output end of the second selector is connected with the second driving input end, the second driving output end is connected with the grid electrode of the second PMOS tube, the source electrode of the second PMOS tube is connected with the positive phase input end of the second comparator, the positive phase input end of the second comparator is connected with the first end of the second capacitor, the first end of the second capacitor is connected with the first end of the second resistor, the second end of the second capacitor and the second end of the second resistor are respectively grounded, and the source electrode of the second PMOS tube is connected with the output end of the second output branch circuit.
4. The circuit of claim 3, wherein the circuit further comprises a third PMOS transistor, a third driver, a third selector, a third comparator, a first NMOS transistor, a fourth driver, a fourth selector, a fourth comparator, a second NMOS transistor, a fifth driver, a fifth selector, a fifth comparator, a sixth comparator, and a seventh comparator;
a first end of the alternating current source is connected with a drain electrode of the third PMOS transistor, a drain electrode of the third PMOS transistor is connected with an inverting input end of the third comparator, an output end of the third comparator is connected with an input end of the third selector, an output end of the third selector is connected with an input end of the third driver, an output end of the third driver is connected with a gate electrode of the third PMOS transistor, a source electrode of the third PMOS transistor is connected with a positive-phase input end of the third comparator, and a positive-phase input end of the third comparator is connected with a source electrode of the second PMOS transistor;
a first end of the alternating current source is connected with a drain electrode of the first NMOS transistor, a drain electrode of the first NMOS transistor is connected with an inverting input terminal of the fourth comparator, an output terminal of the fourth comparator is connected with an input terminal of the fourth selector, an output terminal of the fourth selector is connected with an input terminal of the fourth driver, an output terminal of the fourth driver is connected with a gate electrode of the first NMOS transistor, a source electrode of the first NMOS transistor is connected with a positive-phase input terminal of the fourth comparator, a positive-phase input terminal of the fourth comparator is connected with a source electrode of the second NMOS transistor, a source electrode of the second NMOS transistor is connected with a positive-phase input terminal of the fifth comparator, a positive-phase input terminal of the fifth comparator is grounded, an output terminal of the fifth comparator is connected with an input terminal of the fifth selector, an output terminal of the fifth selector is connected with an input terminal of the fifth driver, an output terminal of the fifth driver is connected with a gate electrode of the second NMOS transistor, a drain electrode of the second NMOS transistor is connected with an inverting input terminal of the fifth comparator, and an inverting input terminal of the fifth comparator is connected with a drain electrode of the PMOS transistor;
a positive phase input end of the sixth comparator inputs a first reference voltage, an inverted phase input end of the sixth comparator is connected with a source electrode of the first PMOS tube, an output end of the sixth comparator is connected with an input end of the first selector, and an output end of the sixth comparator is connected with an input end of the fifth selector;
a second reference voltage is input to a positive phase input end of the seventh comparator, an inverted input end of the seventh comparator is connected to a source electrode of the second PMOS transistor, an output end of the seventh comparator is connected to an input end of the second selector, an output end of the sixth comparator is connected to an input end of the third selector, and an output end of the sixth comparator is connected to an input end of the fourth selector.
5. The circuit of claim 4, wherein the adaptive body bias module comprises a fourth PMOS transistor and a fifth PMOS transistor;
the source electrode of the fourth PMOS tube is connected with the source electrode of the first PMOS tube, the source electrode of the first PMOS tube is connected with the grid electrode of the fifth PMOS tube, the source electrode of the fifth PMOS tube is connected with the grid electrode of the fourth PMOS tube, the grid electrode of the fourth PMOS tube is connected with the drain electrode of the first PMOS tube, the substrate of the first PMOS tube is connected with the drain electrode of the fourth PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the fifth PMOS tube.
6. The circuit of claim 5, wherein the charge/discharge module comprises a third capacitor;
the first end of the third capacitor is connected with the second input end of the first driver, and the second end of the third capacitor is connected with the drain electrode of the first PMOS tube;
the third capacitor stores voltage when the second end of the alternating current source outputs low level, and enables the input voltage of the first driver to be higher than the voltage output by the second end of the alternating current source through discharging when the second end of the alternating current source outputs high level.
7. The circuit of claim 6, wherein the charge-discharge module further comprises a unidirectional conducting element;
and the source electrode of the second PMOS tube is connected with the first end of the third capacitor through the one-way conduction assembly.
8. The circuit of claim 7, wherein the unidirectional conducting component comprises a diode;
the anode of the diode is connected with the source electrode of the second PMOS tube, and the cathode of the diode is connected with the first end of the third capacitor.
CN202210997839.1A 2022-08-19 2022-08-19 Output crosstalk prevention circuit for rectifier bridge multiplexing Active CN115473426B (en)

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