CN115472655A - Display panel, preparation method thereof and display device - Google Patents

Abstract

A display panel, a preparation method thereof and a display device are provided. The display panel comprises an array substrate, an auxiliary electrode layer arranged in the array substrate, a pixel limiting layer arranged on the array substrate, an undercut structure, a second electrode layer extending into the undercut structure and an encapsulation layer covering the second electrode layer and an exposed surface in the undercut structure. The undercut structure includes a second groove and a blocking layer. The second groove penetrates through the pixel defining layer and part of the array substrate to one surface of the auxiliary electrode layer. The shielding layer is arranged on the pixel electrode layer and shields part of the notch of the second groove. The shielding layer and the orthographic projection part of the second groove on the array substrate are overlapped, and the width of the overlapped part is one third to one half of the depth of the second groove.

Description

Display panel, preparation method thereof and display device

Technical Field

The invention relates to the field of display equipment, in particular to a display panel, a preparation method thereof and a display device.

Background

Organic Light-Emitting diodes (OLEDs) are popular among people and developers because of their advantages of self-luminescence, high contrast, wide color gamut, and low power consumption. The productivity of OLED panels, especially flexible OLED panels, is surplus, and the penetration of flexible OLEDs with smartphones to medium-sized or even larger sizes is a necessity for market development.

Compared with the small-size OLED, the medium-size OLED has a larger panel, and if the cathode of the medium-size OLED is electrically connected with the lower layer connecting wire only through the connecting via hole of the frame region, the internal impedance of the panel is increased, so that the display brightness distribution is not uniform. Designing the auxiliary electrodes on the panel is an effective way to reduce the in-plane impedance. However, the undercut structure formed by the current large-sized auxiliary electrode is not favorable for the generation of a Thin Film Encapsulation (TFE) layer, and the TFE Encapsulation layer is prone to crack at the undercut structure, so that water and oxygen cannot be well isolated, and the Encapsulation effect is poor. Therefore, the OLED panel is often further required to be packaged with glass, but the flexible OLED panel is affected by the glass packaging, so that the reliability of the product is poor, and the OLED panel does not have mass production.

Disclosure of Invention

The invention aims to provide a display panel, a preparation method thereof and a display device, and aims to solve the technical problem that an undercut structure in an existing large-size OLED panel is not beneficial to generation of a thin film encapsulation layer.

In order to achieve the above object, the present invention provides a display panel, which includes an array substrate, an auxiliary electrode layer, a first electrode layer, a pixel electrode layer, a first groove, an undercut structure, a light-emitting functional layer, a second electrode layer, and an encapsulation layer.

The auxiliary electrode layer is arranged in the array substrate. The first electrode layer is arranged on the array substrate and is electrically connected with the array substrate. The pixel limiting layer is arranged on the array substrate and covers the first electrode layer. The first groove penetrates through the pixel defining layer to a surface of the first electrode layer. The undercut structure is disposed in the pixel defining layer and the array substrate and corresponds to the auxiliary electrode layer. The light emitting function layer is arranged in the first groove and extends into the undercut structure from the first groove. The second electrode layer is arranged on the light-emitting functional layer and extends from the light-emitting functional layer to cover the auxiliary electrode layer in the undercut structure. The packaging layer is arranged on the second electrode layer, and the exposed surface in the undercut structure is formed.

Wherein the undercut structure includes a second groove and a blocking layer. The second groove penetrates through the pixel defining layer and a part of the array substrate to one surface of the auxiliary electrode layer. The shielding layer is arranged on the pixel electrode layer and shields part of the notch of the second groove. The shielding layer and the orthographic projection part of the second groove on the array substrate are overlapped, and the width of the overlapped part is one third to one half of the depth of the second groove.

Furthermore, the display panel is provided with a display area and a frame area connected with the display area;

the array substrate comprises an array substrate structure, an insulation structure and a thin film transistor structure. The substrate structure covers the display region and the frame region. The insulating structure is arranged on the substrate structure. The thin film transistor structure is arranged in the insulation structure and is positioned in the display area. The auxiliary electrode layer and the orthographic projection of the thin film transistor structure on the substrate structure are not overlapped. The undercut structure is misaligned with an orthographic projection of the first recess on the substrate structure.

Further, the insulating structure includes a first planar layer and a second planar layer. The first planarization layer is disposed on the substrate structure. The second flat layer is arranged on a surface of the second flat layer far away from the first flat layer, and the pixel defining layer is arranged on a surface of the second flat layer far away from the first flat layer.

The thin film transistor structure comprises a source drain layer, and the source drain layer is arranged between the first flat layer and the second flat layer. The auxiliary electrode layer and the source drain layer are arranged on the same surface of the first flat layer together.

Further, in the bezel area, the display panel further includes a connection trace and a third groove. The connecting wires are arranged in the array substrate and are arranged on the same surface of the first flat layer together with the auxiliary electrode layer. The third groove penetrates through the pixel defining layer and the second flat layer to one surface of the connecting routing line. The second electrode layer extends from the display area to the frame area, and the connection wires in the third groove are electrically connected.

Further, the second flat layer and the pixel defining layer each contain an organic material therein. The shielding layer contains an inorganic material.

Further, the thickness of the shielding layer is 0.1-10 microns.

Further, the display panel further comprises a support pillar, and the support pillar is arranged between the pixel defining layer and the second electrode layer.

The invention also provides a preparation method of the display panel, which comprises the following steps:

preparing an array substrate and an auxiliary electrode layer; preparing a first electrode layer and a pixel defining layer on the array substrate; forming a first groove in the pixel defining layer and the array substrate; forming a light emitting function layer on the pixel defining layer and the array substrate; and forming a second electrode layer on the light-emitting functional layer.

Wherein the forming of the undercut structure on the pixel defining layer and the array substrate comprises: forming a second groove in the pixel defining layer and the array substrate; widening the second groove to enable the shielding layer and the orthographic projection part of the second groove on the array substrate to be overlapped, wherein the width of the overlapped part is one third to one half of the depth of the second groove.

Further, the preparation method of the display panel further comprises the following steps: defining a display area and a frame area on the array substrate: forming a connecting wire in the array substrate in the frame area, wherein the connecting wire and the auxiliary electrode layer are prepared simultaneously; and forming a third groove on the pixel defining layer and the array substrate in the frame area.

The invention also provides a display device which comprises the display panel.

The invention has the advantages that: according to the display panel and the preparation method thereof, the proportion between the shielding part and the depth of the second groove in the undercut structure is strictly controlled, so that the undercut structure achieves a perfect state capable of shielding the second electrode layer and the light-emitting function layer and enabling the packaging layer to completely cover, the problem of pressure drop in the second electrode layer is solved, the packaging effect of the packaging layer can be guaranteed, and the service life of the display panel is prolonged.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic view of a display panel according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a layer structure of a display panel according to an embodiment of the present invention;

FIG. 3 is a schematic flow chart illustrating a method for manufacturing a display panel according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a layer structure of the display panel after step S10 according to the embodiment of the present invention;

FIG. 5 is a schematic diagram of the layer structure of the display panel after step S20 according to the embodiment of the present invention;

FIG. 6 is a schematic diagram of a layered structure after forming an inorganic material layer in step S30 according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of the layered structure after widening the second groove in step S30 according to the embodiment of the present invention;

fig. 8 is a schematic diagram of a layer structure after the blocking layer is formed in step S30 in the embodiment of the present invention.

The components in the figures are represented as follows:

a display panel 1; a display area 10;

a frame region 20; a sub-pixel 11;

an array substrate 100; a substrate structure 110;

a first flexible layer 111; a first barrier layer 112;

a second flexible layer 113; a second barrier layer 114;

an insulating structure 120; a buffer layer 121;

a first insulating layer 122; a second insulating layer 123;

an interlayer dielectric layer 124; a first planarization layer 125;

a second planarization layer 126; a thin film transistor structure 130;

an active layer 131; a first gate layer 132;

a second gate layer 133; a first source drain layer 134;

a second source drain layer 135; a first electrode layer 210;

a light emitting functional layer 220; a second electrode layer 230;

a pixel defining layer 300; a first groove 310;

an auxiliary electrode layer 400; an undercut structure 500;

a second groove 510; a shielding layer 520;

an inorganic material layer 520'; an encapsulation layer 600;

a support column 700; a connection trace 800;

a third recess 900.

Detailed Description

The preferred embodiments of the present invention will be described below with reference to the accompanying drawings, which are included to demonstrate that the invention can be practiced, and to provide those skilled in the art with a complete description of the invention so that the technical content thereof will be more clear and readily understood. The present invention may be embodied in many different forms of embodiment and the scope of the invention is not limited to the embodiments set forth herein.

In the drawings, elements that are structurally identical are represented by like reference numerals, and elements that are structurally or functionally similar in each instance are represented by like reference numerals. The size and thickness of each component shown in the drawings are arbitrarily illustrated, and the present invention is not limited to the size and thickness of each component. The thickness of the components has been exaggerated in some places in the drawings where appropriate for clarity of illustration.

Furthermore, the following description of the various embodiments of the invention refers to the accompanying drawings that illustrate specific embodiments of the invention, by which the invention may be practiced. Directional phrases used in this disclosure, such as, for example, "upper," "lower," "front," "rear," "left," "right," "inner," "outer," "side," and the like, refer only to the orientation of the appended drawings and are, therefore, used herein for better and clearer illustration and understanding of the invention, and do not indicate or imply that the device or element so referred to must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the invention. Furthermore, the terms "first," "second," "third," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

When certain components are described as being "on" another component, the components can be directly on the other component; there may also be an intermediate member disposed on the intermediate member and the intermediate member disposed on the other member. When an element is referred to as being "mounted to" or "connected to" another element, it can be directly "mounted to" or "connected to" the other element or indirectly "mounted to" or "connected to" the other element through an intermediate element.

The embodiment of the invention provides a display device, which can be an OLED display device, and comprises a display panel 1, wherein the display panel 1 is used for providing a display picture for the display device. The display device can be any display device with a display function, such as a mobile phone, a notebook computer, a tablet computer, and the like.

As shown in fig. 1, the display panel 1 has a display area 10 and a frame area 20 connected to the display area 10. In the display area 10, the display panel 1 has a plurality of sub-pixels 11, the sub-pixels 11 are uniformly distributed in the display area 10, and the sub-pixels 11 can respectively emit red light, green light, blue light, and the like, and display light of different colors is emitted from the display area 10, so as to form a color display screen and realize color display. In the frame area 20, the display panel 1 is provided with a plurality of traces, and the traces are used for transmitting display signals and displaying power for the display.

As shown in fig. 2, the display panel 1 includes an array substrate 100, a first electrode layer 210, an auxiliary electrode layer 400, a pixel defining layer 300, a light emitting function layer 220, a second electrode layer 230, and an encapsulation layer 600.

The array substrate 100 includes a substrate structure 110, an insulating structure 120, and a plurality of thin film transistor structures 130.

The substrate structure 110 covers the display region 10 and the frame region 20, and includes a first flexible layer 111, a second flexible layer 113, a first barrier layer 112, and a second barrier layer 114. The first flexible layer 111 and the second flexible layer 113 are stacked, the first barrier layer 112 is disposed between the first flexible layer 111 and the second flexible layer 113, and the second barrier layer 114 is disposed on a surface of the second flexible layer 113 away from the first flexible layer 111.

Wherein the first flexible layer 111 and the second flexible layer 113 enable the display panel 1 to implement a flexible bend display. The first barrier layer and the second barrier layer are used for preventing water and oxygen from permeating into the insulating structure 120 through the first flexible layer 111 and the second flexible layer 113, and preventing the thin film transistor structure 130 in the array substrate 100 from being damaged. Specifically, the first flexible layer 111 and the second flexible layer 113 are made of the same material, and may include at least one of PI (polyimide), PET (polyethylene terephthalate), PEN (polyethylene naphthalate), PC (polycarbonate), PES (polyethersulfone), PAR (aromatic fluorotoluene containing polyarylate), or PCO (polycyclic olefin). Preferably, the material of the first flexible layer 111 and the second flexible layer 113 is PI. The material of the first barrier layer and the second barrier layer includes, but is not limited to, an oxide, a nitride or an oxynitride containing silicon, such as at least one of SiOx (silicon oxide), siN (silicon nitride) or SiON (silicon oxynitride).

The insulating structure 120 is disposed on the second blocking layer 114, covers the display area 10 and the frame area 20, and includes a buffer layer 121, a first insulating layer 122, a second insulating layer 123, an interlayer dielectric layer 124, a first planarization layer 125, and a second planarization layer 126, which are sequentially stacked. The tft structure 130 is disposed in the insulating structure 120 in the display area 10, and at least one tft structure 130 is disposed in each sub-pixel 11. The thin film transistor structure 130 includes an active layer 131, a first gate layer 132, a second gate layer 133, a first source drain layer 134, and a second source drain layer 135.

The buffer layer 121 is disposed on a surface of the second barrier layer 114 away from the second flexible layer 113. The active layer 131 is disposed on the buffer layer 121 away from the second barrier layer 114. The first insulating layer 122 is disposed on the buffer layer 121 and covers the active layer 131. The first gate layer 132 is disposed on a surface of the first insulating layer 122 away from the active layer 131. The second insulating layer 123 is disposed on the first insulating layer 122 and covers the first gate layer 132. The second gate layer 133 is disposed on a surface of the second insulating layer 123 away from the first gate layer 132. The interlayer dielectric layer 124 is disposed on the second insulating layer 123 and covers the second gate layer 133. The first source drain layer 134 is disposed on a surface of the interlayer dielectric layer 124 away from the second gate layer 133, and sequentially penetrates through the interlayer dielectric layer 124, the second insulating layer 123 and the first insulating layer 122 to be electrically connected to the active layer 131. The first planarization layer 125 is disposed on the interlayer dielectric layer 124 and covers the first source/drain layer 134. The second source drain layer 135 is disposed on the first planarization layer 125, and passes through the first planarization layer 125 to be electrically connected to the first source drain layer 134. The second planarization layer 126 is disposed on the first planarization layer 125 and covers the second source/drain layer 135.

When a current voltage is applied to the first gate layer 132 and the second gate layer 133, an electric field is generated, and the electric field causes the surface of the active layer 131 to generate induced charges, so as to change the width of the conductive channel in the active layer 131, thereby achieving the purpose of controlling the current in the first source drain layer 134. The upper and lower sides of the second source drain layer 135 are electrically connected to the first source drain layer 134 and the first electrode layer 210, respectively, so as to facilitate the transmission of the electric energy in the first source drain layer 134 to the first electrode layer 210.

Specifically, the active layer 131 is a semiconductor material, such as at least one of amorphous silicon (a-Si), low Temperature Polysilicon (LTPS), or metal oxide (IGZO). The first gate layer 132, the second gate layer 133, the first source drain layer 134, and the second source drain layer 135 are all made of metal materials with excellent conductivity, for example, at least one of metal materials such as copper, titanium, molybdenum, aluminum, silver, and the like. The buffer layer 121, the first insulating layer 122, the second insulating layer 123, and the interlayer dielectric layer 124 are all made of inorganic materials such as silicon oxide and silicon nitride. The buffer layer 121 is used for blocking water and oxygen from invading from one side of the substrate structure 110 and protecting the conductive structure in the array substrate 100. The first insulating layer 122, the second insulating layer 123 and the interlayer dielectric layer 124 are used for insulating and protecting conductive traces in the thin film transistor structure 130, so as to prevent short circuit between the traces. The first and second planarization layers 125 and 126 are made of organic materials, and planarize the surface of the array substrate 100 by leveling of the organic materials.

Each sub-pixel 11 has a first electrode layer 210 therein, and the first electrode layer 210 is disposed on the second planarization layer 126 away from the second source drain layer 135, and penetrates through the second source drain layer 135 to be electrically connected to the second source drain layer 135. The first electrode layer 210 may be a stacked structure of a transparent conductive material and a metal material, such as Indium Tin Oxide (ITO), aluminum, silver, and the like.

The pixel defining layer 300 is disposed on the second flat layer 126 and covers the first electrode layer 210. The pixel defining layer 300 has a plurality of first grooves 310 therein, and each sub-pixel 11 has one of the first grooves 310 therein. The first groove 310 penetrates through the pixel defining layer 300 to the first electrode layer 210, and the upper surface of the first electrode layer 210 (i.e., the surface of the first electrode layer 210 away from the second planarization layer 126) is exposed in the first groove 310.

The auxiliary electrode layer 400 is located in the display region 10 and between two adjacent sub-pixels 11, that is, an orthogonal projection of the auxiliary electrode layer 400 on the substrate structure 110 is not overlapped with an orthogonal projection of the first electrode layer 210 and the thin film transistor structure 130 on the substrate structure 110. The auxiliary electrode layer 400 is located between the first planar layer 125 and the second planar layer 126, and is disposed on the same surface of the first planar layer 125 together with the second source/drain layer 135, so that the auxiliary electrode layer 400 and the second source/drain layer 135 can be prepared by the same process, and therefore the material of the auxiliary electrode layer 400 is the same as that of the second source/drain layer 135.

The display panel 1 further has a plurality of undercut structures 500, wherein the undercut structures 500 are located between two adjacent sub-pixels 11, and each of the undercut structures 500 includes a second groove 510 and a shielding layer 520. The second groove 510 sequentially penetrates through the first electrode layer 210 and the second planarization layer 126 to the auxiliary electrode layer 400, so that the upper surface of the auxiliary electrode layer 400 (i.e., the surface of the auxiliary electrode layer 400 away from the first planarization layer 125) is exposed in the undercut opening. The shielding layer 520 is disposed on a surface of the pixel defining layer 300 away from the first electrode layer 210, and an orthographic projection of the shielding layer 520 on the substrate structure 110 is overlapped with an orthographic projection of the second groove 510 on the substrate structure 110. Specifically, a gap is formed between one end of the shielding layer 520 close to the second groove 510 and the auxiliary electrode layer 400 located at the bottom of the second groove 510, so that one end of the shielding layer 520 close to the second groove 510 is suspended at the notch of the second groove 510, and a shielding structure is formed.

The light emitting function layer 220 generally includes a hole function layer, an organic light emitting layer, an electronic function layer, and the like, which are stacked and disposed on the first electrode layer 210 in the first groove 310, and extend from the top surface of the pixel defining layer 300 to the wall of the second groove 510 along the sidewall of the first groove 310, so that one end of the light emitting function layer 220 located in the second groove 510 covers the side of the auxiliary electrode layer 400 in the second groove 510 away from the shielding layer 520. The light-emitting functional layer 220 is configured to obtain holes and electrons in the first electrode layer 210 and the second electrode layer 230 and combine the holes and the electrons to excite the fluorescent material thereof to emit light, so as to convert electric energy into light energy and enable the display panel 1 to realize light-emitting display.

The second electrode layer 230 is disposed on a surface of the light emitting function layer 220 away from the first electrode layer 210 and the pixel defining layer 300, and also extends from the first groove 310 into the second groove 510. Meanwhile, one end of the second electrode layer 230 located in the second groove 510 extends from the light emitting function layer 220 to cover the exposed surface of the auxiliary electrode layer 400, and is electrically connected to the auxiliary electrode layer 400. The first electrode layer 210 is an anode, and the second electrode layer 230 is a cathode.

In the frame area 20, the display panel 1 further includes a connection trace 800. The connecting trace 800 is located between the first planar layer 125 and the second planar layer 126, that is, the second source drain layer 135, the auxiliary electrode layer 400 and the connecting trace 800 are all located on a surface of the first planar layer 125 away from the first source drain layer 134, so that the connecting trace 800 is also prepared by the same process with the second source drain layer 135 and the auxiliary electrode layer 400.

In the frame area 20, the display panel 1 further has a third groove 900, and the third groove 900 sequentially penetrates through the pixel defining layer 300 and the second flat layer 126 onto the connection trace 800, so that an upper surface of the connection trace 800 (i.e., a surface of the connection trace 800 away from the first flat layer 125) is exposed in the third groove 900. Meanwhile, the second electrode layer 230 extends from the display region 10 to the frame region 20 and covers the exposed surface of the connection trace 800 in the third groove 900, so as to be electrically connected to the connection trace 800. The connection wire 800 is used for transmitting electric energy to the second electrode layer 230, so that the light-emitting functional layer 220 can obtain electrons from the second electrode layer 230.

When the display panel 1 works, due to the difference in transmission distance between the connection trace 800 in the frame area 20 and the second electrode layer 230 at different positions in the display area 10, an IR drop (IR drop) phenomenon occurs at the center position of the display area 10 and at the peripheral edge positions other than the center position, and the IR drop phenomenon may cause uneven brightness of the display screen. In the embodiment of the present invention, the second electrode layer 230 in the display region 10 is electrically connected to the auxiliary electrode layer 400, and an auxiliary voltage is additionally applied to a region with a large voltage drop (for example, the central position of the display region 10) through the auxiliary electrode, so that the voltages in the second electrode layer 230 at each position of the whole display panel 1 are the same or similar during operation, thereby making the image display brightness uniform and stable.

The encapsulation layer 600 is disposed on a surface of the second electrode layer 230 away from the light-emitting functional layer 220, and covers the display region 10 and the frame region 20. The encapsulation layer 600 may be prepared through a thin film process, and is used to prevent water and oxygen from invading into the display panel 1 from one layer of the second electrode layer 230, thereby prolonging the service life of the display panel 1.

Further, in the thin film encapsulation process, the encapsulation layer 600 is formed by depositing a continuous, complete inorganic material layer by using a chemical vapor deposition method. Due to poor toughness of the inorganic material layer, the material layer is often broken at the undercut structure 500. In order to prevent the inorganic material layer in the encapsulation layer 600 from being broken, the width W of the overlapping portion of the shielding layer 520 and the second groove 510 (i.e., the width of the overlapping portion of the orthographic projection of the shielding layer 520 and the orthographic projection of the second groove 510) in the undercut structure 500 is one third to one half of the overall depth D of the second groove 510 (i.e., the vertical distance between the shielding layer 520 and the auxiliary electrode layer 400), so that the continuity of the encapsulation layer 600 can be ensured while the shielding structure is formed, and the encapsulation effect of the encapsulation layer 600 is further improved.

The supporting posts 700 are disposed between the pixel defining layer 300 and the light emitting function layer 220, and are used for supporting the distance between the display panel 1 and other panels when the display panel 1 is assembled with other panels, so as to provide a buffer space between the display panel 1 and other panels and prevent the panels from being damaged due to mutual impact.

The embodiment of the invention also provides a preparation method of the display panel 1, which is used for preparing the display panel 1. The manufacturing flow of the manufacturing method of the display panel 1 is shown in fig. 3, which includes steps S10-S50.

Step S10) preparing the array substrate 100:

the array substrate 100 as shown in fig. 4 is formed through a TFT (Thin Film transistor) process. When the second source/drain layer 135 is prepared, a part of the metal film layer is remained between two adjacent sub-pixels 11 and in the frame region 20, so as to form the auxiliary electrode layer 400 and the connection trace 800 layer.

Step S20) forming the first electrode layer 210 and the pixel defining layer 300:

the first electrode layer 210 is formed on the array substrate 100 through a pixel electrode process, and the pixel defining layer 300 is formed by coating a layer of organic material on the array substrate 100 and the first electrode layer 210. The support posts 700 are formed on the pixel defining layer 300.

Vertical etching is performed on the pixel defining layer 300 and the array substrate 100 through a photolithography process to form a first groove 310, a second groove 510, and a third groove 900 as shown in fig. 5. Wherein, due to the difference in etching depth between the first groove 310 and the second and third grooves 510 and 900, the array substrate 100 and the pixel defining layer 300 may be patterned through a Half-tone (Half-tone) mask process.

Step S30) forming the undercut structure 500:

a layer of inorganic material having a thickness of 0.1-10 microns is deposited over the pixel defining layer 300 to form a layer of inorganic material 520' as shown in fig. 6. The inorganic material layer 520' covers the pixel defining layer 300, the first recess 310, the third recess 900 and a portion of the second recess 510, so that a portion of the sidewall of the second recess 510 is exposed, and the exposed sidewall and the shielding layer 520 are located on the same side of the second recess 510. Wherein the inorganic material may include at least one of silicon oxide, silicon nitride, or silicon oxynitride.

As shown in FIG. 7, using O ₂ The exposed sidewalls of the second groove 510 are etched horizontally by plasma (oxygen plasma), so as to widen the width of the second groove 510, and a portion of the inorganic material layer 520' is suspended at the edge of the notch of the second groove 510, thereby forming a shielding structure. Since the second flat and pixel defining layer 300 in the array substrate 100 is an organic material and has a different material property from the inorganic material layer 520', the inorganic material layer 520' is not etched when the width of the second groove 510 is widened, so as to form a suspended shielding structure.

Specifically, the etching width of the second groove 510 during the second horizontal etching is one third to one half of the etching depth of the second groove 510 during the first vertical etching, so that the width W of the overlapping portion of the second groove 510 and the light shielding layer is one third to one half of the depth D of the second groove 510.

The inorganic material layer 520' is patterned to form the blocking layer 520 as shown in fig. 8. The shielding layer 520 and the second groove 510 combine to form the undercut structure 500.

Step S40) forming the light emitting function layer 220 and the second electrode layer 230:

a layer of organic material is evaporated on the pixel defining layer 300 and in the first, second, and third grooves 310, 510, and 900 to form the light emitting function layer 220. A layer of conductive material is vapor-deposited on the light-emitting functional layer 220 to form the second electrode layer 230. The evaporation range of the second electrode layer 230 is greater than that of the light emitting function layer 220, so that the second electrode layer 230 can be electrically connected to the auxiliary electrode layer 400 in the second groove 510 and the connection trace 800 in the third groove 900.

Step S50) forming the encapsulation layer 600: a plurality of layers of inorganic materials and a plurality of layers of organic materials are respectively deposited on the second electrode layer 230 through a thin film encapsulation process, and the deposited materials cover the surface of the second groove 510 that is not covered by the second electrode layer 230, so as to form a continuous encapsulation layer 600 completely covering the display panel 1 as shown in fig. 1.

According to the display panel and the preparation method thereof provided by the embodiment of the invention, the undercut structure is enabled to achieve a perfect state that the encapsulation layer can completely cover while the second electrode layer and the light-emitting function layer can be shielded by adjusting the proportion between the shielding part and the part which is not shielded in the undercut structure, so that the encapsulation effect of the encapsulation layer can be ensured while the problem of pressure drop in the second electrode layer is solved, and the service life of the display panel is prolonged.

Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that features described in different dependent claims and herein may be combined in ways different from those described in the original claims. It is also to be understood that features described in connection with individual embodiments may be used in other described embodiments.

Claims (10)

1. A display panel, comprising:

an array substrate;

the auxiliary electrode layer is arranged in the array substrate;

the first electrode layer is arranged on the array substrate and is electrically connected with the array substrate;

the pixel limiting layer is arranged on the array substrate and covers the first electrode layer;

a first groove penetrating the pixel defining layer onto a surface of the first electrode layer;

an undercut structure provided in the pixel defining layer and the array substrate and corresponding to the auxiliary electrode layer;

the light-emitting functional layer is arranged in the first groove and extends into the undercut structure from the first groove;

the second electrode layer is arranged on the light-emitting functional layer and extends from the light-emitting functional layer to cover the auxiliary electrode layer in the undercut structure;

the packaging layer is arranged on the second electrode layer, and the exposed surface in the undercut structure is formed;

wherein the undercut structure comprises:

a second groove penetrating through the pixel defining layer and a part of the array substrate to a surface of the auxiliary electrode layer;

the shielding layer is arranged on the pixel electrode layer and shields part of the notch of the second groove;

the shielding layer and the orthographic projection part of the second groove on the array substrate are overlapped, and the width of the overlapped part is one third to one half of the depth of the second groove.

2. The display panel of claim 1, having a display area and a frame area connected to the display area;

the array substrate includes:

a substrate structure covering the display region and the frame region;

the insulating structure is arranged on the substrate structure;

the thin film transistor structure is arranged in the insulating structure and is positioned in the display area;

the auxiliary electrode layer and the orthographic projection of the thin film transistor structure on the substrate structure are not overlapped;

the undercut structure is misaligned with an orthographic projection of the first recess on the substrate structure.

3. The display panel according to claim 2, wherein the insulating structure comprises:

a first planar layer disposed on the substrate structure;

the second flat layer is arranged on one surface of the second flat layer far away from the first flat layer, and the pixel defining layer is arranged on one surface of the second flat layer far away from the first flat layer;

the thin film transistor structure includes:

the source drain layer is arranged between the first flat layer and the second flat layer;

the auxiliary electrode layer and the source drain layer are arranged on the same surface of the first flat layer together.

4. The display panel according to claim 3, wherein in the bezel region, the display panel further comprises:

the connecting routing is arranged in the array substrate and is arranged on the same surface of the first flat layer together with the auxiliary electrode layer;

a third groove penetrating through the pixel defining layer and the second planarization layer to a surface of the connection trace;

the second electrode layer extends from the display area to the frame area, and the connection wires in the third groove are electrically connected.

5. The display panel of claim 3,

the second flat layer and the pixel defining layer both include an organic material therein;

the shielding layer contains an inorganic material.

6. The display panel of claim 1, wherein the thickness of the blocking layer is 0.1 to 10 microns.

7. The display panel of claim 1, further comprising:

a support pillar disposed between the pixel defining layer and the second electrode layer.

8. A preparation method of a display panel is characterized by comprising the following steps:

preparing an array substrate and an auxiliary electrode layer;

preparing a first electrode layer and a pixel defining layer on the array substrate;

forming a first groove in the pixel defining layer and the array substrate;

forming an undercut structure on the pixel defining layer and the array substrate;

forming a light emitting function layer on the pixel defining layer and the array substrate;

forming a second electrode layer on the light emitting function layer;

wherein the forming of the undercut structure on the pixel defining layer and the array substrate comprises:

forming a second groove in the pixel defining layer and the array substrate; widening the second groove to enable the shielding layer and the orthographic projection part of the second groove on the array substrate to be overlapped, wherein the width of the overlapped part is one third to one half of the depth of the second groove.

9. The method for manufacturing a display panel according to claim 8, further comprising the steps of:

defining a display area and a frame area on the array substrate:

forming a connecting wire in the array substrate in the frame area, wherein the connecting wire and the auxiliary electrode layer are prepared simultaneously;

and forming a third groove on the pixel limiting layer and the array substrate in the frame area.

10. A display device characterized by comprising the display panel according to any one of claims 1 to 7.

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