CN115459752A - Driving circuit of gallium nitride power device - Google Patents

Driving circuit of gallium nitride power device Download PDF

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Publication number
CN115459752A
CN115459752A CN202210991983.4A CN202210991983A CN115459752A CN 115459752 A CN115459752 A CN 115459752A CN 202210991983 A CN202210991983 A CN 202210991983A CN 115459752 A CN115459752 A CN 115459752A
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Prior art keywords
gate
input end
circuit
tube
output end
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CN202210991983.4A
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Chinese (zh)
Inventor
李彬
徐丽莉
宋科
李东林
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Sichuan Aviation Vocational College Sichuan Space Advanced Technical School
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Sichuan Aviation Vocational College Sichuan Space Advanced Technical School
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
    • H03K17/0822—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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Abstract

The invention discloses a driving circuit of a gallium nitride power device, which comprises a high-level input end, a low-level input end, a driving output end, a VDD voltage end, a VB voltage end, a Vs end, an input-stage driving circuit, a self-adaptive dead zone circuit, two shifting circuits, two output-stage driving circuits, a negative pressure detection circuit, a first resistor, a second resistor, a third resistor, a fourth resistor, an eleventh PMOS (P-channel metal oxide semiconductor) tube and an eleventh NMOS (N-channel metal oxide semiconductor) tube, wherein the two output-stage driving circuits comprise a first output-stage driving circuit and a second output-stage driving circuit, and the two shifting circuits comprise a high-level shifting circuit and a low-level shifting circuit. The driving circuit in the invention can not only ensure the normal power supply of the high-voltage side circuit of the gallium nitride power device, but also realize the grid clamping protection function of the gallium nitride power device on the basis of not losing the VS negative bias capability of the chip of the driving circuit.

Description

Driving circuit of gallium nitride power device
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a driving circuit of a gallium nitride power device.
Background
Compared with the traditional Si (silicon) based power device, the GaN (gallium nitride) power device has higher current density, higher working frequency and lower switching loss, and the advantages enable the GaN power device to gradually replace the Si based power device and become the mainstream choice of high-density power modules in equipment such as cloud computing and 5G communication. The driving chip of the GaN power device has become a main reason for restricting the application thereof.
In order to fully exert the high-frequency switching performance of the Ga N device, the Ga N driving chip matched with the Ga N device must have strong driving capability, so that the Ga N device can be turned on and off quickly. At present, a traditional output stage driving circuit is realized by adopting a phase inverter chain with driving capability and size gradually increased, when the driving stage drives a high-voltage heavy-current device, a section of direct connection process of a power tube MP (MP) and a power tube MN (MN) of a power output stage can be generated when the driving stage works, and because the current capability of the output stage is very large, chip loss can be greatly increased in the section of direct connection process, and even an output stage is damaged.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a driving circuit of a gallium nitride power device, which can ensure the normal power supply of a high-voltage side circuit of the gallium nitride power device.
The purpose of the invention is realized by the following technical scheme: a driving circuit of a gallium nitride power device comprises a high-level input end, a low-level input end, a driving output end, a VDD voltage end, a VB voltage end, a Vs end, an input-stage driving circuit, a self-adaptive dead zone circuit, two shifting circuits, two output-stage driving circuits, a negative pressure detection circuit, a first resistor, a second resistor, a third resistor, a fourth resistor, an eleventh PMOS (P-channel metal oxide semiconductor) tube and an eleventh NMOS (N-channel metal oxide semiconductor) tube, wherein the two output-stage driving circuits comprise a first output-stage driving circuit and a second output-stage driving circuit, and the two shifting circuits comprise a high-level shifting circuit and a low-level shifting circuit;
the first input end of the input stage driving circuit is connected with the high-level input end, the second input end of the input stage driving circuit is connected with the low-level input end, the high-level output end of the input stage driving circuit is connected with the high-level input end of the self-adaptive dead zone circuit, and the low-level output end of the input stage driving circuit is connected with the low-level input end of the self-adaptive dead zone circuit;
the high level output end of the self-adaptive dead zone circuit is connected with the second input end of the high level shift circuit and the fourth input end of the low level shift circuit, and the low level output end of the self-adaptive dead zone circuit is connected with the first input end of the high level shift circuit and the third input end of the low level shift circuit; the high level output end of the high level shift circuit is connected with the input end of the first output stage drive circuit, and the low level output end of the low level shift circuit is connected with the input end of the second output stage drive circuit;
the high-level output end of the first output stage driving circuit is connected with the grid electrode of an eleventh PMOS tube through a first resistor, and the low-level output end of the first output stage driving circuit is connected with the grid electrode of the eleventh PMOS tube through a second resistor; the high level output end of the second output stage driving circuit is connected with the grid electrode of an eleventh NMOS tube through a third resistor, and the low level output end of the second output stage driving circuit is connected with the grid electrode of the eleventh NMOS tube through a fourth resistor; the drain electrode of the eleventh PMOS tube is connected with power supply voltage, the source electrode of the eleventh PMOS tube is connected with the drain electrode of the eleventh NMOS tube, the source electrode of the eleventh NMOS tube is grounded, and the connecting point of the source electrode of the eleventh PMOS tube and the drain electrode of the eleventh NMOS tube is connected with the driving output end;
the input end of the negative voltage detection circuit is connected with the Vs end, the Vs end is connected with the driving output end, the output end of the negative voltage detection circuit is connected with the control end of the self-adaptive dead zone circuit, the power end of the high-voltage level shift circuit and the power end of the first output stage driving circuit are connected with the VB voltage end, and the power end of the input stage driving circuit, the power end of the low-voltage level shift circuit and the power end of the second output stage driving circuit are connected with the VDD voltage end.
Furthermore, the driving circuit further comprises a clamping protection circuit, a first control end of the clamping protection circuit is connected with a VB voltage end, an output end of the clamping protection circuit is connected with a clamping protection end of the high-level shift circuit, an output end of the negative voltage detection circuit is connected with a second control end of the clamping protection circuit, and a power supply end of the clamping protection circuit is connected with a VDD voltage end.
Further, the input stage driving circuit comprises a first NOR gate, a first NAND gate, a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate and a fifth NOT gate; the first input end of the first NAND gate is used as the high-level input end of the input-stage driving circuit, the output end of the first NAND gate is connected with the input end of a first NOT gate, the output end of the first NOT gate is connected with the input end of a second NOT gate, the output end of the second NOT gate is connected with the input end of a third NOT gate, the output end of the third NOT gate is connected with the first input end of a first NOR gate, and the output end of the third NOT gate is used as the high-level output end of the input-stage driving circuit; the second input end of the first NOR gate is used as the low level input end of the input stage driving circuit, the output end of the first NOR gate is connected with the input end of the fourth NOR gate, the output end of the fourth NOR gate is connected with the input end of the fifth NOR gate, the output end of the fifth NOR gate is connected with the second input end of the first NAND gate, and the output end of the fifth NOR gate is used as the low level output end of the input stage driving circuit.
Further, the adaptive dead zone circuit comprises a sixth not gate, a seventh not gate, a second not gate, a third not gate, a first exclusive-or gate, a second exclusive-or gate, a first dynamic delay unit and a second dynamic delay unit;
the input end of the sixth not gate is used as the high-level input end of the adaptive dead-zone circuit, the output end of the sixth not gate is connected with the first input end of the second not gate and the first input end of the first exclusive-or gate, the input end of the first dynamic delay unit is connected with the input end of the sixth not gate, the output end of the first dynamic delay unit is connected with the second input end of the first exclusive-or gate, and the output end of the first exclusive-or gate is connected with the first input end of the third not gate;
the input end of the seventh not gate is used as the low level input end of the adaptive dead zone circuit, the output end of the seventh not gate is connected with the second input end of the second exclusive-or gate and the second input end of the third nand gate, the input end of the second dynamic delay unit is connected with the input end of the seventh not gate, the output end of the second dynamic delay unit is connected with the first input end of the second exclusive-or gate, the output end of the second exclusive-or gate is connected with the second input end of the second nand gate, and the output end of the third nand gate is used as the high level output end of the adaptive dead zone circuit.
Further, the shift circuit is a dual interlock level shift circuit.
Further, the shift circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a first diode, a second diode, a third xor gate, a fourth xor gate, an eighth not gate, a ninth not gate, a first interlock signal terminal, a second interlock signal terminal, and a feedback terminal;
the grid electrode of the first NMOS tube is used as a first input end of the shift circuit, the source electrode of the first NMOS tube is grounded, the grid electrode of the second NMOS tube is used as a second input end of the shift circuit, and the source electrode of the second NMOS tube is grounded; the grid electrode of the third NMOS tube is connected with the grid electrode of the fourth NMOS tube, the grid electrode of the fourth NMOS tube is connected with the drain electrode of the fourth NMOS tube, the grid electrode of the fifth NMOS tube is connected with the grid electrode of the sixth NMOS tube, the grid electrode of the fifth NMOS tube is connected with the drain electrode of the fifth NMOS tube, and the source electrode of the third NMOS tube, the source electrode of the fourth NMOS tube, the source electrode of the fifth NMOS tube, the source electrode of the sixth NMOS tube, the source electrode of the seventh NMOS tube, the source electrode of the eighth NMOS tube, the source electrode of the ninth NMOS tube and the source electrode of the tenth NMOS tube are all connected with the feedback end; the grid electrode of the seventh NMOS tube, the grid electrode of the eighth NMOS tube, the grid electrode of the ninth NMOS tube and the grid electrode of the tenth NMOS tube are all connected with the first interlocking signal end;
the anode of the first diode and the anode of the second diode are both connected with the feedback end, the cathode of the first diode is connected with the drain electrode of the first NMOS tube, and the cathode of the second diode is connected with the drain electrode of the second NMOS tube;
the grid electrode of the first PMOS tube is used as a third input end of the shift circuit, the grid electrode of the second PMOS tube is used as a fourth input end of the shift circuit, the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube, and the grid electrode of the first PMOS tube, the grid electrode of the third PMOS tube and the grid electrode of the fourth PMOS tube are all connected with the drain electrode of the first PMOS tube; the drain electrode of the second PMOS tube is connected with the drain electrode of the second PMOS tube, and the drain electrode of the second PMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the sixth PMOS tube are all connected with the grid electrode of the second PMOS tube; the source electrode of the first PMOS tube, the source electrode of the second PMOS tube, the source electrode of the third PMOS tube, the source electrode of the fourth PMOS tube, the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube are all connected with the VDD voltage end; the drain electrode of the third PMOS tube is connected with the drain electrode of the third NMOS tube, the drain electrode of the fourth PMOS tube is connected with the drain electrode of the fifth NMOS tube, the drain electrode of the fifth PMOS tube is connected with the drain electrode of the fourth NMOS tube, and the drain electrode of the sixth PMOS tube is connected with the drain electrode of the sixth NMOS tube;
a first input end of the third exclusive-or gate is connected with a drain electrode of a sixth PMOS transistor, an output end of the third exclusive-or gate is used as a high level output end of the shift circuit, a first input end of the fourth exclusive-or gate is connected with an output end of the third exclusive-or gate, a second input end of the fourth exclusive-or gate is connected with a drain electrode of a third NMOS transistor, an output end of the fourth exclusive-or gate is used as a low level output end of the shift circuit, and an output end of the fourth exclusive-or gate is connected with a second input end of the third exclusive-or gate; the source electrode of the seventh PMOS tube, the source electrode of the eighth PMOS tube, the source electrode of the ninth PMOS tube and the source electrode of the tenth PMOS tube are connected with a VB voltage end, the grid electrode of the seventh PMOS tube and the grid electrode of the eighth PMOS tube are connected with a second interlocking signal end, the drain electrode of the seventh PMOS tube is connected with the drain electrode of the seventh NMOS tube, the drain electrode of the eighth PMOS tube is connected with the drain electrode of the eighth NMOS tube, the grid electrode of the ninth PMOS tube is connected with the output end of the fourth exclusive-OR gate, the drain electrode of the ninth PMOS tube is connected with the drain electrode of the ninth NMOS tube, the grid electrode of the tenth PMOS tube is connected with the output end of the third exclusive-OR gate, and the drain electrode of the tenth PMOS tube is connected with the drain electrode of the tenth NMOS tube;
the input end of the eighth not gate is connected with the drain electrode of the tenth PMOS tube, the output end of the eighth not gate is connected with the second input end of the fourth exclusive-OR gate, the input end of the ninth not gate is connected with the drain electrode of the ninth NMOS tube, and the output end of the ninth not gate is connected with the first input end of the third exclusive-OR gate.
Furthermore, the output stage driving circuit comprises a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube and a fourteenth NMOS tube; the source electrode of the twelfth PMOS tube, the source electrode of the thirteenth PMOS tube and the source electrode of the fourteenth PMOS tube are all connected with the power supply end of the output stage driving circuit, and the source electrode of the twelfth NMOS tube, the source electrode of the thirteenth NMOS tube and the source electrode of the fourteenth NMOS tube are all grounded; the grid electrode of the twelfth PMOS tube and the grid electrode of the twelfth NMOS tube are connected to a first connection point, the first connection point is used as the input end of the output stage driving circuit, the drain electrode of the twelfth PMOS tube and the drain electrode of the twelfth NMOS tube are connected to a second connection point, the grid electrode of the thirteenth PMOS tube and the grid electrode of the thirteenth NMOS tube are connected to a third connection point, the thirteenth connection point is connected to the twelfth connection point, the drain electrode of the thirteenth PMOS tube and the drain electrode of the thirteenth NMOS tube are connected to a fourth connection point, the grid electrode of the fourteenth PMOS tube and the grid electrode of the fourteenth NMOS tube are connected to a fifth connection point, the fifth connection point is connected to the fourth connection point, the fifth connection point is used as the output end of the output stage driving circuit, the source electrode of the fourteenth PMOS tube and the drain electrode of the fourteenth NMOS tube are connected to a sixth connection point, and the sixth connection point is connected to the third connection point.
Furthermore, the driving circuit of the gallium nitride power device further comprises two under-voltage protection circuits, the two under-voltage protection circuits are respectively recorded as a first under-voltage protection circuit and a second under-voltage protection circuit, the input end of the first under-voltage protection circuit is connected with the low level output end of the high level shift circuit, the output end of the first under-voltage protection circuit is connected with the second interlocking signal end of the high level shift circuit, the input end of the second under-voltage protection circuit is connected with the low level output end of the low level shift circuit, and the output end of the second under-voltage protection circuit is connected with the first interlocking signal end of the low level shift circuit.
Further, the undervoltage protection circuit comprises a comparator, a first RS flip-flop, a second RS flip-flop, a current-frequency oscillator, a first frequency divider, a second frequency divider, a first D flip-flop, a second nor gate, a first exclusive nor gate, a fourth nand gate, and a first and gate;
the first input end of the comparator is connected with a VDD voltage end, the second input end of the comparator is connected with the low-level output end of the shift circuit, and the output end of the comparator is respectively connected with the S end of the first RS trigger, the Reset end of the first frequency divider, the Reset end of the first D trigger, the second input end of the second NOR gate, the first input end of the first XOR gate and the first input end of the fourth NAND gate; the output end of the first RS trigger is connected with the input end of a current-frequency oscillator, and the output end of the current-frequency oscillator is respectively connected with the CLK end of the first frequency divider and the CLK end of the second frequency divider; the output end of the first frequency divider is connected with the CLK end of a first D flip-flop
Figure BDA0003802931080000051
The end of the first NOR gate is connected with the first input end of a first NOR gate, and the output end of the first NOR gate is connected with the S end of a first RS trigger;
the output end of the second frequency divider is connected with the CLK end of a second D flip-flop
Figure BDA0003802931080000052
The output end of the first exclusive nor gate is connected with the first input end of the first and gate; the second input end of the first AND gate is connected with the output end of a fourth NAND gate, and the second input end of the fourth NAND gate is respectively connected with the Reset end of the second frequency divider and the Reset end of the second D flip-flop(ii) a The output end of the first and gate is connected with the R end of the first RS trigger and the R end of the second RS trigger respectively, the output end of the second RS trigger is connected with the second input end of the fourth NAND gate, and the output end of the second RS trigger is used as the output end of the undervoltage protection circuit.
The invention has the beneficial effects that: the driving circuit in the invention can ensure normal power supply of a high-voltage side circuit of the gallium nitride power device, and can realize a grid clamping protection function of the gallium nitride power device on the basis of not losing VS negative bias capability of a chip of the driving circuit.
Drawings
FIG. 1 is a block diagram of an embodiment of a driving circuit of a GaN power device according to the invention;
FIG. 2 is a block diagram of an embodiment of an input stage driver circuit according to the present invention;
FIG. 3 is a block diagram illustrating the components of an embodiment of the adaptive dead band circuit of the present invention;
FIG. 4 is a functional timing diagram of the adaptive dead band circuit of the present invention;
FIG. 5 is a block diagram of the shift circuit according to one embodiment of the present invention;
FIG. 6 is a functional timing diagram of a shift circuit according to the present invention;
FIG. 7 is a block diagram of an embodiment of an output stage driver circuit according to the present invention;
FIG. 8 is a block diagram of an embodiment of the undervoltage protection circuit of the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the following embodiments, and it should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive effort based on the embodiments of the present invention, are within the scope of the present invention.
Referring to fig. 1 to fig. 8, the present embodiment provides a driving circuit of a gan power device:
as shown in fig. 1, a driving circuit of a gallium nitride power device includes a high level input end, a low level input end, a driving output end, a VDD voltage end, a VB voltage end, a Vs end, an input stage driving circuit, a self-adaptive dead zone circuit, two shift circuits, two output stage driving circuits, a negative voltage detection circuit, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, an eleventh PMOS transistor MP11, and an eleventh NMOS transistor MN11, where the two output stage driving circuits include a first output stage driving circuit and a second output stage driving circuit, and the two shift circuits include a high level shift circuit and a low level shift circuit.
The first input end of the input stage driving circuit is connected with the high-level input end, the second input end of the input stage driving circuit is connected with the low-level input end, the high-level output end of the input stage driving circuit is connected with the high-level input end of the self-adaptive dead zone circuit, and the low-level output end of the input stage driving circuit is connected with the low-level input end of the self-adaptive dead zone circuit.
The high level output end of the self-adaptive dead zone circuit is connected with the second input end of the high level shift circuit and the fourth input end of the low level shift circuit, and the low level output end of the self-adaptive dead zone circuit is connected with the first input end of the high level shift circuit and the third input end of the low level shift circuit; and the high level output end of the high level shift circuit is connected with the input end of the first output stage drive circuit, and the low level output end of the low level shift circuit is connected with the input end of the second output stage drive circuit.
The high level output end of the first output stage driving circuit is connected with the grid electrode of an eleventh PMOS (P-channel metal oxide semiconductor) transistor MP11 through a first resistor R1, and the low level output end of the first output stage driving circuit is connected with the grid electrode of the eleventh PMOS transistor MP11 through a second resistor R2; the high-level output end of the second output stage driving circuit is connected with the grid electrode of an eleventh NMOS (N-channel metal oxide semiconductor) transistor MN11 through a third resistor R3, and the low-level output end of the second output stage driving circuit is connected with the grid electrode of the eleventh NMOS transistor MN11 through a fourth resistor R4; the drain electrode of the eleventh PMOS tube MP11 is connected with the power supply voltage, the source electrode of the eleventh PMOS tube MP11 is connected with the drain electrode of the eleventh NMOS tube MN11, the source electrode of the eleventh NMOS tube MN11 is grounded, and the connecting point of the source electrode of the eleventh PMOS tube MP11 and the drain electrode of the eleventh NMOS tube MN11 is connected with the drive output end.
The input end of the negative voltage detection circuit is connected with the Vs end, the Vs end is connected with the driving output end, the output end of the negative voltage detection circuit is connected with the control end of the self-adaptive dead zone circuit, the power end of the high-voltage level shift circuit and the power end of the first output stage driving circuit are connected with the VB voltage end, and the power end of the input stage driving circuit, the power end of the low-voltage level shift circuit and the power end of the second output stage driving circuit are connected with the VDD voltage end.
In this embodiment, the input signal is transmitted to the high level input terminal (HI in fig. 1) and the low level input terminal (LI in fig. 1) of the GaN power device driver chip, and the two channels on the high and low voltage sides use the identical transmission logic to implement strict delay matching. The signal is shaped by the input stage driving circuit to obtain a standard square wave signal, the shaped signal enters the self-adaptive dead zone generating circuit, and the input stage driving circuit improves the signal-to-noise ratio of the input signal. The self-adaptive dead zone circuit solves the contradiction between the fixed dead zone time and the reverse conduction loss of the GaN power device, and solves the problem that the level shift signal is difficult to be transmitted to a low-voltage area in a high-voltage application environment in the application of a Buck type switching power supply converter by the traditional self-adaptive dead zone technology. The negative voltage detection circuit monitors the state of the Vs terminal voltage to determine the adjustment direction of the delay time for generating the dead zone internally. The output stage driving circuit adopts two-port output, grid resistors (such as a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4) with different sizes are externally connected, the value of the resistors is selected from 1-100 ohms according to the situation, the loss is increased when the resistance is too large, and serious electromagnetic interference noise and overshoot are caused when the resistance is too small), and the rising/falling speed of the GaN power device is respectively controlled to obtain the compromise between the opening loss and the electromagnetic interference.
In one embodiment, the driving circuit further comprises a clamp protection circuit, a first control terminal of the clamp protection circuit is connected with the VB voltage terminal, an output terminal of the clamp protection circuit is connected with a clamp protection terminal of the high level shift circuit, an output terminal of the negative voltage detection circuit is connected with a second control terminal of the clamp protection circuit, and a power supply terminal of the clamp protection circuit is connected with the VDD voltage terminal.
The clamp protection circuit adopts the PMOS tube as the buffer stage, so that the response voltage of the buffer stage is reduced, the power supply of two parts of the high-voltage side is realized through the double-level bootstrap power supply circuit so as to ensure the negative bias capability of the chip, and the work of the double-bootstrap power supply circuit is controlled by generating a control signal through the negative bias detection circuit so as to achieve the purpose of output voltage clamping. The clamping protection circuit is a negative bias clamping protection circuit, the negative bias clamping protection circuit meets the requirements of voltage clamping on the high-voltage side of the GaN high-voltage grid electrode driving chip and protection of a rear-stage GaN device, the negative bias capability of the chip is improved, and therefore the stability of the chip is improved.
As shown in fig. 2, in one embodiment, the input stage driving circuit includes a first NOR gate NOR1, a first NAND gate NAND1, a first not gate INV1, a second not gate INV2, a third not gate INV3, a fourth not gate INV4, and a fifth not gate INV5; the first input end of the first NAND gate NAND1 is used as the high level input end of the input stage driving circuit, the output end of the first NAND gate NAND1 is connected with the input end of a first not gate INV1, the output end of the first not gate INV1 is connected with the input end of a second not gate INV2, the output end of the second not gate INV2 is connected with the input end of a third not gate INV3, the output end of the third not gate INV3 is connected with the first input end of a first NOR gate NOR1, and the output end of the third not gate INV3 is used as the high level output end of the input stage driving circuit; the second input end of the first NOR gate NOR1 is used as the low level input end of the input stage driving circuit, the output end of the first NOR gate NOR1 is connected with the input end of a fourth not gate INV4, the output end of the fourth not gate INV4 is connected with the input end of a fifth not gate INV5, the output end of the fifth not gate INV5 is connected with the second input end of the first NAND gate NAND1, and the output end of the fifth not gate INV5 is used as the low level output end of the input stage driving circuit.
As shown in fig. 3, in one embodiment, the adaptive dead zone circuit includes a sixth not gate INV6, a seventh not gate INV7, a second NAND gate NAND2, a third NAND gate NAND3, a first XOR gate XOR1, a second XOR gate XOR2, a first dynamic DELAY unit DELAY1, and a second dynamic DELAY unit DELAY2; an input end of the sixth not gate INV6 is used as a high-level input end of the adaptive dead-zone circuit, an output end of the sixth not gate INV6 is connected with a first input end of a second NAND gate NAND2 and a first input end of a first exclusive or gate XOR1, an input end of the first dynamic DELAY unit DELAY1 is connected with an input end of the sixth not gate INV6, an output end of the first dynamic DELAY unit DELAY1 is connected with a second input end of the first exclusive or gate XOR1, and an output end of the first exclusive or gate XOR1 is connected with a first input end of a third NAND gate NAND 3; the input end of the seventh not gate INV7 is used as the low level input end of the adaptive dead zone circuit, the output end of the seventh not gate INV7 is connected with the second input end of the second exclusive or gate XOR2 and the second input end of the third NAND gate NAND3, the input end of the second dynamic DELAY unit DELAY2 is connected with the input end of the seventh not gate INV7, the output end of the second dynamic DELAY unit DELAY2 is connected with the first input end of the second exclusive or gate XOR2, the output end of the second exclusive or gate XOR2 is connected with the second input end of the second NAND gate NAND2, and the output end of the third NAND gate NAND3 is used as the high level output end of the adaptive dead zone circuit.
As shown IN fig. 4, if there is an overlap between the input signals of the high-level input terminal (IN _ H) and the low-level input terminal (IN _ L) of the adaptive dead-time circuit, the adaptive dead-time circuit will force the two signals OUT _ H and OUT _ L to be set to zero IN the overlapping region to ensure that the output signals are normal, and will also superimpose a certain dead time. To illustrate more specifically, the input signals IN _ H and IN _ L are two square wave signals interlaced with each other, the C1 signal is an output signal of IN _ H after passing through the dynamic delay unit, the dynamic delay unit only delays the falling edge of the input signal and outputs an inverted signal, and thus, the falling edge of IN _ H is delayed; the output is an A1 signal used for controlling the opening time of a low-pressure side channel. Similarly, B1 is the falling edge delay output signal of IN _ L for controlling the on-time of the high-side channel. Finally, the inverted signal A and the B1 of the IN _ H or the non-rear output signal turn on the eleventh PMOS tube MP11 and form dead time from turning off of the eleventh NMOS tube MN11 to turning on of the eleventh PMOS tube MP11, and the inverted signal B and the A1 of the IN _ L or the non-rear output signal turn on the eleventh NMOS tube MN11 and form dead time from turning off of the eleventh PMOS tube MP11 to turning on of the eleventh NMOS tube MN 11.
In one embodiment, the shift circuit is a dual interlock level shift circuit.
As shown in fig. 5, in one embodiment, the shift circuit includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, a first diode D1, a second diode D2, a third exclusive or gate XOR3, a fourth exclusive or gate XOR4, an eighth exclusive or gate INV8, a ninth exclusive or INV9, a first interlock signal terminal, a second interlock signal terminal, and a feedback terminal.
The grid electrode of the first NMOS tube MN1 is used as a first input end of the shift circuit, the source electrode of the first NMOS tube MN1 is grounded, the grid electrode of the second NMOS tube MN2 is used as a second input end of the shift circuit, and the source electrode of the second NMOS tube MN2 is grounded; the grid electrode of the third NMOS tube MN3 is connected with the grid electrode of the fourth NMOS tube MN4, the grid electrode of the fourth NMOS tube MN4 is connected with the drain electrode of the fourth NMOS tube MN4, the grid electrode of the fifth NMOS tube MN5 is connected with the grid electrode of the sixth NMOS tube MN6, the grid electrode of the fifth NMOS tube MN5 is connected with the drain electrode of the fifth NMOS tube MN5, and the source electrode of the third NMOS tube MN3, the source electrode of the fourth NMOS tube MN4, the source electrode of the fifth NMOS tube MN5, the source electrode of the sixth NMOS tube MN6, the source electrode of the seventh NMOS tube MN7, the source electrode of the eighth NMOS tube MN8, the source electrode of the ninth NMOS tube MN9 and the source electrode of the tenth NMOS tube MN10 are all connected with the feedback end; the grid electrode of the seventh NMOS tube MN7, the grid electrode of the eighth NMOS tube MN8, the grid electrode of the ninth NMOS tube MN9 and the grid electrode of the tenth NMOS tube MN10 are all connected with a first interlocking signal end.
The positive pole of the first diode D1 and the positive pole of the second diode D2 are both connected with the feedback end, the negative pole of the first diode D1 is connected with the drain electrode of the first NMOS tube MN1, and the negative pole of the second diode D2 is connected with the drain electrode of the second NMOS tube MN 2.
The grid electrode of the first PMOS tube MP1 is used as a third input end of the shift circuit, the grid electrode of the second PMOS tube MP2 is used as a fourth input end of the shift circuit, the drain electrode of the first PMOS tube MP1 is connected with the drain electrode of the first NMOS tube MN1, and the grid electrode of the first PMOS tube MP1, the grid electrode of the third PMOS tube MP3 and the grid electrode of the fourth PMOS tube MP4 are all connected with the drain electrode of the first PMOS tube MP 1; the drain electrode of the second PMOS tube MP2 is connected with the drain electrode of the second PMOS tube MP2, and the drain electrode of the second PMOS tube MP2, the grid electrode of the fifth PMOS tube MP5 and the grid electrode of the sixth PMOS tube MP6 are connected with the grid electrode of the second PMOS tube MP 2; the source electrode of the first PMOS tube MP1, the source electrode of the second PMOS tube MP2, the source electrode of the third PMOS tube MP3, the source electrode of the fourth PMOS tube MP4, the source electrode of the fifth PMOS tube MP5 and the source electrode of the sixth PMOS tube MP6 are all connected with the VDD voltage end; the drain electrode of the third PMOS transistor MP3 is connected to the drain electrode of the third NMOS transistor MN3, the drain electrode of the fourth PMOS transistor MP4 is connected to the drain electrode of the fifth NMOS transistor MN5, the drain electrode of the fifth PMOS transistor MP5 is connected to the drain electrode of the fourth NMOS transistor MN4, and the drain electrode of the sixth PMOS transistor MP6 is connected to the drain electrode of the sixth NMOS transistor MN 6.
A first input end of the third exclusive-or gate XOR3 is connected to a drain electrode of a sixth PMOS transistor MP6, an output end of the third exclusive-or gate XOR3 serves as a high level output end of the shift circuit, a first input end of the fourth exclusive-or gate XOR4 is connected to an output end of the third exclusive-or gate XOR3, a second input end of the fourth exclusive-or gate XOR4 is connected to a drain electrode of a third NMOS transistor MN3, an output end of the fourth exclusive-or gate XOR4 serves as a low level output end of the shift circuit, and an output end of the fourth exclusive-or gate XOR4 is connected to a second input end of the third exclusive-or gate XOR 3; the source electrode of the seventh PMOS transistor MP7, the source electrode of the eighth PMOS transistor MP8, the source electrode of the ninth PMOS transistor MP9, and the source electrode of the tenth PMOS transistor MP10 are all connected to the VB voltage terminal, the gate electrode of the seventh PMOS transistor MP7 and the gate electrode of the eighth PMOS transistor MP8 are all connected to the second interlock signal terminal, the drain electrode of the seventh PMOS transistor MP7 is connected to the drain electrode of the seventh NMOS transistor MN7, the drain electrode of the eighth PMOS transistor MP8 is connected to the drain electrode of the eighth NMOS transistor MN8, the gate electrode of the ninth PMOS transistor MP9 is connected to the output terminal of the fourth XOR gate 4, the drain electrode of the ninth PMOS transistor MP9 is connected to the drain electrode of the ninth NMOS transistor MN9, the gate electrode of the tenth PMOS transistor MP10 is connected to the output terminal of the third XOR gate 3, and the drain electrode of the tenth PMOS transistor MP10 is connected to the drain electrode of the tenth NMOS transistor MN 10.
An input end of the eighth not gate INV8 and the seventh not gate INV7 is connected to the drain of the tenth PMOS transistor MP10, an output end of the eighth not gate INV8 and the seventh not gate INV7 is connected to the second input end of the fourth exclusive or gate XOR4, an input end of the ninth not gate INV9 is connected to the drain of the ninth NMOS transistor MN9, and an output end of the ninth not gate INV9 is connected to the first input end of the third exclusive or gate XOR 3.
When the shift circuit is used as a low level shift circuit, the feedback terminal is grounded, and the third input terminal of the low level shift circuit (in FIG. 5)
Figure BDA0003802931080000107
) The OUT _ H end of the adaptive dead zone circuit and the fourth input end of the low level shift circuit (in figure 5)
Figure BDA0003802931080000106
) The end of OUT _ L of the self-adaptive dead zone circuit is connected with the C \ of the low level shift circuit
Figure BDA0003802931080000108
And is connected with the input end of the second output stage driving circuit. When the shift circuit is used as a high level shift circuit, the feedback end is connected with the VS end, the first input end (Set in figure 5) of the high level shift circuit is connected with the OUT _ H end of the adaptive dead zone circuit, the second input end (Reset in figure 5) of the low level shift circuit is connected with the OUT _ L end of the adaptive dead zone circuit, and the C _ OUT end of the high level shift circuit is connected with the input end of the first output stage drive circuit.
In this embodiment, the shift circuit is composed of a level shift circuit, a common mode noise cancellation circuit, and a dual interlock circuit. The input signals of the level shift circuit are two narrow pulse signals generated by the pulse generating circuit, the common mode noise eliminating circuit is used for filtering common mode quantity in transient noise, and the double interlocking circuit is used for filtering differential mode quantity introduced by process deviation in the noise. Because no RC filter circuit is used, the delay characteristic of the structure overcomes the defects of the traditional transient noise suppression circuit, and breaks through the contradiction between the delay and the transient noise suppression capability of the traditional level shift circuit. Reset and Set correspond to the input signals HI or LI of the level shift circuit part, and BiasP and BiasN are connected with the interlock signal.
As shown in fig. 6, initial stage (t 0 to t 1): IN the initial state, the IN signal is kept at a low level, so Reset = '0' and Set = '0' exist, the initial state of the C _ OUT is Set to be a low level by using the power-on Reset circuit, and the C _ OUT is kept under the action of the second-stage interlock
Figure BDA0003802931080000101
Figure BDA0003802931080000102
Thereby maintaining C _ OUT at a low level. Opening stage (t 1 to t 2): when the IN signal goes high and a rising edge is generated, the pulse generation circuit outputs a SET narrow pulse signal at the SET end, and at this time SET = '1' and Reset = '0', the pull-down capability of the sixth NMOS transistor MN6 is stronger than the current capability of the seventh PMOS transistor MP7 of the current source on the ninth not gate INV9 IN the second-stage interlock structure, so that the sixth NMOS transistor MN6 can be driven to generate a high-voltage pulse
Figure BDA0003802931080000103
The pull-up capability of the seventh PMOS transistor MP7 is stronger than the current capability of an eighth NMOS transistor MN8 below an eighth NOT gate INV8 and a seventh NOT gate INV7 in the second-stage interlocking structure, so that the current capability of the seventh PMOS transistor MP7 is higher than that of the eighth NMOS transistor MN8 below the eighth NOT gate INV8 and the seventh NOT gate INV7 in the second-stage interlocking structure
Figure BDA0003802931080000104
Eventually causing C _ OUT to go high.
IN the latch stage (t 2-t 3), the duration of the narrow pulse signal generated by the pulse generating circuit IN is completed, and the Set signal is Set to low level, i.e., set = '0' and Reset = '0'. At this time, the third PMOS transistor MP3 to the sixth PMOS transistor MP6 are turned off, and the third NMOS transistor MN3 to the sixth NMOS transistor MN6 are turned off. For the
Figure BDA0003802931080000105
Under the combined action of the ninth not gate INV9 and the current source seventh NMOS transistor MN7 in the second-stage interlocking structure,
Figure BDA0003802931080000111
the voltage is maintained at a low level, and the voltage overshoot in the t2 phase is caused by the turn-off process of the sixth NMOS transistor MN 6. For the
Figure BDA0003802931080000112
The signal, under the combined action of an eighth NOT gate INV8, a seventh NOT gate INV7 and a current source eighth PMOS tube MP8 in the second-stage interlocking structure,
Figure BDA0003802931080000113
the voltage is maintained at high level, and the voltage spike in the t2 stage is caused by the turn-off process of the third PMOS transistor MP 3.
And a closing stage (t 3-t 4) IN which the IN signal changes from high level to low level to generate a falling edge, the pulse generating circuit outputs a narrow pulse signal at the RESET end, the LDMOS grid electrode state is Set = '0' and RESET = '1', and the pull-down capability of the ninth NMOS transistor MN9 is stronger than the current capability of the eighth PMOS transistor MP8 at the upper end of the seventh NOT transistor INV7 of the eighth-stage interlocking structure
Figure BDA0003802931080000114
The pull-up capability of the sixth PMOS transistor MP6 is stronger than the current capability of the seventh NMOS transistor MN7 in which the ninth NOT gate INV9 is connected in series in the second-stage interlocking structure, so that the current capability of the sixth NMOS transistor MP6 is stronger than that of the seventh NMOS transistor MN7 in which the ninth NOT gate INV9 is connected in series in the second-stage interlocking structure
Figure BDA0003802931080000115
Eventually making C _ OUT low. the working process after t4 is the same as that of the latch stage, wherein the t4 stage
Figure BDA0003802931080000116
The overshoot of the t4 stage-R-is caused by the turn-off of the seventh NMOS transistor MN 7.
As shown in fig. 7, in an embodiment, the output stage driving circuit includes a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, and a fourteenth NMOS transistor MN14; the source electrode of the twelfth PMOS tube MP12, the source electrode of the thirteenth PMOS tube MP13 and the source electrode of the fourteenth PMOS tube MP14 are all connected with the power supply end of the output stage driving circuit, and the source electrode of the twelfth NMOS tube MN12, the source electrode of the thirteenth NMOS tube MN13 and the source electrode of the fourteenth NMOS tube MN14 are all grounded; the gate of the twelfth PMOS transistor MP12 and the gate of the twelfth NMOS transistor MN12 are connected to a first connection point, the first connection point is used as an input end of the output stage driving circuit, the drain of the twelfth PMOS transistor MP12 and the drain of the twelfth NMOS transistor MN12 are connected to a second connection point, the gate of the thirteenth PMOS transistor MP13 and the gate of the thirteenth NMOS transistor MN13 are connected to a third connection point, the thirteenth connection point is connected to the twelfth connection point, the drain of the thirteenth PMOS transistor MP13 and the drain of the thirteenth NMOS transistor MN13 are connected to a fourth connection point, the gate of the fourteenth PMOS transistor MP14 and the gate of the fourteenth NMOS transistor MN14 are connected to a fifth connection point, the fifth connection point is connected to the fourth connection point, the fifth connection point is used as an output end of the output stage driving circuit, the source of the fourteenth PMOS transistor MP14 and the drain of the fourteenth NMOS transistor MN14 are connected to a sixth connection point, and the sixth connection point is connected to the third connection point.
In this embodiment, when the input Vin is at a low level, the twelfth PMOS transistor MP12, the fourteenth PMOS transistor MP14, and the thirteenth NMOS transistor MN13 are turned on, and the thirteenth PMOS transistor MP13, the twelfth NMOS transistor MN12, and the fourteenth NMOS transistor MN14 are turned off. When Vin begins to rise to the threshold voltage of the NMOS transistor, the twelfth NMOS transistor MN12 is turned on slowly, but the currents of the twelfth PMOS transistor MP12 and the fourteenth PMOS transistor MP14 are much larger than the current of the twelfth NMOS transistor MN12, until the current capability of the twelfth NMOS transistor MN12 is equal to the sum of the current capabilities of the twelfth PMOS transistor MP12 and the fourteenth PMOS transistor MP14, vin reaches the forward flip threshold. Similarly, when Vin is inverted from high level to low level, vin reaches the reverse threshold of the schmitt trigger if and only if the current capability of the twelfth PMOS transistor MP12 is equal to the sum of the current capabilities of the twelfth NMOS transistor MN12 and the fourteenth NMOS transistor MN14 which are turned off.
In an embodiment, the driving circuit of the gallium nitride power device further includes two under-voltage protection circuits, the two under-voltage protection circuits are respectively recorded as a first under-voltage protection circuit and a second under-voltage protection circuit, an input end of the first under-voltage protection circuit is connected with a low level output end of the high level shift circuit, an output end of the first under-voltage protection circuit is connected with a second interlock signal end of the high level shift circuit, an input end of the second under-voltage protection circuit is connected with a low level output end of the low level shift circuit, and an output end of the second under-voltage protection circuit is connected with a first interlock signal end of the low level shift circuit. When the power supply voltage drops to 2.5V, the detection circuit detects that the voltage division value of the power supply voltage is lower than the reference voltage, and undervoltage protection is output, so that the whole circuit is in a protection state. And the circuit is restarted until the voltage returns to normal.
As shown in fig. 8, in one embodiment, the undervoltage protection circuit includes a comparator, a first RS flip-flop RS1, a second RS flip-flop RS2, a current-frequency oscillator, a first frequency divider, a second frequency divider, a first D flip-flop DFF1, a second D flip-flop DFF2, a second NOR gate NOR2, a first exclusive NOR gate XNOR1, a fourth NAND gate NAND4, AND a first AND gate AND1.
The first input end of the comparator is connected with a VDD voltage end, the second input end of the comparator is connected with the low-level output end of the shift circuit, and the output end of the comparator is respectively connected with the S end of the first RS trigger RS1, the Reset end of the first frequency divider, the Reset end of the first D trigger DFF1, the second input end of the second NOR gate NOR2, the first input end of the first XOR gate XNOR1 and the first input end of the fourth NAND gate NAND 4; the output end of the first RS trigger RS1 is connected with the input end of a current-frequency oscillator, and the output end of the current-frequency oscillator is respectively connected with the CLK end of a first frequency divider and the CLK end of a second frequency divider; the output terminal of the first frequency divider is connected to the CLK terminal of a first D flip-flop DFF1, the CLK terminal of the first D flip-flop DFF1
Figure BDA0003802931080000121
The terminal is connected to a first input terminal of a second NOR gate NOR2, and an output terminal of the second NOR gate NOR2 is connected to an S terminal of a second RS flip-flop RS 2.
The output terminal of the second frequency divider is connected to the CLK terminal of a second D flip-flop DFF2, the second D flip-flop DFF2
Figure BDA0003802931080000122
The end of the first exclusive nor gate XNOR1 is connected with the second input end of the first exclusive nor gate XNOR1, AND the output end of the first exclusive nor gate XNOR1 is connected with the first input end of the first AND gate AND 1; a second input end of the first AND gate AND1 is connected with an output end of a fourth NAND gate NAND4, AND a second input end of the fourth NAND gate NAND4 is respectively connected with a Reset end of the second frequency divider AND a Reset end of the second D flip-flop DFF 2; the output end of the first AND gate AND1 is connected with the R end of the first RS flip-flop RS1 AND the R end of the second RS flip-flop RS2, respectively, the output end of the second RS flip-flop RS2 is connected with the second input end of the fourth NAND gate NAND4, AND the output end of the second RS flip-flop RS2 serves as the output end of the under-voltage protection circuit.
When the undervoltage protection circuit is connected with the high level shift circuit, the output end of the undervoltage protection circuit is connected with a second interlocking signal end (BiasP) of the high level shift circuit; when the undervoltage protection circuit is connected with the low level shift circuit, the output end of the undervoltage protection circuit is connected with a first interlocking signal end (BiasN) of the low level shift circuit. The undervoltage protection circuit adopted by the embodiment has undervoltage filtering and fault recovery. When the VDD voltage drops to 2.5V, the comparator detects that the divided voltage value of the power voltage is lower than the reference voltage, so that a high level signal is output at a point A, meanwhile, the first RS trigger is set, and a high level enabling signal is output at a point B, so that the current-frequency oscillator starts to work. When the power voltage is recovered to 5V from 2.5V, no signal is output at the point D, which indicates that the undervoltage time does not reach the filtering width of the undervoltage filtering, and at the moment, the circuit judges that the chip is not in an abnormal working state, and outputs a falling edge signal at the point E to close the current-frequency oscillator. There is no change from point F (i.e., the output signal of the under-voltage protection) to point F.
The first frequency divider and the second frequency divider are composed of a plurality of D triggers triggered by rising edges, the output frequency of each D trigger is halved, the period is changed to 2 times of the original period, and the total period is equivalent to the increment of the current-frequency oscillator based on the period with the exponential power of 2. The significance of the frequency divider is that the filtering time is inversely proportional to the change of the power supply voltage, and more, the fault recovery circuit of most of driving circuits needs millisecond-level delay, if the RC delay is used alone, the RC delay occupies a large chip area, and the mode of the oscillator and the frequency divider can effectively generate accurate delay, and the area of the chip can be greatly reduced on the premise of higher and higher integration level of the existing transistor.
The foregoing is illustrative of the preferred embodiments of this invention, and it is to be understood that the invention is not limited to the precise form disclosed herein and that various other combinations, modifications, and environments may be resorted to, falling within the scope of the concept as disclosed herein, either as described above or as apparent to those skilled in the relevant art. And that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (9)

1. A driving circuit of a gallium nitride power device is characterized by comprising a high-level input end, a low-level input end, a driving output end, a VDD voltage end, a VB voltage end, a Vs end, an input-stage driving circuit, a self-adaptive dead zone circuit, two shifting circuits, two output-stage driving circuits, a negative-pressure detection circuit, a first resistor, a second resistor, a third resistor, a fourth resistor, an eleventh PMOS (P-channel metal oxide semiconductor) tube and an eleventh NMOS (N-channel metal oxide semiconductor) tube, wherein the two output-stage driving circuits comprise a first output-stage driving circuit and a second output-stage driving circuit, and the two shifting circuits comprise a high-level shifting circuit and a low-level shifting circuit;
the first input end of the input stage driving circuit is connected with the high-level input end, the second input end of the input stage driving circuit is connected with the low-level input end, the high-level output end of the input stage driving circuit is connected with the high-level input end of the self-adaptive dead zone circuit, and the low-level output end of the input stage driving circuit is connected with the low-level input end of the self-adaptive dead zone circuit;
the high level output end of the self-adaptive dead zone circuit is connected with the second input end of the high level shift circuit and the fourth input end of the low level shift circuit, and the low level output end of the self-adaptive dead zone circuit is connected with the first input end of the high level shift circuit and the third input end of the low level shift circuit; the high level output end of the high level shift circuit is connected with the input end of the first output stage drive circuit, and the low level output end of the low level shift circuit is connected with the input end of the second output stage drive circuit;
the high level output end of the first output stage driving circuit is connected with the grid electrode of an eleventh PMOS tube through a first resistor, and the low level output end of the first output stage driving circuit is connected with the grid electrode of the eleventh PMOS tube through a second resistor; the high level output end of the second output stage driving circuit is connected with the grid electrode of an eleventh NMOS tube through a third resistor, and the low level output end of the second output stage driving circuit is connected with the grid electrode of the eleventh NMOS tube through a fourth resistor; the drain electrode of the eleventh PMOS tube is connected with power supply voltage, the source electrode of the eleventh PMOS tube is connected with the drain electrode of the eleventh NMOS tube, the source electrode of the eleventh NMOS tube is grounded, and the connecting point of the source electrode of the eleventh PMOS tube and the drain electrode of the eleventh NMOS tube is connected with the driving output end;
the input end of the negative voltage detection circuit is connected with the Vs end, the Vs end is connected with the driving output end, the output end of the negative voltage detection circuit is connected with the control end of the self-adaptive dead zone circuit, the power end of the high-voltage level shift circuit and the power end of the first output stage driving circuit are connected with the VB voltage end, and the power end of the input stage driving circuit, the power end of the low-voltage level shift circuit and the power end of the second output stage driving circuit are connected with the VDD voltage end.
2. The driving circuit of claim 1, further comprising a clamp protection circuit, wherein a first control terminal of the clamp protection circuit is connected to the VB voltage terminal, an output terminal of the clamp protection circuit is connected to the clamp protection terminal of the high level shifter, an output terminal of the negative voltage detection circuit is connected to a second control terminal of the clamp protection circuit, and a power supply terminal of the clamp protection circuit is connected to the VDD voltage terminal.
3. The driving circuit of a gan power device according to claim 1, wherein the input stage driving circuit comprises a first nor gate, a first nand gate, a first not gate, a second not gate, a third not gate, a fourth not gate and a fifth not gate; the first input end of the first NAND gate is used as the high-level input end of the input-stage driving circuit, the output end of the first NAND gate is connected with the input end of a first NOT gate, the output end of the first NOT gate is connected with the input end of a second NOT gate, the output end of the second NOT gate is connected with the input end of a third NOT gate, the output end of the third NOT gate is connected with the first input end of a first NOR gate, and the output end of the third NOT gate is used as the high-level output end of the input-stage driving circuit; the second input end of the first nor gate is used as the low level input end of the input stage driving circuit, the output end of the first nor gate is connected with the input end of the fourth not gate, the output end of the fourth not gate is connected with the input end of the fifth not gate, the output end of the fifth not gate is connected with the second input end of the first nand gate, and the output end of the fifth not gate is used as the low level output end of the input stage driving circuit.
4. The driving circuit of a gan power device according to claim 1, wherein the adaptive dead-band circuit comprises a sixth not gate, a seventh not gate, a second nand gate, a third nand gate, a first xor gate, a second xor gate, a first dynamic delay unit and a second dynamic delay unit;
the input end of the sixth not gate is used as the high-level input end of the adaptive dead-zone circuit, the output end of the sixth not gate is connected with the first input end of the second not gate and the first input end of the first exclusive-or gate, the input end of the first dynamic delay unit is connected with the input end of the sixth not gate, the output end of the first dynamic delay unit is connected with the second input end of the first exclusive-or gate, and the output end of the first exclusive-or gate is connected with the first input end of the third not gate;
the input end of the seventh not gate is used as the low level input end of the adaptive dead zone circuit, the output end of the seventh not gate is connected with the second input end of the second exclusive-or gate and the second input end of the third nand gate, the input end of the second dynamic delay unit is connected with the input end of the seventh not gate, the output end of the second dynamic delay unit is connected with the first input end of the second exclusive-or gate, the output end of the second exclusive-or gate is connected with the second input end of the second nand gate, and the output end of the third nand gate is used as the high level output end of the adaptive dead zone circuit.
5. The driving circuit of a gan power device as claimed in claim 1, wherein the level shifting circuit is a dual interlock level shifting circuit.
6. The driving circuit of a gan power device according to claim 5, wherein the shift circuit comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a first diode, a second diode, a third exclusive or gate, a fourth exclusive or gate, an eighth not gate, a ninth not gate, a first interlock signal terminal, a second interlock signal terminal and a feedback terminal;
the grid electrode of the first NMOS tube is used as a first input end of the shift circuit, the source electrode of the first NMOS tube is grounded, the grid electrode of the second NMOS tube is used as a second input end of the shift circuit, and the source electrode of the second NMOS tube is grounded; the grid electrode of the third NMOS tube is connected with the grid electrode of the fourth NMOS tube, the grid electrode of the fourth NMOS tube is connected with the drain electrode of the fourth NMOS tube, the grid electrode of the fifth NMOS tube is connected with the grid electrode of the sixth NMOS tube, the grid electrode of the fifth NMOS tube is connected with the drain electrode of the fifth NMOS tube, and the source electrode of the third NMOS tube, the source electrode of the fourth NMOS tube, the source electrode of the fifth NMOS tube, the source electrode of the sixth NMOS tube, the source electrode of the seventh NMOS tube, the source electrode of the eighth NMOS tube, the source electrode of the ninth NMOS tube and the source electrode of the tenth NMOS tube are all connected with the feedback end; the grid electrode of the seventh NMOS tube, the grid electrode of the eighth NMOS tube, the grid electrode of the ninth NMOS tube and the grid electrode of the tenth NMOS tube are all connected with a first interlocking signal end;
the anode of the first diode and the anode of the second diode are both connected with the feedback end, the cathode of the first diode is connected with the drain electrode of the first NMOS tube, and the cathode of the second diode is connected with the drain electrode of the second NMOS tube;
the grid electrode of the first PMOS tube is used as a third input end of the shift circuit, the grid electrode of the second PMOS tube is used as a fourth input end of the shift circuit, the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube, and the grid electrode of the first PMOS tube, the grid electrode of the third PMOS tube and the grid electrode of the fourth PMOS tube are all connected with the drain electrode of the first PMOS tube; the drain electrode of the second PMOS tube is connected with the drain electrode of the second PMOS tube, and the drain electrode of the second PMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the sixth PMOS tube are connected with the grid electrode of the second PMOS tube; the source electrode of the first PMOS tube, the source electrode of the second PMOS tube, the source electrode of the third PMOS tube, the source electrode of the fourth PMOS tube, the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube are all connected with the VDD voltage end; the drain electrode of the third PMOS tube is connected with the drain electrode of the third NMOS tube, the drain electrode of the fourth PMOS tube is connected with the drain electrode of the fifth NMOS tube, the drain electrode of the fifth PMOS tube is connected with the drain electrode of the fourth NMOS tube, and the drain electrode of the sixth PMOS tube is connected with the drain electrode of the sixth NMOS tube;
a first input end of the third exclusive-or gate is connected with a drain electrode of a sixth PMOS transistor, an output end of the third exclusive-or gate is used as a high level output end of the shift circuit, a first input end of the fourth exclusive-or gate is connected with an output end of the third exclusive-or gate, a second input end of the fourth exclusive-or gate is connected with a drain electrode of a third NMOS transistor, an output end of the fourth exclusive-or gate is used as a low level output end of the shift circuit, and an output end of the fourth exclusive-or gate is connected with a second input end of the third exclusive-or gate; the source electrode of the seventh PMOS tube, the source electrode of the eighth PMOS tube, the source electrode of the ninth PMOS tube and the source electrode of the tenth PMOS tube are all connected with a VB voltage end, the grid electrode of the seventh PMOS tube and the grid electrode of the eighth PMOS tube are all connected with a second interlocking signal end, the drain electrode of the seventh PMOS tube is connected with the drain electrode of the seventh NMOS tube, the drain electrode of the eighth PMOS tube is connected with the drain electrode of the eighth NMOS tube, the grid electrode of the ninth PMOS tube is connected with the output end of the fourth exclusive-OR gate, the drain electrode of the ninth PMOS tube is connected with the drain electrode of the ninth NMOS tube, the grid electrode of the tenth PMOS tube is connected with the output end of the third exclusive-OR gate, and the drain electrode of the tenth PMOS tube is connected with the drain electrode of the tenth NMOS tube;
the input end of the eighth not gate is connected with the drain electrode of the tenth PMOS tube, the output end of the eighth not gate is connected with the second input end of the fourth exclusive-OR gate, the input end of the ninth not gate is connected with the drain electrode of the ninth NMOS tube, and the output end of the ninth not gate is connected with the first input end of the third exclusive-OR gate.
7. The driving circuit of a gan power device according to claim 1, wherein the output stage driving circuit comprises a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor; the source electrode of the twelfth PMOS tube, the source electrode of the thirteenth PMOS tube and the source electrode of the fourteenth PMOS tube are all connected with the power supply end of the output stage driving circuit, and the source electrode of the twelfth NMOS tube, the source electrode of the thirteenth NMOS tube and the source electrode of the fourteenth NMOS tube are all grounded; the grid electrode of the twelfth PMOS tube and the grid electrode of the twelfth NMOS tube are connected to a first connection point, the first connection point is used as the input end of the output stage driving circuit, the drain electrode of the twelfth PMOS tube and the drain electrode of the twelfth NMOS tube are connected to a second connection point, the grid electrode of the thirteenth PMOS tube and the grid electrode of the thirteenth NMOS tube are connected to a third connection point, the thirteenth connection point is connected to the twelfth connection point, the drain electrode of the thirteenth PMOS tube and the drain electrode of the thirteenth NMOS tube are connected to a fourth connection point, the grid electrode of the fourteenth PMOS tube and the grid electrode of the fourteenth NMOS tube are connected to a fifth connection point, the fifth connection point is connected to the fourth connection point, the fifth connection point is used as the output end of the output stage driving circuit, the source electrode of the fourteenth PMOS tube and the drain electrode of the fourteenth NMOS tube are connected to the sixth connection point, and the sixth connection point is connected to the third connection point.
8. The driving circuit of a gan power device according to claim 1, wherein the driving circuit of a gan power device further comprises two under-voltage protection circuits, the two under-voltage protection circuits are respectively marked as a first under-voltage protection circuit and a second under-voltage protection circuit, an input terminal of the first under-voltage protection circuit is connected with a low level output terminal of the high level shift circuit, an output terminal of the first under-voltage protection circuit is connected with a second interlock signal terminal of the high level shift circuit, an input terminal of the second under-voltage protection circuit is connected with a low level output terminal of the low level shift circuit, and an output terminal of the second under-voltage protection circuit is connected with a first interlock signal terminal of the low level shift circuit.
9. The driving circuit of a gan power device according to claim 8, wherein the under-voltage protection circuit comprises a comparator, a first RS flip-flop, a second RS flip-flop, a current-frequency oscillator, a first frequency divider, a second frequency divider, a first D flip-flop, a second nor gate, a first xor gate, a fourth nand gate and a first and gate;
the first input end of the comparator is connected with a VDD voltage end, the second input end of the comparator is connected with the low-level output end of the shift circuit, and the output end of the comparator is respectively connected with the S end of the first RS trigger, the Reset end of the first frequency divider, the Reset end of the first D trigger, the second input end of the second NOR gate, the first input end of the first XOR gate and the first input end of the fourth NAND gate; the output end of the first RS trigger is connected with the input end of a current-frequency oscillator, and the output end of the current-frequency oscillator is respectively connected with the CLK end of the first frequency divider and the CLK end of the second frequency divider; said-
The output end of the first frequency divider is connected with the CLK end of the first D flip-flop, the Q end of the first D flip-flop is connected with the first input end of the second NOR gate, and the output end of the second NOR gate is connected with the S end of the second RS flip-flop;
the output end of the second frequency divider is connected with the CLK end of a second D flip-flop, the Q end of the second D flip-flop is connected with the second input end of a first exclusive-OR gate, and the output end of the first exclusive-OR gate is connected with the first input end of a first AND gate; the second input end of the first AND gate is connected with the output end of a fourth NAND gate, and the second input end of the fourth NAND gate is respectively connected with the Reset end of the second frequency divider and the Reset end of the second D trigger; the output end of the first and gate is connected with the R end of the first RS trigger and the R end of the second RS trigger respectively, the output end of the second RS trigger is connected with the second input end of the fourth NAND gate, and the output end of the second RS trigger is used as the output end of the undervoltage protection circuit.
CN202210991983.4A 2022-08-17 2022-08-17 Driving circuit of gallium nitride power device Pending CN115459752A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116191842A (en) * 2023-04-25 2023-05-30 广东汇芯半导体有限公司 High-voltage integrated circuit
CN116995938A (en) * 2023-09-26 2023-11-03 四川航天职业技术学院(四川航天高级技工学校) DC-DC conversion circuit capable of automatically equalizing voltage

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116191842A (en) * 2023-04-25 2023-05-30 广东汇芯半导体有限公司 High-voltage integrated circuit
CN116191842B (en) * 2023-04-25 2023-07-25 广东汇芯半导体有限公司 High-voltage integrated circuit
CN116995938A (en) * 2023-09-26 2023-11-03 四川航天职业技术学院(四川航天高级技工学校) DC-DC conversion circuit capable of automatically equalizing voltage

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