CN115455876A - Method for debugging logic system design and electronic equipment - Google Patents
Method for debugging logic system design and electronic equipment Download PDFInfo
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- CN115455876A CN115455876A CN202211150883.5A CN202211150883A CN115455876A CN 115455876 A CN115455876 A CN 115455876A CN 202211150883 A CN202211150883 A CN 202211150883A CN 115455876 A CN115455876 A CN 115455876A
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Abstract
The application relates to the technical field of computer application, and particularly discloses a method and electronic equipment for debugging logic system design, wherein the method comprises the following steps: receiving an instruction for selecting a debugging object in a graphical debugging tool, wherein the debugging object comprises one or more design elements; determining a characterization of the one or more design elements; and generating a graphic window in the debugging tool according to the characteristic description, wherein the graphic window is used for displaying the information of the one or more design elements in the dragging operation. The method and the device display the information of one or more design elements of the selected debugging object in the dragging operation through the graphical interface, so that a user can conveniently judge whether the currently selected debugging object comprises the design elements needing debugging or not, the user can adjust the selected debugging object, unnecessary operations of dragging a function window to check signals are reduced, the debugging efficiency is improved, and the time cost of the user is reduced.
Description
Technical Field
The present application relates to the field of computer application technologies, and in particular, to a method and an electronic device for debugging a logic system design.
Background
Before the logic system design is put into actual operation, the compiled logic system design needs to be operated and debugged, and the logic system design is found to be abnormal in the debugging process. Further diagnosis is needed for the discovered abnormalities, the cause and the specific source position of the abnormalities are found, and correction is performed to ensure the robustness of the logic system design. In the process of designing and debugging a logic system, many functions are involved, such as waveform debugging, coverage rate debugging, source code debugging and circuit schematic diagram debugging, and the debugging functions are usually operated independently.
In the related art, a user needs to repeatedly check a schematic diagram, a waveform diagram, source code, coverage rate, etc. of a logic system design at different ranges (e.g., one signal, one circuit module, one piece of code, etc.) during debugging of the logic system design. Therefore, a user needs to modify the selected range for many times, continuously drags the selected range to the function window to check the signal, and may need to try many times to obtain the part of the signal which the user wants to debug, so that the debugging efficiency is limited.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a method, an electronic device and a readable storage medium for debugging a logic system design.
In a first aspect, the present application provides a method for debugging a logic system design. The method comprises the following steps: receiving an instruction for selecting a debugging object in a graphical debugging tool, wherein the debugging object comprises one or more design elements; determining a characterization of the one or more design elements; and generating a graphic window in the debugging tool according to the characteristic description, wherein the graphic window is used for displaying the information of the one or more design elements in the dragging operation.
In a second aspect, the application further provides an electronic device. The electronic device includes a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions to cause the electronic device to perform the method according to the first aspect.
In a third aspect, the present application also provides a non-transitory computer-readable storage medium storing a set of instructions of a computer for, when executed, causing the computer to perform the method according to the first aspect.
The method, the electronic device and the readable storage medium for debugging the logic system design at least have the following advantages that:
the method and the device display the information of one or more design elements of the selected debugging object in the dragging operation through the graphical interface, and can determine the design elements included in the debugging object before dragging the debugging object to the function window to check the signal according to the information, so that a user can conveniently judge whether the currently selected debugging object includes the design elements needing debugging, the user can adjust the selected debugging object, unnecessary operation of dragging the function window to check the signal is reduced, the debugging efficiency is improved, and the time cost of the user is reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 shows a schematic diagram of a host according to an embodiment of the application;
FIG. 2 shows a schematic diagram of a commissioning tool according to an embodiment of the present application;
FIG. 3 shows a schematic diagram of a graphical interface of a debugging tool according to an embodiment of the present application;
FIG. 4 shows a source code region diagram of a debugging tool according to an embodiment of the present application;
FIG. 5 shows a schematic diagram of a method for debugging a logic system design according to an embodiment of the application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the application, as detailed in the appended claims. The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the presence of additional identical or equivalent elements in processes, methods, articles, or apparatus that include the recited elements is not excluded. For example, if the terms first, second, etc. are used to denote names, they do not denote any particular order. "connected," and like terms, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising," "includes" or "including," etc., specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and/or" includes any and all combinations of the associated listed items.
As described above, in the simulation debugging process, there are cases that a schematic diagram, a waveform diagram, source code, coverage rate, and the like of a logic system design need to be repeatedly checked in different ranges (for example, one signal, one circuit module, one section of code, and the like), however, during the simulation debugging, a user needs to modify a selected range for many times, and drag the selected range to a function window to check a signal continuously, and may need to try many times to obtain a part of signals that the user wants to debug, so that the debugging efficiency is limited. The method for debugging the logic system design provided by the embodiment of the application can be applied to simulation debugging occasions. By adopting the method provided by the embodiment of the application, the simulation debugging efficiency can be improved to a certain extent.
Specifically, simulation testing is the application of various stimuli to a logic system design on a host computer running a simulation test system to detect whether the logic system design can perform a predetermined function.
Fig. 1 shows a schematic diagram of a host 100 according to an embodiment of the application. The host computer 100 may be an electronic device running a simulation test system. As shown in fig. 1, the host 100 may include: a processor 102, a memory 104, a network interface 106, a peripheral interface 108, and a bus 110. Wherein processor 102, memory 104, network interface 106, and peripheral interface 108 are communicatively coupled to each other within the host via bus 110.
The processor 102 may be a Central Processing Unit (CPU), an image processor, a neural Network Processor (NPU), a Microcontroller (MCU), a programmable logic device, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), or one or more Integrated circuits. The processor 102 may be used to perform functions associated with the techniques described herein. In some embodiments, processor 102 may also include multiple processors integrated into a single logic component. As shown in FIG. 1, processor 102 may include a plurality of processors 103A, 103B, and 102c.
The memory 104 may be configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). In some embodiments, the simulation test system for simulating a test design may be a computer program stored in memory 104. As shown in fig. 1, the data stored by the memory may include program instructions (e.g., for implementing the methods for debugging a logic system design of the present application) as well as data to be processed (e.g., the memory may store temporary code generated during the compilation process). The processor 102 may also access memory-stored program instructions and data and execute the program instructions to operate on the data to be processed. The memory 104 may include volatile memory devices or non-volatile memory devices. In some embodiments, the memory 104 may include Random Access Memory (RAM), read Only Memory (ROM), optical disks, magnetic disks, hard disks, solid State Disks (SSDs), flash memory, memory sticks, and the like.
The network interface 106 may be configured to provide communications with other external devices to the host 100 via a network. The network may be any wired or wireless network capable of transmitting and receiving data. For example, the network may be a wired network, a local wireless network (e.g., bluetooth, wiFi, near Field Communication (NFC), etc.), a cellular network, the internet, or a combination of the above. It is to be understood that the type of network is not limited to the specific examples described above. In some embodiments, network interface 106 may include any combination of any number of Network Interface Controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, and the like.
Bus 110 may be configured to transfer information between various components of host 100 (e.g., processor 102, memory 104, network interface 106, and peripheral interface 108), such as an internal bus (e.g., processor-memory bus), an external bus (USB port, PCI-E bus), and so forth.
It should be noted that although the host architecture only shows the processor 102, the memory 104, the network interface 106, the peripheral interface 108, and the bus 110, in a specific implementation, the host architecture may also include other components necessary to achieve normal operation. Furthermore, those skilled in the art will appreciate that the above-described host architecture may also include only the components necessary to implement the embodiments of the present application, and need not include all of the components shown in the figures.
FIG. 2 shows a schematic diagram of a debugging tool 200 and a simulation tool 202 according to an embodiment of the application. Debugging tool 200 and simulation tool 202 may be computer programs running on host 100.
In the field of chip design, a design may be simulated using a simulation tool. The simulation tool may be, for example, a GalaxSim simulation tool available from Chihua chapter science and technology, inc. The example simulation tool 202 shown in FIG. 2 may include a compiler 120 and a simulator 220. Compiler 120 may compile a design (e.g., logic system design 210) into object code 204, simulator 220 may simulate from object code 204, and output simulation results 206. A logic system design may include several design elements. For example, the simulation tool 202 may output simulation results (e.g., a simulation waveform diagram) onto an output device (e.g., displayed on a display) via the peripheral interface 108 of fig. 1.
By the method, the debugging environment for debugging the logic system design is constructed, and the logic system design is debugged through the debugging environment. The debug interface may include a plurality of debug regions, each corresponding to a variety of functions, such as the above-described view waveform diagrams, circuit schematics, code, or coverage, among others. In order to facilitate debugging work of a user, the user can debug an object in one debugging area of a debugging interface and drag the object to another debugging area, and a debugging tool can display a waveform diagram, a circuit schematic diagram, a code, a coverage rate and the like corresponding to the debugging object in the other debugging area according to the dragging operation. In actual operation, a debug object selected in one debug area may not be able to activate a corresponding debug function in another debug area. For example, when a selected signal does not have any coverage statistics, the coverage of the signal cannot be viewed even if the signal is dragged to a coverage window. However, it is difficult for the user to know this information when selecting a debug object. Meanwhile, as the debugging object selected by the user and the debugging part needing to be selected by the user often have the conditions of wrong selection range or overlarge or undersize selection range, the user needs to modify the selected range for many times, continuously drag the user to a functional window to check signals, and possibly try many times to obtain the part of signals which the user wants to debug, so that the debugging efficiency is limited, and the time cost of the user is greatly increased.
Based on this, the present application further proposes a method, an electronic device and a storage medium for debugging a logic system design on this basis. By the method, the information of one or more design elements of the selected debugging object in the dragging operation can be displayed through the graphical interface in the debugging process, the design elements included in the debugging object can be determined before the debugging object is dragged to the function window to check the signal according to the information, and a user can conveniently judge whether the currently selected debugging object includes the design elements needing debugging or not, so that the user can adjust the selected debugging object, unnecessary operations of dragging to the function window to check the signal are reduced, the debugging efficiency is improved, and the time cost of the user is reduced.
Next, the present application will explain how to design the debugging tool and how to display the debugging region of the debugging tool.
Fig. 3 shows a schematic diagram of a graphical interface 300 of the debugging tool 200 according to an embodiment of the application. Graphical interface 300 may be displayed on an output device of host 100 (e.g., on a display). In some embodiments, graphical interface 300 of debugging tool 200 includes a plurality of debugging regions corresponding to a plurality of debugging functions. For example, the graphical interface 300 includes a waveform area 310, a circuit schematic area 320, a source code area 330, a coverage area 340, and the like, corresponding to a waveform display function, a circuit schematic display function, a source code display function, a coverage information display function, and the like, respectively. The graphical interface 300 may further include a logic system design framework area 302, where the logic system design framework area 302 may display a code framework (usually displayed in a tree structure) of the logic system design, so as to show the upper and lower hierarchical relationships among the modules of the logic system design, which may further facilitate a user to quickly locate a portion that needs to be debugged.
The circuit schematic area 320 may be used to display the circuit schematic of the selected module. For example, as shown in FIG. 3, a schematic circuit diagram area 320 shows the schematic circuit diagram of the module associated with signals a and b.
The coverage area 340 may be used to display coverage information for the selected signal. For example, as shown in fig. 3, the coverage area 340 shows 40% coverage of signal a and 90% coverage of signal b.
It is understood that graphical interface 300 may include more or less display areas.
The waveform area 310, the schematic circuit area 320, the source code area 330 and the coverage area 340 may be displayed in separate or embedded windows.
The user may select a debugging object in any one of a plurality of display areas (e.g., the waveform area 310, the schematic circuit area 320, the source code area 330, and the coverage area 340) of the graphical interface 300, for example, by means of a mouse, a touch screen, or the like. The debug object may include one or more design elements in the logic system design, which may include a piece of source code, a signal waveform (e.g., of signal a), a signal (e.g., of signal a), a port, or a module of the logic system design. The debug tool 200 may determine a characterization of one or more design elements in the debug object. A characterization may include source code associated with one or more design elements (e.g., a module). That is, the characterization may include code (e.g., object code 204 or source code) in the logic system design that corresponds to the design elements.
The debugging tool 200 can generate a graphical window in the graphical interface 300 according to the feature description of the debugging object, and display information of the design elements in the debugging object in the dragging operation in the graphical window.
Fig. 4 is a schematic diagram illustrating a drag operation of the debugging tool 200 according to an embodiment of the present application.
A schematic diagram of a drag operation in source code region 330 is shown in fig. 4. More specifically, FIG. 4 shows a corresponding graphical window 334 generated by the debugging tool 200 when a debugging object 322 is selected during the drag operation.
The drag operation may refer to a debugging and verifying operation of the user on the graphical interface 300 through the debugging tool 200. The debugging tool 200 may recognize the drag operation and accordingly display corresponding information, such as a waveform diagram, a schematic diagram of a circuit, a code, a coverage rate, etc., in the debugging area having different functions according to the drag operation.
In FIG. 4, the user selected debug object 322 is a piece of source code. For example, the code located in the black shaded area in lines 327-330 of the code is the selected debugging object, and the selected state can also be displayed by using a color block background of other colors. The debug object 322 includes a plurality of design elements, such as a module named u _ e203_ soc _ top, the functions hfextclk (hfclk) and hfxoscnt () included in the module, and the signal hfclk.
The debugging tool 200 may determine the characterization of the design elements described above from the source code of the logic system design to determine the information displayed in the graphical window 334. The information displayed in the graphic window 334 may include the name, attributes, etc. of the design element.
For example, debug tool 200 may determine that module u _ e203_ soc _ top may be displayed in circuit schematic area 320, and thus may determine that module u _ e203_ soc _ top has schematic attributes; the signal hfclk may be displayed in the waveform region 310 (e.g., having a waveform file corresponding to hfclk), so the signal hfclk may be determined to have waveform properties. However, the debug tool 200 may similarly determine that there is no coverage information corresponding to the signal hfclk, and therefore, the signal hfclk does not have a coverage attribute.
Accordingly, the information displayed in the graphics window 334 may include the names of the module u _ e203_ soc _ top and the signal hfclk and their corresponding attributes. The attributes may be displayed in the form of icons, such as the schematic diagram icon and the waveform icon in fig. 4. The box below the debug object in fig. 4 is a graphic window, and the graphic window may also take other shapes, such as a circular frame, a cloud frame, and the like.
In some embodiments, the debug tool 200 may determine the characterization of the design elements described above from keywords in the debug object 322. The debugging tool 200 may extract a keyword of the debugging object, for example, "u _ e203_ soc _ top" and "hfclk" as keywords, and extract a feature description (e.g., source code) corresponding to or related to "u _ e203_ soc _ top" and "hfclk" in the description of the logic system design, thereby determining a feature description of the design element in the debugging object. The debugging tool 200 further performs parsing according to the feature descriptions of "u _ e203_ soc _ top" and "hfclk", and determines that one design element included in the currently selected debugging object is "u _ e203_ soc _ top", which represents one module; another design element is "hfclk," which represents a signal.
In some embodiments, the drag operation may include: clicking on an icon in the graphical window 334, such as the schematic circuit diagram icon and the waveform icon in fig. 4. In this case, the debugging tool 200 may transmit the debugging object 322 to the debugging region corresponding to the clicked icon according to the clicked icon, thereby calling the debugging function. For example, the user has clicked the signal icon corresponding to hfclk, the debugging tool 200 sends the user-selected debugging object 322 to the waveform region 310 corresponding to the signal icon, and the waveform of the signal hfclk is displayed in the waveform region 310. It will be appreciated that sending the debug object 322 to the debug area corresponding to the clicked icon may be just one graphical presentation process for the debug tool 200, and in fact, the debug tool 200 may directly invoke the debug function corresponding to the icon without further determining its debug area. In other embodiments, the drag operation may include: drag debug object 322 from the current debug area (e.g., source code area 330) to other debug areas (e.g., schematic area 320 or waveform area 310) and release the debug object. In this case, the debug tool 200 calls the debug function corresponding to the debug area in the debug area where the debug object 322 is released, according to the debug object 322.
In some embodiments, when the debug object 322 is in the source code region 330 and the debug tool 200 responds to the drag operation, in the case that the schematic diagram area 320 calls the schematic diagram display function according to the debug object 322, specifically, the debug tool 200 may obtain a circuit netlist corresponding to the design elements included in the debug object 322 from the circuit netlist database, where the circuit netlist generally refers to a netlist used for describing the connection relationship between circuit elements. The debugging tool 200 may read the circuit netlist file in the simulation result 206 from the circuit netlist database, and further obtain a circuit netlist corresponding to the design element included in the debugging object 322 according to the name of the design element included in the debugging object 322. The debug tool 200 loads the obtained circuit netlist in the circuit schematic area 320, and displays a circuit schematic corresponding to the circuit netlist in the circuit schematic area 320 according to the circuit netlist.
According to the debugging method and device, the information of one or more design elements of the selected debugging object in the dragging operation is displayed through the graphical interface, the design elements included in the debugging object can be determined before the debugging object is dragged to the function window to check the signal according to the information, and a user can conveniently judge whether the currently selected debugging object includes the design elements needing debugging or not, so that the user can adjust the selected debugging object, unnecessary operation of dragging to the function window to check the signal is reduced, the debugging efficiency is improved, and the time cost of the user is reduced. Meanwhile, by analyzing the debugging attributes (e.g., the circuit diagram of u _ e203_ soc _ top and the waveform of hfclk) corresponding to the debugging object selected by the user, the user can know in advance which debugging functions can be called by the debugging object. The embodiment of the application also allows the user to click the icon in the graphical window 334, which is convenient for the user to quickly call the debugging function.
A method for debugging a logic system design is also provided in some embodiments of the present application.
FIG. 5 shows a schematic diagram of a method 500 for debugging a logic system design, according to an embodiment of the application. Method 500 may be performed by host 100 of fig. 1, and more specifically, may be performed by graphical debugging tool 200 of fig. 2 running on host 100. The method 500 may include the following steps.
At step 510, host 100 may receive an instruction to select a debug object in graphical debug tool 200. The instruction may be an operation in which the user selects a debug object using a mouse. A debug object may refer to, for example, a portion of graphical interface 300 in debug tool 200 that is in a selected state (e.g., debug object 322 in FIG. 4). The debug object may include one or more design elements. In some embodiments, one or more design elements may include a piece of source code, a signal waveform (e.g., the waveform of signal a in FIG. 3), a signal (e.g., signal a in FIG. 3), a port, or a module of a logic system design. In some embodiments, the debug tool 200 includes a plurality of debug regions corresponding to a plurality of debug functions, the plurality of debug functions including at least one of a source code display, a waveform display, a schematic circuit display, or a coverage statistic, for example, the debug regions may include a waveform region 310, a schematic circuit region 320, a source code region 330, and a coverage region 340 as in fig. 3 corresponding to the plurality of debug functions described above. It is understood that host 100 may process the description of the logical system design as object code (e.g., object code 204 in FIG. 2, object code 204 may comprise binary code or RTL code, etc.), and further process the object code of the logical system design.
At step 520, based on the selected debug object, host 100 may determine a characterization of one or more design elements included in the debug object. Where a feature description may include source code associated with one or more design elements, i.e., a feature description may include code (e.g., object code 204 or source code) in a logic system design that corresponds to a design element. In some embodiments, determining the characterization of the one or more design elements further comprises: host 100 may extract the key of the debug object (e.g., "u _ e203_ soc _ top" and "hfclk" of debug object 322 in fig. 4 are keys); and extracting feature descriptions of one or more design elements corresponding to the keywords from the description of the logic system design based on the keywords. The keyword of the debug object may refer to a keyword for characterizing a design element of the debug object, for example, in a case that the design element includes a piece of source code, the keyword may be a code description of a function or a module extracted after the initialization block statement is screened out. In this embodiment, the feature description of the design element in the debug object may be determined by extracting the keyword of the debug object and extracting the feature description corresponding to the keyword according to the description of the keyword in the logic system design.
At step 530, according to the characterization, host 100 may generate a graphical window (e.g., 334 in fig. 4) in debugging tool 200, the graphical window for displaying information of one or more design elements in the drag operation. In some embodiments, the plurality of debugging regions includes a first debugging region and a second debugging region, and the drag operation is used to transfer the selected debugging object from the first debugging region to the second debugging region. For example, the first debugging region and the second debugging region may be any one of the waveform region 310, the schematic circuit diagram region 320, the source code region 330 and the coverage region 340 in fig. 3. The embodiment can realize the dragging operation of the debugging object from the first debugging area and the second debugging area, and display the corresponding debugging function in the second debugging area, thereby meeting the debugging requirements in different occasions, facilitating the debugging of users in different debugging areas and improving the debugging efficiency.
In some embodiments, a graphical window may be used to display the name of one or more design elements and debugging functions corresponding to the one or more design elements. In the embodiment, the name of the design element is displayed in the graphic window, and the debugging function corresponding to the design element is also displayed, so that the user can conveniently indicate which debugging area or areas the debugging object currently selected by the user supports dragging, and the debugging efficiency is further improved. In some embodiments, generating the graphical window in the debugging tool according to the characterization further comprises: the host computer 100 may determine a name of a target design element of the one or more design elements from the characterization; the host 100 may determine, according to the target design element, a candidate debug function corresponding to the target design element, where the debug function corresponding to the target design element includes a debug function that the target design element can call, that is, the target design element has an attribute corresponding to the debug function, for example, the module u _ e203_ soc _ top in fig. 4 has a schematic attribute, and the signal hfclk has a waveform attribute; and displaying the name of the target design element and attribute icons (e.g., a schematic circuit diagram icon and a waveform icon in fig. 4) of the candidate debugging functions in the graphic window, wherein the attribute icons are in one-to-one correspondence with the candidate debugging functions. In the embodiment, the name of the target design element and the corresponding attribute icon of the candidate debugging function are displayed in the image window, so that the debugging object currently selected by the user can be clearly indicated to support the dragging of the debugging object to which debugging area or areas, and the debugging efficiency is further improved.
In some embodiments, the plurality of debugging features includes a first debugging feature corresponding to the first debugging region and a second debugging feature corresponding to the second debugging region. The method 500 may further include the steps of: the host 100 may receive a drag operation; and in response to receiving the drag operation, invoking a second debugging function for the target design element in a second debugging region. In some embodiments, the drag operation comprises: clicking attribute icons of candidate debugging functions; or drag the debug object and release the debug object in the second debug area. For example, clicking on the schematic circuit diagram icon or waveform icon in the graphic window 334 of FIG. 4; or drag the debug object 322 to the circuit schematic area 320 or the waveform area 310. The dragging operation of the embodiment can comprise clicking an attribute icon or dragging a debugging object and releasing the debugging object in the second debugging area, so that not only can a user call a corresponding debugging function by dragging the debugging object to the second debugging area, but also the user can be supported to directly click the attribute icon of a candidate debugging function in the graphic window, a debugging tool calls and displays in the second debugging area according to the debugging function corresponding to the clicked attribute icon, the user can conveniently and accurately call according to different debugging functions, and the debugging efficiency is improved.
In some embodiments, the first debugging region is a source code region, the second debugging region is a schematic circuit region, and invoking the second debugging feature for the target design element in the second debugging region further comprises: the host 100 may obtain a circuit netlist corresponding to the target design element from the circuit netlist database, load the circuit netlist, and display a schematic diagram of the circuit corresponding to the circuit netlist in the second debugging region. In the embodiment, the debugging tool reads the circuit netlist file in the simulation result through the circuit netlist database, and quickly acquires the circuit netlist corresponding to the target design element according to the acquired name of the target design element, so that the efficiency of loading the circuit netlist in the circuit schematic diagram area and displaying the circuit schematic diagram is improved, the generated circuit schematic diagram can be accurately matched with the selected debugging object, and the condition of loading redundancy is avoided.
The method and the device can display the information of one or more design elements of the selected debugging object in the dragging operation through the graphical interface, can determine the design elements included in the debugging object before dragging the debugging object to the function window to check the signal according to the information, and are convenient for a user to judge whether the currently selected debugging object includes the design elements needing debugging, so that the user can adjust the selected debugging object, unnecessary operations of dragging the function window to check the signal are reduced, the debugging efficiency is improved, and the time cost of the user is reduced.
It should be noted that the method of the present application may be executed by a single device, such as a computer or a server. The method of the embodiment can also be applied to a distributed scene and completed by the mutual cooperation of a plurality of devices. In the case of such a distributed scenario, one of the multiple devices may only perform one or more steps of the method of the present application, and the multiple devices interact with each other to complete the method.
It should be understood that, although the steps in the flowcharts related to the embodiments described above are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a part of the steps in the flowcharts related to the embodiments described above may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the execution order of the steps or stages is not necessarily sequential, but may be rotated or alternated with other steps or at least a part of the steps or stages in other steps.
There is also provided in an embodiment of the present application an electronic device, including a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions to cause the electronic device to perform the method 500 provided by the embodiments of the present application.
Embodiments of the present application also provide a non-transitory computer-readable storage medium storing a set of instructions of a computer for causing the computer to perform the method 400 provided by embodiments of the present application when executed. Any reference to memory, database, or other medium used in the embodiments provided herein may include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, high-density embedded nonvolatile Memory, resistive Random Access Memory (ReRAM), magnetic Random Access Memory (MRAM), ferroelectric Random Access Memory (FRAM), phase Change Memory (PCM), graphene Memory, and the like. Volatile Memory can include Random Access Memory (RAM), external cache Memory, and the like. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), among others. The databases referred to in various embodiments provided herein may include at least one of relational and non-relational databases. The non-relational database may include, but is not limited to, a block chain based distributed database, and the like. The processors referred to in the embodiments provided herein may be general purpose processors, central processing units, graphics processors, digital signal processors, programmable logic devices, quantum computing based data processing logic devices, etc., without limitation.
Some embodiments of the present application are described above. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, is limited to these examples; within the context of the present application, features from the above embodiments or from different embodiments may also be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the present application as described above, which are not provided in detail for the sake of brevity.
While the present application has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, other memory architectures, such as Dynamic RAM (DRAM), may use the discussed embodiments.
The present application is intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the application are intended to be included within the scope of the application.
Claims (10)
1. A method for debugging a logic system design, the method comprising:
receiving an instruction for selecting a debugging object in a graphical debugging tool, wherein the debugging object comprises one or more design elements;
determining a characterization of the one or more design elements; and
and generating a graphic window in the debugging tool according to the characteristic description, wherein the graphic window is used for displaying the information of the one or more design elements in the dragging operation.
2. The method of claim 1, wherein the debugging tool comprises a plurality of debugging regions corresponding to a plurality of debugging functions, wherein the plurality of debugging regions comprises a first debugging region and a second debugging region, wherein the dragging operation is used for transferring the selected debugging object from the first debugging region to the second debugging region, and wherein the plurality of debugging functions comprises at least one of source code display, waveform display, schematic circuit display or coverage statistics.
3. The method of claim 2, wherein the one or more design elements comprise a piece of source code, a signal waveform, a signal, a port, or a module of the logic system design, and wherein the graphical window is configured to display a name of the one or more design elements and debugging functionality corresponding to the one or more design elements.
4. The method of claim 3, wherein the characterization includes source code associated with the one or more design elements, the determining the characterization of the one or more design elements further comprising:
extracting keywords of the debugging object; and
and extracting the characteristic description of one or more design elements corresponding to the keywords from the description of the logic system design based on the keywords.
5. The method of claim 3,
the generating a graphical window in the debugging tool according to the feature description further comprises:
determining a name of a target design element of the one or more design elements based on the characterization;
determining candidate debugging functions corresponding to the target design elements according to the target design elements, wherein the debugging functions corresponding to the target design elements comprise debugging functions which can be called by the target design elements; and
and displaying the name of the target design element and the attribute icon of the candidate debugging function in the graphic window.
6. The method of claim 5, wherein the plurality of debugging features includes a first debugging feature corresponding to the first debugging region and a second debugging feature corresponding to the second debugging region, the method further comprising:
receiving the dragging operation; and
in response to receiving the drag operation, invoking the second debugging function for the target design element in the second debugging region.
7. The method of claim 6, wherein the drag operation comprises:
clicking an attribute icon of the candidate debugging function; or
Dragging the debugging object and releasing the debugging object in the second debugging area.
8. The method of claim 6, wherein the first debugging region is a source code region, wherein the second debugging region is a circuit schematic region, and wherein invoking the second debugging feature for the target design element in the second debugging region further comprises:
acquiring a circuit netlist corresponding to the target design element from a circuit netlist database;
loading the circuit netlist; and
and displaying a circuit schematic diagram corresponding to the circuit netlist in the second debugging area.
9. An electronic device, comprising
A memory for storing a set of instructions; and
at least one processor configured to execute the set of instructions to cause the electronic device to perform the method of any of claims 1-8.
10. A non-transitory computer-readable storage medium storing a set of instructions of a computer, the set of instructions, when executed, causing the computer to perform the method of any of claims 1 to 8.
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