CN115441698A - Wave trough locking method and circuit for converter - Google Patents
Wave trough locking method and circuit for converter Download PDFInfo
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- CN115441698A CN115441698A CN202110611862.8A CN202110611862A CN115441698A CN 115441698 A CN115441698 A CN 115441698A CN 202110611862 A CN202110611862 A CN 202110611862A CN 115441698 A CN115441698 A CN 115441698A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
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- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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Abstract
The invention relates to the field of converter design, and provides a trough locking method and a trough locking circuit for a converter. The wave trough locking method reduces the modulation speed of the PFM pulse frequency modulation unit by arranging a hysteresis compensation link behind the error signal; dynamically changing the threshold value and the return difference required by the wave trough switching of the next period by comparing the positions of the opening wave troughs of the current period and the previous period; specifically, if the number of troughs of the current period is increased compared with the number of troughs of the last period, the time threshold for switching troughs of the next period is delayed by one return difference time; if the number of the wave troughs of the current period is less than that of the wave troughs of the previous period, the time threshold value for switching the wave troughs of the next period is advanced by one return difference time. Different wave troughs correspond to different switching thresholds and return differences, so that good locking effect can be realized under different system parameters.
Description
Technical Field
The invention relates to the field of converter design, in particular to a method and a circuit for locking a wave trough in a power converter, and particularly relates to a method and a circuit for dynamically locking the wave trough.
Background
In a Quasi-resonance (QR) control mode, a sine wave trough is judged by detecting the resonance waveform of the voltage of a switching node of the converter, and a power tube is switched on at the trough to reduce the switching loss of the power tube. The reduction of switching losses improves converter efficiency, facilitating its development towards high frequency, miniaturization.
As shown in fig. 1, the waveform of the switching node voltage (i.e. the drain voltage of the power tube) VDS of the typical flyback converter and the power tube gate driving voltage G _ M P And (4) waveform. The switch node voltage VDS is resonated by the excitation inductance and the switch node parasitic capacitance after the demagnetization of the transformer is finished to form a resonant waveform G _ M P At the trough of the resonant waveform going high, N is drivenThe power tube is switched on, and the switching loss of the power tube is minimized.
However, one inherent technical difficulty exists with respect to valley opening control. In fig. 1, the power tube is turned on at the first valley of the resonant waveform in the first period, and the power tube is turned on at the second valley due to slight jitter of the input voltage or the load in the second period; at the moment, the frequency suddenly decreases, and the excitation time of the transformer needs to be prolonged to meet the energy conservation; the increase in excitation time, in turn, causes the controller to reselect the first valley floor to turn on, as shown in the third cycle. If the valley bottom is switched repeatedly at the turn-on time and the switching frequency is within the audio frequency range, the converter will generate abnormal sound and the output voltage will generate low-frequency ripple waves. Therefore, a valley locking technique is needed so that small variations in input voltage or load do not cause repeated switching of the valley opening points.
Common valley locking techniques on the market can be divided into three categories: (1) Within a certain range of the feedback error voltage, the Nth wave trough is fixed to be opened, and the wave trough is switched only when the error voltage jumps out of the set range, such as an Annema chip NCP1342; (2) Detecting the working frequency of the converter, converting the working frequency into voltage through links such as integration, filtering and the like, comparing the voltage with reference voltage, and then determining whether to keep the current wave trough open or select the previous or next wave trough open, such as Chinese patent with application publication number 'CN 108347173A'; (3) The switching threshold is increased by setting the time return difference of the trough switching, such as chinese patent with application publication number "CN 111049388A". These locking techniques are based on fixed comparison thresholds, which are not flexible enough to be specifically set for different converter power parameters.
Disclosure of Invention
In view of the disadvantages that the prior art of trough locking fixes a comparison threshold and the system application is not flexible enough, the invention aims to provide a dynamic trough locking method and a circuit thereof, wherein the locking method and the circuit dynamically change the threshold and the return difference required by trough switching based on each different opening trough, so that no additional design is needed when the system is applied.
The invention provides a wave trough locking method for a converter, which comprises the following steps:
detecting a resonant waveform of a switch node voltage of a power tube of the converter in the current period to obtain the number of troughs of the resonant waveform;
comparing the detected number of the troughs of the current period with the number of the troughs of the previous period;
if the number of the wave troughs of the current period is increased than that of the wave troughs of the previous period, delaying the time threshold value of the wave trough switching by one return difference time in the next period;
if the number of the wave troughs of the current period is less than that of the wave troughs of the previous period, the time threshold value of the wave trough switching is advanced by one return difference time in the next period.
In one embodiment, the time threshold for switching the valley is the time when the rising edge or the falling edge of the valley selection signal for controlling the power tube to be switched on is generated.
In one embodiment, in one period, the return difference time corresponding to a smaller number of troughs is greater than the return difference time corresponding to a larger number of troughs.
In one embodiment, the valley locking method further comprises the step of slowing down the modulation speed of the pulse frequency modulation unit by hysteresis compensating the error signal fed back by the control loop.
The present invention also provides a valley lock circuit for a converter, comprising: the device comprises a pulse frequency modulation unit, a trough detection unit, a dynamic threshold generation unit and a trough selection unit;
the pulse frequency modulation unit is used for generating a wave trough selection signal for controlling the power tube of the converter to be switched on and transmitting the wave trough selection signal to the dynamic threshold generation unit and the wave trough selection unit;
the wave trough detection unit is used for detecting the voltage waveform of a switching node of a power tube of the converter and generating a wave trough mark signal representing the position of a resonance wave trough;
the dynamic threshold generating unit is used for receiving the trough mark signal and the trough selection signal and counting the trough number of the current period according to the trough mark signal; if the number of wave troughs in the current period is increased than that of the wave troughs in the previous period, controlling a wave trough selection signal to delay one return difference time in the next period; if the number of the wave troughs in the current period is less than that of the wave troughs in the previous period, controlling the wave trough selection signal to advance by one return difference time in the next period;
the trough selection unit is used for receiving the trough mark signal and the trough selection signal and outputting a power tube switching-on signal according to the trough mark signal and the trough selection signal.
In one embodiment, the valley locking circuit further comprises a lag compensation unit, wherein an input end of the lag compensation unit is used for inputting the error signal fed back by the control loop and generating a compensation signal with a lag phase relative to the error signal according to the error signal;
the pulse frequency modulation unit receives the compensation signal and modulates the charging current of a capacitor arranged in the pulse frequency modulation unit according to the difference value of the compensation signal and the reference voltage, so that the charging period of the capacitor is changed to generate a trough selection signal.
In one embodiment, the lag compensation unit includes: the circuit comprises a narrow pulse generator, a first switch, a resistor R1, a capacitor C1, a resistor R2, a buffer and a resistor R3; one end of the first switch is connected with the error signal and one end of the second resistor R2, the other end of the first switch is connected with one end of the resistor R1, and the control end of the first switch is connected with the output end of the narrow pulse generator; the other end of the resistor R1 is connected with the positive input end of the buffer and a first polar plate of the capacitor C1; the second plate of the capacitor C2 is grounded; the negative input end of the buffer is connected with the output end of the buffer and one end of the resistor R3; the other end of the resistor R2 is connected with the other end of the resistor R3, and the connection point of the resistor R2 and the resistor R3 is used for outputting a compensation signal.
In one embodiment, the pulse frequency modulation unit includes: the circuit comprises a transconductance amplifier, a capacitor C2, a second switch, a first comparator, an AND gate, a first NOT gate, a high level generator, a first D trigger and a second NOT gate;
the positive input end of the first transconductance amplifier is connected with a compensation signal, the negative input end of the first transconductance amplifier is connected with a first reference voltage, and the output end of the first transconductance amplifier is connected with a first polar plate of a capacitor C2, one end of a second switch and the negative input end of a first comparator; the second plate of the capacitor C2 is grounded; the other end of the second switch is grounded, and the control end of the second switch is connected with the output end of the AND gate; the positive input end of the first comparator is connected with the second reference voltage, and the output end of the first comparator is connected with the trigger end of the first D trigger and the input end of the first NOT gate; the output end of the first NOT gate is connected with one input end of the AND gate; the other input end of the AND gate is connected with a grid driving signal of the power tube; the D input end of the first D trigger is connected with the high level generator, and the Q output end of the first D trigger is used for outputting a trough selection signal; the input end of the second NOT gate is connected with a grid driving signal of the power tube, and the output end of the second NOT gate is connected with the reset end of the first D trigger.
In one embodiment, the valley detecting unit includes: a second comparator and an adaptive delay circuit; the positive input end of the second comparator is connected with the switch node voltage of the power tube, the negative input end of the second comparator is connected with the threshold voltage, and the output end of the second comparator is connected with the input end of the self-adaptive delay circuit; the self-adaptive time delay circuit output is used for outputting a trough mark signal.
In one embodiment, the dynamic threshold generating unit comprises a counter, an increase/decrease judging circuit and a delay selecting circuit;
the counter is used for receiving the trough mark signal output by the trough detection unit and outputting a trough counting signal reflecting the trough number of the current period according to the trough mark signal;
the increasing and decreasing judgment circuit receives the trough counting signal, judges whether the trough number of the current period is increased or decreased according to the recorded trough number of the previous period, and outputs a judgment signal reflecting the increase or decrease of the trough number of the current period;
the time delay selection circuit is used for receiving the trough counting signal, the judging signal and the trough selection signal, and controlling the trough selection signal to delay a return difference time in the next period if the judging signal reflects that the number of the troughs of the current period is increased compared with that of the troughs of the previous period; if the judgment signal reflects that the number of the wave troughs of the current period is reduced compared with the number of the wave troughs of the previous period, the control is used for controlling the wave trough selection signal to be advanced by one return difference time in the next period.
In one embodiment, the valley selecting unit includes: a second D flip-flop and a third NOT gate; the D input end of the second D trigger is connected with the trough selection signal of the current period, the trigger end is connected with the trough mark signal, the Q output end outputs a power tube opening signal, and the reset end is connected with the output end of the third NOT gate; the input end of the third NOT gate is connected with a grid driving signal of the power tube.
The present invention also provides a valley locking method for a converter, which includes:
detecting the wave trough number of voltage resonance of a switching node of a power tube of a current period converter;
comparing the detected number of the wave troughs of the current period with the number of the wave troughs of the previous period, and if the number of the wave troughs of the current period is increased than that of the wave troughs of the previous period, controlling a wave trough selection signal for controlling the power tube to be switched on in the next period to delay a return difference time; if the number of the wave troughs of the current period is less than that of the wave troughs of the previous period, the wave trough selection signal is controlled to be advanced by one return difference time in the next period.
The invention has the beneficial effects that:
(1) The frequency modulation speed of the control loop is slowed down by the hysteresis compensation unit, so that the frequency modulation signal can be used as a time threshold value for selecting a wave trough, and the wave trough conduction switching caused by loop interference is prevented;
(2) Based on the increase and decrease conditions of the trough number of the last period and the current period, delaying or advancing a return difference time at a time threshold value so that the repeated switching of trough opening points cannot be caused by the small-range change of input voltage or load, and the return difference time dynamically changes along with the trough number;
(3) Different troughs correspond to different time thresholds and return differences, so that good locking effect can be achieved under different system parameters.
Drawings
FIG. 1 is a waveform diagram of key signals of a typical quasi-resonant control flyback converter;
FIG. 2 is a functional block diagram of a dynamic trough locking circuit of the present invention;
FIG. 3 is a circuit diagram of a hysteresis compensation unit in the valley locking circuit of the present invention;
FIG. 4 is a circuit diagram of a pulse frequency modulation unit in the valley locking circuit according to the present invention;
FIG. 5 is a circuit diagram of a trough detection unit in the trough locking circuit of the present invention;
FIG. 6 is a circuit diagram of a dynamic threshold generation unit in the valley locked circuit of the present invention;
FIG. 7 is a circuit diagram of a valley selection unit in the valley locking circuit of the present invention;
FIG. 8 is a timing diagram of the waveforms of the key signals of the valley and valley locking circuit of the present invention;
fig. 9 is a flow chart illustrating the operation of the locking method and circuit of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to fig. 2 to 9. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention.
Referring to fig. 2, a valley locking circuit 10 of the present invention includes a lag compensation unit 11, a Pulse Frequency Modulation (PFM) unit 12, a valley detection unit 13, a dynamic threshold generation unit 14, and a valley selection unit 15.
The input end of the lag compensation unit 11 is connected to the control loop and is used for inputting an error signal FB fed back by the control loop, and the lag compensation unit 11 receives the error signal FB and then provides a pair of zero-poles to compensate the error signal FB to form a compensation signal FB _ PFM with a phase lagging relative to the error signal FB; the compensation signal FB _ PFM is output to the pulse frequency modulation unit 12.
The pulse frequency modulation unit 12 modulates the charging current of the capacitor C2 disposed inside the pulse frequency modulation unit 12 according to the difference between the compensation signal FB _ PFM and the first reference voltage REF1, so that the charging period of the capacitor C2 changes, and a valley selection signal VAEN of the current period is generated. In this embodiment, the compensation signal FB _ PFM slows down the modulation speed of the pulse frequency modulation unit 12, so that the valley selection signal is unchanged as the time reference in a short time, thereby enhancing the loop stability.
The dynamic threshold generating unit 14 is connected to the pulse frequency modulating unit 12, and the dynamic threshold generating unit 14 is configured to receive the valley selection signal VAEN, determine, based on the number of valleys corresponding to the valley selection signal VAEN in the current period and the recorded number of valleys in the previous period, whether to delay a return difference time or advance a return difference time based on the valley selection signal VAEN in the NEXT period, and use the valley selection signal VAEN with the return difference time superimposed as the valley selection signal VAEN _ NEXT in the NEXT period.
The input end of the wave trough detection unit 13 is connected with a power tube M P The output end of the switch node (i.e. drain electrode) is connected with a wave trough selection unit 15, and a wave trough detection unit 13 compares the power tube M P The magnitude of the switch node voltage and the threshold voltage VTH generates a valley flag signal VA representing the valley position.
The trough selection unit 15 is used for selecting the power transistor M in the present period according to the trough selection signal VAEN generated in the previous period P And opens when the next few troughs appear.
Referring to fig. 3, fig. 3 is a circuit diagram of the lag compensation unit in the valley locking circuit of the present invention, wherein the lag compensation 11 includes: narrow pulse generator 111, first switch 112, resistor R1, capacitor C1, resistor R2, buffer 113, and resistor R3. One end of the first switch 112 is connected to the error signal FB and one end of the second resistor R2, the other end of the first switch 112 is connected to one end of the resistor R1, and the control end of the first switch 112 is connected to the output end of the narrow pulse generator 111; the other end of the resistor R1 is connected with the positive input end of the buffer 113 and the first polar plate of the capacitor C1; the second plate of the capacitor C2 is grounded; the negative input end of the buffer 113 is connected with the output end of the buffer and one end of the resistor R3; the other end of the resistor R2 is connected with the other end of the resistor R3, and the connection point of the resistor R2 and the resistor R3 is used as an output end for outputting the compensation signal FB _ PFM.
Assume that the pulse width generated by the narrow pulse generator 111 is T P With a pulse period of T C Then the transfer function of the error signal FB to the compensation signal FB _ PFM can be expressed as:
wherein s is a laplacian operator, and a required compensation effect (the phase margin is larger than 45 degrees) can be obtained by reasonably setting the resistance value of the resistor R1, the resistance value of the resistor R2, the resistance value of the resistor R3, the capacitance value of the capacitor C1 and the width and period of the narrow pulse.
Referring to fig. 4, fig. 4 is a circuit diagram of a pulse frequency modulation unit in a valley locking circuit of the present invention, the pulse frequency modulation unit 12 includes: a transconductance amplifier 121, a capacitor C2, a second switch 122, a first comparator 123, an and gate 124, a first not gate 125, a high level generator 126, a first D flip-flop 127, and a second not gate 128.
The positive input end of the first transconductance amplifier is connected with the compensation signal FB _ PFM, the negative input end is connected with the first reference voltage REF1, and the output end of the transconductance amplifier 121 is connected with the first plate of the capacitor C2, one end of the second switch 122 and the negative input end of the first comparator 123; the second plate of the capacitor C2 is grounded; the other end of the second switch 122 is grounded, and the control end of the second switch is connected with the output end of the AND gate 124; the positive input end of the first comparator 123 is connected to the second reference voltage REF2, and the output end of the first comparator 123 is connected to the trigger end of the first D flip-flop 127 and the input end of the first not gate 125; the output end of the first not gate 125 is connected with one input end of the and gate 124; the other input end of the AND gate 124 is connected with the power tube M P The gate driving signal of (1); the D input end of the first D flip-flop 127 is connected to the high level generator 126, and the Q output end of the first D flip-flop 127 outputs a current period valley selection signal; the input end of the second NOT gate 128 is connected with the power tube M P The output terminal of the gate driving signal of (1) is connected to the reset terminal of the first D flip-flop 127.
Assume that the gain of transconductance amplifier 121 is G m Then the charging current I to the capacitor C2 C Comprises the following steps:
I C ＝(FB_PFM-REF1)·G m
assuming that the capacitance value of the capacitor C2 is C2, the time for the voltage of the first plate of the capacitor C2 to charge to the second reference voltage REF2 at the positive input terminal of the first comparator 123 is:
the voltage at the negative input terminal of the first comparator 123 is greater than that at the positive input terminal, the output terminal thereof becomes low level, the first D flip-flop 127 is triggered, and the valley selection signal VAEN output from the Q output terminal of the first D flip-flop 127 becomes high level. After the valley selection signal VAEN changes to high level, the valley mark signal VA coming first is selected to give out the power tube M P Of a switching-on signal, power tube M P Gate driving signal G _ M P Change to high level, power tube M P And (4) opening.
Drive signal G _ M P The high level causes the second not gate 128 to output a low level to reset the first D flip-flop 127, and the valley selection signal VAEN becomes a low level; at the same time, both input terminals of the and gate 124 become high, so that its output terminal outputs high, closing the two switches 122. The first plate charge of the capacitor C2 is discharged to ground, the comparator 123 outputs high level, the first not gate 125 outputs low level, the and gate 124 outputs low level, the second switch 122 is turned off, the capacitor C2 is recharged, and the next stage of frequency modulation is started.
Referring to fig. 5, fig. 5 is a circuit diagram of a valley detection circuit in the valley locking circuit of the present invention, the valley detection unit 13 compares the power transistors M P The magnitude of the switch node voltage VDS (i.e., the drain voltage) and the threshold voltage VTH generate the valley flag signal VA representing the valley position.
The trough detection unit includes: a second comparator 131 and an adaptive delay circuit 132. The positive input end of the second comparator 131 is connected to the switch node voltage VDS of the power transistor, the negative input end is connected to the threshold voltage VTH, and the output end is connected to the input end of the adaptive delay circuit 132; the adaptive delay circuit 132 outputs a valley flag signal, where the threshold voltage VTH may be the input voltage of the converter or a variable threshold near the valley of the switch node voltage. In this embodiment, the threshold voltage VTH is taken as the input voltage V of the converter IN . The voltage of the switching node of the power tube of the converter working in DCM (current discontinuous mode) is atAfter the demagnetization is finished, the voltage VDS of the switch node is at the input voltage V IN Up and down, the resonance period is fixed, as shown in fig. 1. The falling edge of the low level output from the second comparator 131 corresponds to 1/4 of each resonance period. The adaptive delay circuit 132 generates different delays according to different resonant periods, so that the falling edge of the output signal VA of the adaptive delay circuit lags behind the falling edge of the output signal of the second comparator 131 by 1/4 resonant period, thereby ensuring that the falling edge of the output signal VA of the valley mark signal is at 1/2 resonant period, i.e. at the valley bottom.
Referring to fig. 6, fig. 6 is a circuit diagram of a dynamic threshold generating unit in a valley locking circuit according to the present invention, the dynamic threshold generating unit includes: a counter 141, a delay selection circuit 142, and an up/down determination circuit 143. The counter 141 receives the trough flag signal VA, outputs a trough counting signal reflecting the number of troughs in the current period according to the trough flag signal VA, and outputs the trough counting signal to the up-down judging circuit 143 and the delay selecting circuit 142; the increase/decrease judging circuit 143 may be formed by a shift register, and records the number of troughs, and outputs a delay signal to the delay selecting circuit 142 if the number of troughs in the current cycle is increased to the number of troughs in the previous cycle; if the number of troughs in the current cycle is smaller than the number of troughs in the previous cycle, an advance signal is output to the delay selection circuit 142. The delay signal and the advance signal are different levels of the same determination signal, the delay selection circuit 142 controls the valley selection signal VAEN to be delayed by one back difference time or advanced by one back difference time in the NEXT cycle according to the high and low levels of the determination signal, the delayed or advanced valley selection signal VAEN is used as the valley selection signal VAEN _ NEXT of the NEXT cycle, and the valley selection signal VAEN _ NEXT is used as the valley selection signal VAEN in the NEXT cycle.
Referring to fig. 7, fig. 7 is a circuit diagram of a valley selection unit in the valley locking circuit of the present invention, the valley selection unit 15 is used for selecting the power transistor M in the current period according to the valley selection signal VAEN generated in the previous period P Opening at the second trough.
The valley selecting unit 15 includes: a second D flip-flop 151 and a third not gate 152. Second D flip-flopA D input end of the 151 inputs a trough selection signal VAEN of the current period, a trigger end inputs a trough mark signal VA, and a Q output end outputs a power tube opening signal ON; power tube M P Gate driving signal G _ M P And is output to the reset terminal of the second D flip-flop 151 through the third not gate 152. The valley mark signal VA is firstly down after the valley selection signal VAEN is changed into high level, the power tube ON signal is changed into high level, and the power tube M is driven by the driving circuit P Gate driving signal G _ M P Goes high, and the gate driving signal G _ M P And resetting the ON signal of the power tube to low level after the high level is changed.
FIG. 8 is a timing diagram of the waveforms of the key signals of the valley locking circuit of the present invention.
Wave trough mark signal VA in power tube M P Switch node voltage V of DS A low-level narrow pulse is generated at the trough of the resonance (namely, the drain voltage); trough selection signal VAEN power tube M in each period P Driving voltage signal G _ M P The rising edge of the voltage is reset to low level, and then a pulse frequency modulation unit (PFM) controls when a valley selection signal VAEN in a single period changes to high level; the first narrow pulse of the valley flag signal VA after the valley selection signal VAEN changes to the high level causes the power tube M to P Driving voltage signal G _ M P And goes high.
In the first stage, the valley selection signal VAEN makes the power tube M P The power tube M of the next period is changed from the first wave trough opening to the second wave trough opening, the frequency is reduced P The on-time of the signal VAEN is increased to maintain energy conservation, and if the low level time of the trough selection signal VAEN is not changed, as shown by the dotted line in the figure, the first trough will be selected again in the next period to turn on the power transistor M P To avoid this, the valley selection signal VAEN of the next period is delayed by a back-off time TD 1,2 So that the second trough is still selected to turn on the power tube M P 。
In the second stage, because the input voltage of the flyback converter is increased or the load is lightened, the trough selection signal VAEN selects the second trough to turn on the power tube M P Become selectedThird wave valley open power tube M P Frequency is reduced, and likewise, power tube M of the next cycle P The on-time is prolonged, if the low level time of the trough selection signal VAEN is not changed, the second trough is reselected to switch on the power tube M in the next period P To avoid this, the valley selection signal VAEN of the next period is delayed by a back-off time TD 2,3 So that the third wave valley is still selected to turn on the power tube M P 。
In the third stage, the input voltage of the converter is reduced or the load is heavy, and the valley selection signal VAEN switches on the power tube M from the third valley P The power tube M is switched on by selecting the second trough P When the frequency is increased, the conduction time of the power tube in the next period is shortened, and if the low level time of the trough selection signal VAEN is kept unchanged, the third trough is selected again in the next period to turn on the power tube M P To avoid this, the valley selection signal VAEN at this time is advanced by a back-off time TD 3,2 So that the second wave trough is still actually selected to switch on the power tube M P . Since the frequency change from the first to the second valley on is larger than the frequency change from the second to the third valley on, the backlash time TD needs to be set 1,2 Is longer than return difference time TD 2,3 And enough return difference can be ensured to meet energy conservation when different wave troughs are switched, so that the phenomenon of repeated switching of the wave troughs is avoided.
Fig. 9 is a flowchart illustrating the valley locking method according to the present invention. Firstly, detecting the trough number of each period, and recording the trough number; secondly, comparing the trough number of the current period with the recorded trough number of the previous period, if the trough number is reduced, advancing a return difference time TD on the basis of the trough selection signal of the next period, and generating a new trough selection signal for selecting the trough of the next period; if the number of the wave troughs is increased, delaying a return difference time TD on the basis of the wave trough selection signal of the next period, and generating a new wave trough selection signal for wave trough selection of the next period. The trough selection signal is generated by an error signal through a hysteresis compensation link and a frequency modulation link.
In addition, the return difference time can be changed along with the change of different trough numbers, and is not fixed time.
It is to be understood that the embodiments of the present invention are not limited thereto, and that other embodiments of the dynamic locking method and circuit of the trough of the present invention can be made based on the above descriptions and according to the ordinary technical knowledge and conventional means in the field without departing from the basic technical idea of the present invention; therefore, the present invention can be modified, replaced or changed in other various forms without departing from the scope of the present invention.
Claims (12)
1. A method of valley locking for a converter, comprising:
detecting a resonant waveform of a switch node voltage of a power tube of the converter in a current period to obtain the number of troughs of the resonant waveform;
comparing the detected trough number of the current period with the trough number of the previous period;
if the number of the wave troughs of the current period is increased than that of the wave troughs of the previous period, delaying the time threshold value of the wave trough switching by one return difference time in the next period;
if the number of the wave troughs in the current period is less than that of the wave troughs in the previous period, the time threshold value of the wave trough switching is advanced by one return difference time in the next period.
2. A valley locking method for a converter according to claim 1, wherein the time threshold for valley switching is a time instant when a rising or falling edge of a valley selection signal for controlling the switching on of said power tube is generated.
3. A valley locking method for a converter according to claim 1, wherein in a cycle, a return difference time corresponding to a smaller number of valleys is larger than a return difference time corresponding to a larger number of valleys.
4. A method of valley locking for a converter according to claim 1 further including the step of slowing the modulation speed of the pulse frequency modulation unit by hysteresis compensating an error signal fed back by the control loop.
5. A valley-locking circuit for a converter, comprising: the device comprises a pulse frequency modulation unit, a trough detection unit, a dynamic threshold generation unit and a trough selection unit;
the pulse frequency modulation unit is used for generating a trough selection signal for controlling the power tube of the converter to be switched on and transmitting the trough selection signal to the dynamic threshold generation unit and the trough selection unit;
the wave trough detection unit is used for detecting the voltage waveform of a switching node of a power tube of the converter and generating a wave trough mark signal representing the position of a resonance wave trough;
the dynamic threshold generating unit is used for receiving the trough mark signal and the trough selection signal and counting the trough number of the current period according to the trough mark signal; if the number of the wave troughs in the current period is increased than that of the wave troughs in the previous period, controlling the wave trough selection signal to delay one return difference time in the next period; if the number of the wave troughs in the current period is less than that of the wave troughs in the previous period, controlling the wave trough selection signal to advance by one return difference time in the next period;
the wave trough selection unit is used for receiving the wave trough mark signal and the wave trough selection signal and outputting a power tube switching-on signal for switching on a power tube according to the wave trough mark signal and the wave trough selection signal.
6. A valley lock circuit for a converter according to claim 5, further comprising a lag compensation unit having an input for inputting an error signal fed back by the control loop and generating a compensation signal having a phase lagging with respect to the error signal in response to said error signal;
and the pulse frequency modulation unit receives the compensation signal and modulates the charging current of a capacitor arranged in the pulse frequency modulation unit according to the difference value of the compensation signal and the reference voltage, so that the charging period of the capacitor is changed to generate the wave trough selection signal.
7. A valley locking circuit for a converter according to claim 6, wherein said lag compensating unit comprises: the circuit comprises a narrow pulse generator, a first switch, a resistor R1, a capacitor C1, a resistor R2, a buffer and a resistor R3; one end of the first switch is connected with the error signal and one end of the second resistor R2, the other end of the first switch is connected with one end of the resistor R1, and the control end of the first switch is connected with the output end of the narrow pulse generator; the other end of the resistor R1 is connected with the positive input end of the buffer and the first polar plate of the capacitor C1; the second plate of the capacitor C2 is grounded; the negative input end of the buffer is connected with the output end of the buffer and one end of the resistor R3; the other end of the resistor R2 is connected with the other end of the resistor R3, and the connection point of the resistor R2 and the resistor R3 is used for outputting the compensation signal.
8. A valley locking circuit for a converter according to claim 7, wherein said pulse frequency modulation unit comprises: the circuit comprises a transconductance amplifier, a capacitor C2, a second switch, a first comparator, an AND gate, a first NOT gate, a high-level generator, a first D trigger and a second NOT gate;
a positive input end of the first transconductance amplifier is connected with the compensation signal, a negative input end of the first transconductance amplifier is connected with a first reference voltage, and an output end of the first transconductance amplifier is connected with a first polar plate of the capacitor C2, one end of the second switch and a negative input end of the first comparator; the second plate of the capacitor C2 is grounded; the other end of the second switch is grounded, and the control end of the second switch is connected with the output end of the AND gate; a positive input end of the first comparator is connected with a second reference voltage, and an output end of the first comparator is connected with a trigger end of the first D flip-flop and an input end of the first NOT gate; the output end of the first NOT gate is connected with one input end of the AND gate; the other input end of the AND gate is connected with a gate drive signal of the power tube; the D input end of the first D trigger is connected with the high level generator, and the Q output end of the first D trigger is used for outputting the trough selection signal; the input end of the second NOT gate is connected with the grid driving signal of the power tube, and the output end of the second NOT gate is connected with the reset end of the first D trigger.
9. A valley lock circuit for a converter according to claim 8, wherein said valley detecting unit includes: a second comparator and an adaptive delay circuit; the positive input end of the second comparator is connected with the switch node voltage of the power tube, the negative input end of the second comparator is connected with the threshold voltage, and the output end of the second comparator is connected with the input end of the self-adaptive delay circuit; and the self-adaptive time delay circuit output is used for outputting the trough mark signal.
10. A valley lock circuit for a converter according to claim 9, wherein the dynamic threshold generating unit includes a counter, an up-down judging circuit, and a delay selecting circuit;
the counter is used for receiving the trough mark signal output by the trough detection unit and outputting a trough counting signal reflecting the trough number of the current period according to the trough mark signal;
the increasing and decreasing judgment circuit receives the trough counting signal, judges whether the trough number of the current period is increased or decreased according to the recorded trough number of the previous period, and outputs a judgment signal reflecting the increase or decrease of the trough number of the current period;
the time delay selection circuit is used for receiving the trough counting signal, the judging signal and the trough selection signal, and if the judging signal reflects that the number of troughs of the current trough is increased compared with that of the trough of the previous period, the trough selection signal is controlled to delay a return difference time in the next period; and if the judgment signal reflects that the number of the wave troughs of the current period is reduced compared with the number of the wave troughs of the previous period, controlling to control the wave trough selection signal to be advanced by one return difference time in the next period.
11. A valley lock circuit for a converter according to claim 10, wherein said valley selecting unit comprises: a second D flip-flop and a third NOT gate; the D input end of the second D trigger is connected with the wave trough selection signal in the period, the trigger end of the second D trigger is connected with the wave trough mark signal, the Q output end outputs a power tube opening signal, and the reset end is connected with the output end of the third NOT gate; and the input end of the third NOT gate is connected with a grid driving signal of the power tube.
12. A method of valley locking for a converter, comprising:
detecting the wave trough number of the voltage resonance of a switching node of a power tube of the converter in the current period;
comparing the detected number of the wave troughs of the current period with the number of the wave troughs of the previous period, and if the number of the wave troughs of the current period is increased than that of the wave troughs of the previous period, controlling a wave trough selection signal for controlling the power tube to be switched on in the next period to delay a return difference time; and if the number of the wave troughs of the current period is less than that of the wave troughs of the previous period, controlling the wave trough selection signal to advance by one return difference time in the next period.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110611862.8A CN115441698A (en) | 2021-06-02 | 2021-06-02 | Wave trough locking method and circuit for converter |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110611862.8A CN115441698A (en) | 2021-06-02 | 2021-06-02 | Wave trough locking method and circuit for converter |
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| CN115441698A true CN115441698A (en) | 2022-12-06 |
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| CN202110611862.8A Pending CN115441698A (en) | 2021-06-02 | 2021-06-02 | Wave trough locking method and circuit for converter |
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| CN (1) | CN115441698A (en) |
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