CN115437453B - Bias circuit and self-biased OSC circuit - Google Patents
Bias circuit and self-biased OSC circuit Download PDFInfo
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- CN115437453B CN115437453B CN202110619514.5A CN202110619514A CN115437453B CN 115437453 B CN115437453 B CN 115437453B CN 202110619514 A CN202110619514 A CN 202110619514A CN 115437453 B CN115437453 B CN 115437453B
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Abstract
The application provides a bias circuit and a self-biased OSC circuit. The bias circuit is used for providing bias current for the OSC circuit; the impedance module and the first switch module of the bias circuit are connected in series between the power end of the OSC circuit and the bias current input end of the OSC circuit, when the OSC circuit is turned on, i.e. the first switch module is turned on, the power supply of the OSC circuit is utilized to provide bias current for the OSC circuit through the impedance module, so that the OSC circuit can realize self-bias, and therefore, the bias circuit can reduce the power consumption caused by external bias.
Description
Technical Field
The invention relates to the technical field of power electronics, in particular to a bias circuit and a self-biased OSC circuit.
Background
With the advent of the intelligent era, handheld and wearable devices are becoming more widely used, and in the present case, the design difficulty of the wearable device is to control power consumption. At present, two ideas for realizing low power consumption are available, one is to reduce the power consumption of each module in the equipment; another is to intermittently turn off or on unnecessary modules in the device, for example, by an externally biased OSC (Oscillator) circuit as shown in fig. 1, by turning off unimportant modules when intermittently turned off, only some of the critical modules are operated, thereby reducing average power consumption.
Referring to fig. 1, an external circuit provides a bias current IBIAS for the external bias OSC circuit; in the dashed box, a ring oscillator is shown which is composed of an odd number of inverters, the frequency of which is determined by the voltage at the junction B of the first switching tube and the output capacitor, which in turn is equal to the voltage at the junction a of the second switching tube and the adjusting impedance, and the voltage at the junction a is determined by the adjusting impedance Rq, so that adjusting the impedance value of the adjusting impedance Rq adjusts the output frequency of the externally biased OSC circuit, i.e. the frequency that is intermittently turned off or on.
However, the externally biased OSC circuit requires an external circuit to provide a bias current to start and operate normally, i.e. the external circuit must be kept active all the time, which generates a lot of additional power consumption.
Disclosure of Invention
In view of this, the present invention provides a bias circuit and a self-biased OSC circuit that can reduce power consumption by external bias.
In order to achieve the above object, the embodiment of the present invention provides the following technical solutions:
An aspect of the present application provides a bias circuit applied to an oscillator OSC circuit to supply a bias current, the bias circuit comprising: an impedance module and a first switch module; wherein:
The impedance module and the first switch module are connected in series between a power supply terminal of the OSC circuit and a bias current input terminal of the OSC circuit;
The control end of the first switch module receives a control signal output by the OSC circuit.
Optionally, the OSC circuit includes an enable state pin, and the control terminal of the first switch module is connected to the enable state pin of the OSC circuit.
Optionally, the first end of the impedance module is connected to the power supply end of the OSC circuit, the second end of the impedance module is connected to the input end of the first switch module, and the output end of the first switch module is connected to the bias current input end of the OSC circuit; or alternatively
The input end of the first switch module is connected with the power end of the OSC circuit, the output end of the first switch module is connected with the first end of the impedance module, and the second end of the impedance module is connected with the bias current input end of the OSC circuit.
Optionally, the method further comprises: the switching module and the current mirror module; wherein:
The current mirror module is connected with a third switch module in the switch switching module in series to form a first branch, and the impedance module is connected with a second switch module in the switch switching module in series to form a second branch; the first branch circuit is connected with the second branch circuit in parallel, and the branch circuit after parallel connection and the first switch module are connected between a power end and a bias current input end of the OSC circuit in series;
The current mirror module is used for proportionally mirroring the current value of a power supply branch of the ring oscillator in the OSC circuit;
The switch switching module is configured to switch the impedance module to provide the bias current for the OSC circuit after the impedance module provides the bias current for the OSC circuit for a preset time, to: a bias current is provided to the OSC circuit by the current mirror module.
Optionally, the input end of the current mirror module is connected with the first end of the impedance module, and the connection point is used as a connection point where the first branch and the second branch are connected in parallel; the first input end of the switch switching module is connected with the second end of the impedance module; the second input end of the switch switching module is connected with the output end of the current mirror image module; the output end of the switch switching module is used as another connecting point for connecting the first branch with the second branch in parallel; or alternatively
The input end of the switch switching module is used as a connecting point for connecting the first branch and the second branch in parallel; the first output end of the switch switching module is connected with the first end of the impedance module; the second output end of the switch switching module is connected with the input end of the current mirror image module; the second end of the impedance module is connected with the output end of the current mirror module, and the connecting point is used as another connecting point for connecting the first branch with the second branch in parallel.
Optionally, the switch switching module includes: the second switch module, the third switch module, a counter and an inverter; wherein:
The control end of the third switch module is connected with the output end of the inverter, the input end of the inverter and the control end of the second switch module are both connected with the output end of the counter, and the input end of the counter is used as the control end of the switch switching module and receives the oscillation signal of the ring oscillator in the OSC circuit;
The second switch module and the impedance module are connected in series to form the second branch; the third switch module and the current mirror module are connected in series to form the first branch.
Optionally, an enable state pin of the counter is connected to an enable state pin of the OSC circuit;
the feedback pin of the counter receives signals output by the output end of the counter;
The priority of the enabling state signal received by the enabling state pin of the counter is larger than that of the signal output by the output end of the counter.
Optionally, the preset time is a time when the counter counts the oscillation period of the oscillation signal to a preset value.
Optionally, the current mirror module includes: a switching tube; wherein:
the switching tube and an output switching tube in the power supply branch of the ring oscillator form a current mirror.
Optionally, the number ratio of the switching tube to the output switching tube is a preset multiple.
Optionally, the impedance module includes: at least one impedance; wherein:
when the number of the impedances is greater than 1, the respective impedances are connected in series and/or in parallel.
Optionally, each switch module is a reverse-conducting transistor or a mechanical switch.
Another aspect of the application provides a self-biasing OSC circuit comprising: OSC circuitry and bias circuitry as claimed in any one of the above aspects of the application.
As can be seen from the above technical solution, the present invention provides a bias circuit for providing bias current for an OSC circuit; the impedance module and the first switch module of the bias circuit are connected in series between the power end of the OSC circuit and the bias current input end of the OSC circuit, when the OSC circuit is turned on, i.e. the first switch module is turned on, the power supply of the OSC circuit is utilized to provide bias current for the OSC circuit through the impedance module, so that the OSC circuit can realize self-bias, and therefore, the bias circuit can reduce the power consumption caused by external bias.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of an external bias OSC circuit in the prior art;
Fig. 2 to 6 are schematic diagrams of five structures of the self-bias OSC circuit, respectively.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In order to reduce power consumption caused by external bias, the embodiment of the present application provides a bias circuit, which can be applied to an OSC circuit 01, and the specific structure of the bias circuit is shown in fig. 2, and includes: an impedance module 10 and a first switch module 20.
The impedance module 10 and the first switch module 20 are connected in series between the power supply terminal VCC of the OSC circuit 01 and the bias current input terminal O of the OSC circuit 01, and the control terminal of the first switch module 20 receives the control level outputted from the OSC circuit 01, for example, the control terminal of the first switch module 20 is connected to the enable state pin EN1 of the OSC circuit 01 (only EN1 represents the enable state pin EN1 of the OSC circuit 01 in the figure, but the specific structure thereof is not shown).
When the enable state pin EN1 of the OSC circuit 01 receives the first level signal, the OSC circuit 01 is turned on, and the first switch module 20 is turned on, so that a current flows through the impedance module 10 and is input to the OSC circuit 01 from the bias current input terminal O of the OSC circuit 01 as a bias current of the OSC circuit 01; when the enable state pin EN1 of the OSC circuit 01 receives the second level signal, the OSC circuit 01 is turned off, and the first switch module 20 is turned off, so that no current flows through the impedance module 10, i.e. the bias circuit is also turned off, and stops working.
When a current is inputted to the OSC circuit 01 through the bias current input terminal O of the OSC circuit 01 as the bias current of the OSC circuit 01, the potential of the bias current input terminal O of the OSC circuit 01 is approximately equal to the low level, and thus the bias current ibias= (VR-Vo)/Ro of the OSC circuit 01.
Wherein VR is the potential of the power supply terminal VCC of the OSC circuit 01; vo is the voltage value below the impedance module 10, such as the sum of the potential difference across the first switch module 20 and the potential difference across the input switch N in the OSC circuit; ro is the equivalent impedance value of the impedance module 10.
It should be noted that, the first level signal is a start signal issued by the system controller when the OSC circuit 01 is in a system start state; the second level signal is a shutdown signal issued by the system controller when the OSC circuit 01 is in a system shutdown state; in practical applications, the first level signal and the second level signal may be various level signals, such as high level or low level, but as long as the implementation manners of distinguishing the two are within the protection scope of the present application, the present application is not limited specifically, and the first level signal and the second level signal may be selected according to specific situations; preferably, the first level signal is a high level signal and the second level signal is a low level signal.
As can be seen from the above description, in the bias circuit provided by the present invention, after the OSC circuit 01 is turned on, that is, after the first switch module 20 is turned on, the power supply of the OSC circuit 01 can provide the bias current IBIAS to the OSC circuit 01 through the impedance module 10, that is, the OSC circuit 01 can realize self-bias, so that the bias circuit can reduce the power consumption caused by external bias.
In practical applications, there are different embodiments of the connection relationship between the impedance module 10 and the first switch module 20 and the connection relationship between the two and the OSC circuit 01, and one embodiment is shown in fig. 2, specifically: the first end of the impedance module 10 is connected to the power supply end VCC of the OSC circuit 01, the second end of the impedance module 10 is connected to the input end of the first switch module 20, and the output end of the first switch module 20 is connected to the bias current input end O of the OSC circuit 01; another embodiment is shown in fig. 3, specifically: the input end of the first switch module 20 is connected with the power end VCC of the OSC circuit 01, the output end of the first switch module 20 is connected with the first end of the impedance module 10, and the second end of the impedance module 10 is connected with the bias current input end O of the OSC circuit 01; the two embodiments may be selected according to circumstances, and are not particularly limited herein, and are all within the scope of the present application.
Optionally, the impedance module 10 includes at least one resistor R, where the number of resistors R is greater than 2, and each resistor R is connected in series and/or in parallel, which is not specifically limited herein, and may be optionally and specifically within the scope of the present application.
Alternatively, the first switch module 20 may be: reverse-conducting transistors, such as MOS transistors, JEET (Junction Field-Effect Transistor), IGBTs, may also be: mechanical switches, such as relays, are not specifically limited herein and may be used as appropriate within the scope of the present application.
It should be noted that, when the first switch module 20 is a MOS transistor, the potential difference between the input terminal and the output terminal of the first switch module 20 is the potential difference VTH between the drain and the source of the MOS transistor.
Although the bias circuit provided in the above embodiment can make the OSC circuit 01 realize self-bias, that is, reduce power consumption caused by external bias, since the bias circuit in the above embodiment provides the bias current IBIAS for the OSC circuit 01 with respect to the power supply of the OSC circuit 01, the bias current IBIAS for the OSC circuit 01 may change frequently, which may affect the power consumption of the OSC circuit 01.
Accordingly, another embodiment of the present application provides another implementation manner of the bias circuit, as shown in fig. 4, and further includes, based on the bias circuit in the foregoing embodiment: a switch switching module 40 and a current mirror module 30.
The current mirror module 30 is connected in series with a third switch module in the switch switching module 40 to form a first branch, the impedance module 10 is connected in series with a second switch module in the switch switching module 40 to form a second branch, the first branch is connected in parallel with the second branch, and the parallel branch is connected in series with the first switch module 20 between the power supply terminal VCC and the bias current input terminal O of the OSC circuit 01.
After the OSC circuit 01 is started, the switch switching module 40 selects the impedance module 10 to provide the bias current IBIAS for the OSC circuit 01, i.e. the second branch is turned on; after a preset time, the switch switching module 40 selects the current mirror module 30 to provide the bias current IBIAS for the OSC circuit 01; i.e. after a preset time, the first branch is conducted; that is, after a preset time, the switch switching module 40 switches the bias current IBIAS provided by the impedance module 10 to the OSC circuit 01 to: the bias current IBIAS is provided to the OSC circuit 01 by the current mirror block 30.
It should be noted that the preset time is required to be longer than the time required for the OSC circuit 01 to start up to the steady state, that is, after the preset time, the OSC circuit 01 is already in the steady state; in practical application, the specific selection of the preset time can be selected according to practical situations, so long as the requirement is met, the specific limitation is not made here, and the specific selection is within the protection scope of the application.
In addition, the control end of the current mirror module 30 is connected to the control end of the ring oscillator power supply branch 02 in the OSC circuit 01; the input end of the current mirror module 30 is directly connected with the input end of the ring oscillator power supply branch 02, or the input end of the current mirror module 30 is indirectly connected with the input end of the ring oscillator power supply branch 02 through a corresponding switch module in the switch switching module 40; the current mirror module 30 is configured to mirror the current of the ring oscillator supply branch 02 in the OSC circuit 01 by a preset ratio.
It should be noted that, the ring oscillator power supply branch 02 in the OSC circuit 01 includes the first output switch tube MX, the second output switch tube MY, the output capacitor C and the output resistor Rc in fig. 4, when the first output switch tube MX and the second output switch tube MY are PMOS transistors, as shown in fig. 4, the first output switch tube MX and the second output switch tube MY form a current mirror, that is, the gates of the first output switch tube MX and the second output switch tube MY are connected, and the sources of the first output switch tube MX and the second output switch tube MY are connected to the power supply terminal VCC of the OSC circuit 01; the drain electrode of the first output switching tube MX is grounded through an output resistor Rc, and the drain electrode of the second output switching tube MY is grounded through an output capacitor C; it can be seen that the current of the ring oscillator supply branch 02 in the OSC circuit 01 may be the current flowing through the first output switch tube MX or the current flowing through the second output switch tube MY, which is not limited herein, and the current is within the protection scope of the present application as the case may be.
After the preset time, the OSC circuit 01 is in a stable state, the output of the operational amplifier in the OSC circuit 01 is a stable voltage, and the current of the ring oscillator power supply branch 02 in the OSC circuit 01 is directly related to the frequency, so that the current of the ring oscillator power supply branch 02 in the OSC current is relatively stable at this time, and the currents in the current mirror module 30 are relatively stable at this time, and then the bias current IBIAS is provided for the OSC current by the current mirror module 30 is selected at this time, so that the OSC circuit 01 can obtain the relatively stable bias current IBIAS, that is, frequent conversion of the bias current IBIAS can be reduced, and therefore, the influence on the power consumption of the OSC circuit 01 can be reduced.
Specifically, in this embodiment, there are two embodiments of the connection relationship among the current mirror module 30, the impedance module 10, and the switch switching module 40, and one embodiment is shown in fig. 4, specifically:
The input end of the current mirror module 30 is connected to the first end of the impedance module 10, and the connection point is used as a connection point where the first branch and the second branch are connected in parallel; a first input terminal of the switching module 40 is connected to a second terminal of the impedance module 10, and a second input terminal of the switching module 40 is connected to an output terminal of the current mirror module 30; the output of the switching module 40 serves as a further connection point for the parallel connection of the first branch with the second branch.
Another embodiment is shown in fig. 5, specifically:
The input end of the switch switching module 40 is used as a connection point for connecting the first branch and the second branch in parallel; a first output end of the switch switching module 40 is connected with a first end of the impedance module 10, and a second output end of the switch switching module 40 is connected with an input end of the current mirror module 30; a second end of the impedance module 10 is connected to the output of the circuit mirror module, and the connection point is another connection point where the first branch is connected in parallel with the second branch.
The two embodiments of the connection relationship among the current mirror module 30, the impedance module 10, and the switch switching module 40 can be selected according to the circumstances, and are not specifically limited herein, and are all within the scope of the present application.
It should be noted that, in the present embodiment, the connection relationship between the branch formed by connecting the first branch and the second branch in parallel and the first switch module 20 is the same as that between the impedance module 10 and the first switch module 20 in the above embodiment, and may be derived by referring to the description of the connection relationship between the impedance module 10 and the first switch module 20 in the above embodiment, which is not described in detail herein.
In the above embodiment, the switch switching module 40 may switch to a power supply module that provides the bias current IBIAS to the OSC circuit 01 after a preset time, such as the current mirror module 30 in the above embodiment, to reduce the influence on the power consumption of the OSC circuit 01. To achieve the above object, another embodiment of the present application provides an implementation of the internal structure of the switch-switching module 40, whose specific structure is shown in fig. 6 (shown on the basis of fig. 4 as an example), including: the second switching module 41, the third switching module 42, the counter 43, and the inverter INV.
The second switch module 41 is connected in series with the impedance module 10 as a second branch; the third switching module 42 is connected in series with the current mirror module 30 as a first branch.
The control end of the third switch module 42 is connected to the control end of the second switch module 41 through the inverter INV, and the connection point is connected to the output end of the counter 43, specifically, the control end of the third switch module 42 is connected to the input end of the inverter INV, then the output end of the inverter INV is connected to the control end of the second switch module 41, and the connection point is connected to the output end of the counter 43.
The input terminal of the counter 43 is used as the control terminal of the switch switching module 40, and is connected to the output terminal of the OSC circuit 01, and receives the oscillating signal of the ring oscillator 02 in the OSC circuit 01, and uses the oscillating signal to time, i.e. count the oscillating period of the oscillating signal, so that the preset time is the time for counting the oscillating period of the oscillating signal to a preset value, i.e. the preset time is equal to the product of the oscillating period of the oscillating signal and the preset value.
Optionally, the preset value may be 4, or other values, which are not specifically limited herein, and are all within the protection scope of the present application.
For example, the oscillation period is 0.5s, the preset value is 4, and the preset time is 2s, that is, after the OSC circuit 01 is started for 5s, the switch switching module 40 will switch the bias current IBIAS provided by the impedance module 10 to the OSC circuit 01 to: the bias current IBIAS is provided to the OSC circuit 01 by the current mirror block 30.
Before the preset time, the counter 43 outputs a third level signal, after the preset time, the signal output by the counter 43 is turned from the third level signal to a fourth level signal, the control end of the second switch module 41 receives the fourth level signal, and the inverter INV turns the fourth level signal to the third level signal and inputs the third level signal to the third switch module 42, so that the second switch module 41 is turned off, the third switch module 42 is turned on, i.e. the first branch is turned on, and the current mirror module 30 provides the bias current IBIAS for the OSC circuit 01.
It should be noted that, in practical applications, the third level signal and the fourth level signal may be various level signals, such as high level or low level, but as long as the implementation manners of the two signals that can be distinguished are within the scope of the present application, the specific limitation is not made here, and the type conditions of the second switch module 41 and the third switch module 42 may be selected according to the type conditions; preferably, the third level signal is a low level signal, and the fourth level signal is a high level signal.
The above-mentioned preferred embodiment is only a preferred internal structure of the switch switching module 40, and in practical applications, including but not limited to the above-mentioned embodiment, it is possible to apply the present application as the case may be, and the present application is not limited thereto.
It should be noted that, in the present embodiment, the connection between the control terminal of the switch switching module 40 and the output terminal of the OSC circuit 01 is merely a preferred connection manner of the control terminal of the switch switching module 40, and in practical applications, including but not limited to the foregoing embodiments, it is possible to determine that the connection is not specifically limited herein, and the connection is within the scope of the present application.
In practical applications, as shown in fig. 6, a feedback pin F is further provided on the counter 43, where the feedback pin F of the counter 43 receives a signal output from its own output terminal, for example, a fourth level signal; before the preset time, the feedback pin F of the counter 43 receives the third level signal and still maintains itself in the working state, after the preset time, the feedback pin F of the counter 43 receives the fourth level signal, and then closes itself, stops working, so as to maintain the output end of itself to output the fourth level signal.
In practical applications, as shown in fig. 6, the counter 43 is further provided with an enable state pin EN2, and the feedback pin EN2 of the counter 43 is connected to the enable state pin EN1 of the OSC circuit 01, and receives an enable state signal; when the enable state signal is the second level signal, that is, the OSC circuit 01 is turned off, the counter 43 is reset.
It should be noted that, the priority of the enable state signal received by the feedback pin EN2 of the counter 43 is greater than the signal output by the output terminal of the counter 43, for example, when the feedback pin F of the counter 43 receives the fourth level signal, the counter is turned off, and if the enable state signal received by the feedback pin EN2 of the counter 43 at this time becomes the second level signal, the counter 43 is immediately reset, and the signal output by the output terminal thereof is also switched to the third level signal.
Alternatively, as with the first switch module 20, the second switch module 41 or the third switch module 42 may be: reverse-conducting transistors, such as MOS transistors, JEET (Junction Field-Effect Transistor), IGBTs, may also be: mechanical switches, such as relays, are not specifically limited herein and may be used as appropriate within the scope of the present application.
The present embodiment also provides a specific implementation of the current mirror module 30, whose specific structure is shown in fig. 6, and includes: and a switching tube M.
The source electrode and the drain electrode of the switching tube M are respectively used as an input end and an output end of the current mirror image module; the grid electrode of the switching tube M is connected with the grid electrodes of the output switching tubes MX and MY in the ring oscillator power supply branch 02 in the OSC circuit 01 to form a current mirror, and mirror image output of the preset proportion is carried out on the current of the ring oscillator power supply branch 02 in the OSC circuit 01.
Optionally, the switching tube M may be an NMOS transistor or a PMOS transistor, which is not specifically limited herein, and may be optionally within the scope of the present application, and it is not necessary to note that the switching tube M needs to be ensured to be the same as the types of the output switching tubes MX and MY in the ring oscillator power supply branch 02 of the OSC circuit 01.
It should be noted that, when the current of the ring oscillator supply branch 02 in the OSC circuit 01 is the current flowing through the first output switching tube MX, the preset ratio is a first preset ratio, and the first preset ratio is equal to the number ratio of the switching tube M to the first output switching tube MX in the ring oscillator supply branch 02 in the OSC circuit 01; when the current of the ring oscillator power supply branch 02 in the OSC circuit 01 is the current flowing through the second output switching tube MY, the preset proportion is a second preset proportion, and the second preset proportion is equal to the number ratio of the switching tube M to the second output switching tube MY in the ring oscillator power supply branch 02 in the OSC circuit 01; the first preset proportion and the second preset proportion can be set according to actual conditions, and are not particularly limited herein, and are all within the protection scope of the application.
Another embodiment of the present application provides a self-biased OSC circuit, the specific structure of which can be seen in fig. 2-6, which includes an OSC circuit 01 and the bias circuit in the above embodiments.
The specific structure of the bias circuit is described in detail in the above embodiments, which can be seen in the above embodiments, and will not be described in detail here,
In the present application, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The features described in the various embodiments of the present disclosure may be interchanged or combined with one another in the description of the disclosed embodiments to enable those skilled in the art to make or use the application. The above description is only of the preferred embodiment of the present application, and is not intended to limit the present application in any way. While the application has been described with reference to preferred embodiments, it is not intended to be limiting. Any person skilled in the art can make many possible variations and modifications to the technical solution of the present application or modifications to equivalent embodiments using the methods and technical contents disclosed above, without departing from the scope of the technical solution of the present application. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present application still fall within the scope of the technical solution of the present application.
Claims (11)
1. A bias circuit for application to an oscillator OSC circuit to provide a bias current, the bias circuit comprising: an impedance module and a first switch module; wherein:
The impedance module and the first switch module are connected in series between a power supply terminal of the OSC circuit and a bias current input terminal of the OSC circuit;
the control end of the first switch module receives a control signal output by the OSC circuit;
the OSC circuit comprises an enable state pin, and a control end of the first switch module is connected to the enable state pin of the OSC circuit;
Further comprises: the switching module and the current mirror module; wherein:
The current mirror module is connected with a third switch module in the switch switching module in series to form a first branch, and the impedance module is connected with a second switch module in the switch switching module in series to form a second branch; the first branch circuit is connected in parallel with the second branch circuit, and the parallel branch circuit and the first switch module are connected in series between a power supply end and a bias current input end of the OSC circuit.
2. The bias circuit of claim 1, wherein a first terminal of the impedance block is connected to a power supply terminal of the OSC circuit, a second terminal of the impedance block is connected to an input terminal of the first switch block, and an output terminal of the first switch block is connected to a bias current input terminal of the OSC circuit; or alternatively
The input end of the first switch module is connected with the power end of the OSC circuit, the output end of the first switch module is connected with the first end of the impedance module, and the second end of the impedance module is connected with the bias current input end of the OSC circuit.
3. The biasing circuit of claim 1, wherein the bias voltage is,
The current mirror module is used for proportionally mirroring the current value of a power supply branch of the ring oscillator in the OSC circuit;
The switch switching module is configured to switch the impedance module to provide the bias current for the OSC circuit after the impedance module provides the bias current for the OSC circuit for a preset time, to: a bias current is provided to the OSC circuit by the current mirror module.
4. The biasing circuit of claim 1, wherein an input of said current mirror module is connected to a first end of said impedance module at a junction point that is a junction point of said first branch and said second branch connected in parallel; the first input end of the switch switching module is connected with the second end of the impedance module; the second input end of the switch switching module is connected with the output end of the current mirror image module; the output end of the switch switching module is used as another connecting point for connecting the first branch with the second branch in parallel; or alternatively
The input end of the switch switching module is used as a connecting point for connecting the first branch and the second branch in parallel; the first output end of the switch switching module is connected with the first end of the impedance module; the second output end of the switch switching module is connected with the input end of the current mirror image module; the second end of the impedance module is connected with the output end of the current mirror module, and the connecting point is used as another connecting point for connecting the first branch with the second branch in parallel.
5. A biasing circuit according to claim 3, wherein said switch-switching module comprises: the second switch module, the third switch module, a counter and an inverter; wherein:
The control end of the third switch module is connected with the output end of the inverter, the input end of the inverter and the control end of the second switch module are both connected with the output end of the counter, and the input end of the counter is used as the control end of the switch switching module and receives the oscillation signal of the ring oscillator in the OSC circuit;
The second switch module and the impedance module are connected in series to form the second branch; the third switch module and the current mirror module are connected in series to form the first branch.
6. The biasing circuit of claim 5, wherein an enable state pin of the counter is connected to an enable state pin of the OSC circuit;
the feedback pin of the counter receives signals output by the output end of the counter;
The priority of the enabling state signal received by the enabling state pin of the counter is larger than that of the signal output by the output end of the counter.
7. The bias circuit of claim 6 wherein said preset time is a time for said counter to count an oscillation period of said oscillation signal to a preset value.
8. The bias circuit of claim 3 wherein said current mirror module comprises: a switching tube; wherein:
and the switching tube and an output switching tube in the power supply branch of the ring oscillator form the current mirror module.
9. The bias circuit of claim 8 wherein the ratio of the number of said switching tubes to said output switching tubes is a predetermined multiple.
10. The bias circuit of any one of claims 1-9, wherein the impedance module comprises: at least one impedance; wherein:
when the number of the impedances is greater than 1, the respective impedances are connected in series and/or in parallel.
11. A self-biasing OSC circuit, comprising: OSC circuitry and a biasing circuit as claimed in any one of claims 1 to 10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110619514.5A CN115437453B (en) | 2021-06-03 | Bias circuit and self-biased OSC circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110619514.5A CN115437453B (en) | 2021-06-03 | Bias circuit and self-biased OSC circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115437453A CN115437453A (en) | 2022-12-06 |
| CN115437453B true CN115437453B (en) | 2024-06-28 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101127506A (en) * | 2007-09-29 | 2008-02-20 | 北京时代民芯科技有限公司 | A novel CMOS oscillator circuit |
| CN206698185U (en) * | 2016-02-25 | 2017-12-01 | 宗仁科技(平潭)有限公司 | A kind of oscillating circuit and oscillator |
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101127506A (en) * | 2007-09-29 | 2008-02-20 | 北京时代民芯科技有限公司 | A novel CMOS oscillator circuit |
| CN206698185U (en) * | 2016-02-25 | 2017-12-01 | 宗仁科技(平潭)有限公司 | A kind of oscillating circuit and oscillator |
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