CN115426438B - DP video signal time sequence recovery device and working method thereof - Google Patents
DP video signal time sequence recovery device and working method thereof Download PDFInfo
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- H04N19/44—Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
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Abstract
The invention discloses a DP video signal time sequence recovery device and a working method thereof. The device comprises a DP receiving and decoding module, a video data caching module, a double-port first-in first-out module, a storage control module, a clock recovery control module, a phase-locked loop module and a video time sequence generating module. The DP video signal processing method has the advantages that the control information of the DP video signal is analyzed through the DP receiving and decoding module, the DP video signal in the FreeSeync mode can be converted into complete Timing information to be output according to the configuration of VSW and VSS parameters, and the DP video signal can be converted into other video signals conveniently; the method realizes that the numerical values of VSync _ Width and VSync _ Start are consistent under the condition of variable frame frequency in a FreeSesync mode; the circuit cost is reduced, and the video time sequence conversion delay is reduced; the integrity and real-time performance of Timing information of the output video signal can be ensured.
Description
Technical Field
The invention relates to the technical field of DP video signal timing sequence recovery, in particular to a DP video signal timing sequence recovery device and a working method thereof.
Background
DP (Display Port) is a high definition digital Display protocol interface, and is commonly used to connect a computer and a Display device, and the DP interface supports the communication problem between a computing processor and the Display device through the FreeSync technology, and can dynamically adjust the frame refresh frequency of a video signal, thereby solving the tearing phenomenon of a Display frame. Because the DP interface is a display communication port that relies on packetized data transmission, in order to implement complete restoration of Timing in the conventional video interface conversion, a Frame Buffer-based mode is required for supporting FreeSeync, which is costly to implement, and the processing delay for video signals is greater than one Frame, so that the purpose of low-delay display cannot be achieved.
Disclosure of Invention
The invention aims to provide a DP video signal time sequence recovery device and a working method thereof aiming at the defects in the prior art.
In order to achieve the above object, in a first aspect, the present invention provides a DP video signal timing recovery apparatus, including a DP receiving and decoding module, a video data caching module, a dual-port first-in first-out module, a storage control module, a clock recovery control module, a phase-locked loop module, and a video timing generation module;
the DP receiving and decoding module is used for receiving a DP video signal and a DP auxiliary signal sent by a DP signal source and analyzing the DP video signal and the DP auxiliary signal to obtain and output a video pixel, a video pixel effective signal, video data information, control information and a DP link clock;
the video data caching module is respectively connected with the DP receiving and decoding module, the storage control module and the double-port first-in first-out module and is used for caching video pixels output by the DP receiving and decoding module under the control of the storage control module and sending the video pixels to the double-port first-in first-out module;
the double-port first-in first-out module is respectively connected with the storage control module and the video time sequence generation module and is used for receiving the video pixels sent by the video data caching module under the write control of the storage control module and outputting video pixel signals to the post-stage circuit under the read control of the video time sequence generation module;
the storage control module is respectively connected with the DP receiving and decoding module and the video time sequence generating module and is used for receiving a video pixel effective signal output by the DP receiving and decoding module and an effective gating signal DE output by the video time sequence generating module, generating a control signal for controlling the video data caching module according to the video pixel effective signal and generating a writing control signal for controlling the double-port first-in first-out module according to the effective gating signal DE;
the clock recovery control module is respectively connected with the DP receiving and decoding module, the video data caching module, the double-port first-in first-out module and the phase-locked loop module, and is used for receiving video data information output by the DP receiving and decoding module, state information output by the double-port first-in first-out module and state information output by the video data caching module, and generating a control signal for controlling the phase-locked loop module according to the video data information, the state information of the double-port first-in first-out module and the state information of the video data caching module;
the phase-locked loop module is respectively connected with the DP receiving and decoding module, the video time sequence generating module and the double-port first-in first-out module, and is used for receiving a DP link clock output by the DP receiving and decoding module, taking the DP link clock as a reference, generating a recovered video clock under the control of the clock recovery control module, and outputting the recovered video clock to the double-port first-in first-out module, the video time sequence generating module and the post-stage circuit by the phase-locked loop module;
the video time sequence generating module is connected with the DP receiving and decoding module and used for receiving the control information output by the DP receiving and decoding module, generating an effective gating signal DE, a field synchronizing signal VSYNC and a line synchronizing signal HSYNC to a rear-stage circuit according to the control information and a video clock output by the phase-locked loop module, and outputting a reading control signal to the double-port first-in first-out module.
In a second aspect, the present invention provides a method for operating a DP video signal timing recovery apparatus, comprising the steps of:
the method comprises the following steps that 1, a DP receiving and decoding module analyzes received DP video signals and DP auxiliary signals to obtain video pixels, video pixel effective signals, video data information, control information and a DP link clock;
step 3, the video Timing generation module detects whether a FreeSeync signal is output by the DP signal source according to the control information, if the FreeSeync signal is output by the DP signal source, the Timing information is generated by referring to the control information, and the Timing information comprises a line synchronization signal Width HSync _ Width, a distance HSync _ Start from a line synchronization to a line effective pixel, a field synchronization signal Width VSync _ Width, a distance VSync _ Start from a field synchronization signal to a field effective line, an effective pixel Width H _ Active of a line video signal and an effective line number V _ Active of a field video signal;
step 4, after the storage control module detects a first video pixel effective signal of a frame of video data, the storage control module triggers the video time sequence generating module to generate an effective gating signal DE, a field synchronizing signal VSYNC and a line synchronizing signal HSYNC according to the Timing information, and controls the video data caching module to cache a parameter value of the field synchronizing signal Width VSync _ Width + a parameter value of the field synchronizing signal distance VSync _ Start to the field effective line-1 line of video pixels according to the field synchronizing signal Width VSync _ Width and the parameter value of the field effective line distance VSync _ Start;
step 5, writing the cached video pixels into a double-port first-in first-out module under the control of a storage control module;
step 6, after the video time sequence generation module outputs a field synchronizing signal VSYNC, the effective gating signal DE controls the double-port first-in first-out module to output a video pixel signal;
and 8, after the video time sequence generation module outputs the V _ Active time of one frame of picture, the clock recovery control module stops tracking the generation of the video clock and waits for the DP receiving and decoding module to output the next frame of video data.
Further, in step 4, after the clock recovery control module has tracked and stabilized, if the start of the first video pixel signal or the first line of video signal of each frame of video signal is detected, the start edge of the VSync generated by resynchronization of the start edge of the next HSync is waited, and the length of the video pixel data buffered by the video data buffer module is adjusted accordingly.
Further, the mode that the clock recovery control module controls the phase-locked loop module to generate the recovered video clock based on the initial video clock in step 7 according to the comparison result is specifically as follows:
if the double-port first-in first-out module is deflected to be empty, the clock recovery control module controls the phase-locked loop module to increase on the basis of the initial video clock and outputs the increased phase-locked loop module as a recovered video clock;
if the double-port first-in first-out module is biased to be full, the clock recovery control module controls the phase-locked loop module to be lowered on the basis of the initial video clock and outputs the lowered phase-locked loop module as a recovered video clock.
Further, the manner of generating the Timing information with reference to the control information in step 3 is specifically as follows:
the Width HSync _ Width of the line synchronization signal uses an HSyncWidth field in the control information, and the unit is a pixel point;
the distance HSync _ Start from the line synchronization to the line effective pixel uses an HStart field in the control information, and the unit is a pixel point;
the effective pixel width H _ Active of a line of video signals uses the HWidth field in the control information, and the unit is a pixel point;
the effective line number V _ Active of a field of video signal uses a VWidth field in the control information, and the unit is a line;
the field synchronizing signal Width VSync _ Width uses a configurable parameter VSW, and the unit is a line;
the distance VSync _ Start of the field sync signal to the field active lines is in lines using the configurable parameter VSS.
Further, the phase-locked loop module in step 2 generates the initial video clock in the following manner:
counting the time of each line of DP video signals as T1 according to the DP link clock;
calculating the frequency Hfreq = 1/T1 of the line synchronization signal;
acquiring each line of pixel point Htotal from the control information;
the initial video clock = Hfreq Htotal is calculated.
Has the advantages that: 1. the DP video signal processing method has the advantages that the control information of the DP video signal is analyzed through the DP receiving and decoding module, the DP video signal in the FreeSync mode can be converted into complete Timing information to be output according to the configuration of VSW and VSS parameters, and the DP video signal can be converted into other video signals conveniently;
2. when the Start of each frame of video data is detected, the video time sequence generation module prepares to output a field synchronizing signal VSYNC, only when the Start of the first line of effective data of each frame is detected, the field synchronizing signal VSYNC is output, and therefore the purpose that the numerical values of VSync _ Width and VSync _ Start are consistent under the condition of variable frame frequency in a FreeSesync mode can be achieved;
3. the video data caching module caches the video pixels in the VSW + VSS-1 line, starts to output the video pixel data when the video time sequence generating module generates an effective gating signal DE, and reduces the circuit cost and the video time sequence conversion delay by using the video data caching module and the double-port first-in first-out module in a matching way;
4. the invention utilizes the double-port first-in first-out module, the clock recovery control module and the phase-locked loop module to finely adjust the video clock in the effective V _ Active period of the Timing information output, thereby ensuring the integrity and the real-time property of the Timing information of the output video signal.
Drawings
FIG. 1 is a schematic diagram of a DP video timing recovery apparatus according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a video Timing generation module generating Timing information.
Detailed Description
The present invention will be further illustrated with reference to the accompanying drawings and specific examples, which are carried out on the premise of the technical solution of the present invention, and it should be understood that these examples are only for illustrating the present invention and are not intended to limit the scope of the present invention.
As shown in fig. 1, an embodiment of the present invention provides a DP video signal timing recovery apparatus, which includes a DP receiving and decoding module 1, a video data buffering module 2, a dual-port first-in first-out module 3, a storage control module 4, a clock recovery control module 5, a phase-locked loop module 6, and a video timing generation module 7.
The DP receiving and decoding module 1 is configured to receive a DP video signal and a DP auxiliary signal from a DP signal source, and parse the DP video signal and the DP auxiliary signal to obtain and output a video pixel, a video pixel valid signal, video data information, control information (MSA-Main Stream Attribute, etc.), and a DP link clock.
The video data caching module 2 is connected with the DP receiving decoding module 1, the storage control module 4 and the dual-port fifo module 3 respectively, and is configured to cache video pixels output by the DP receiving decoding module 1 under the control of the storage control module 4, and send the video pixels to the dual-port fifo module 3.
The dual-port first-in first-out module 3 is connected with the storage control module 4 and the video timing sequence generation module 7 respectively, and is used for receiving the video pixels sent by the video data caching module 2 under the write control of the storage control module 4 and outputting video pixel signals to the subsequent circuit under the read control of the video timing sequence generation module 7.
The storage control module 4 is connected to the DP receiving and decoding module 1 and the video timing sequence generating module 7, respectively, and is configured to receive the video pixel valid signal output by the DP receiving and decoding module 1 and the valid strobe signal DE output by the video timing sequence generating module 7, generate a control signal for controlling the video data buffer module 2 according to the video pixel valid signal, and generate a write control signal for controlling the dual-port fifo module 3 according to the valid strobe signal DE.
The clock recovery control module 5 is connected to the DP receiving and decoding module 1, the video data buffer module 2, the dual port fifo module 3, and the pll module 6, respectively, and is configured to receive video data information output by the DP receiving and decoding module 1, state information output by the dual port fifo module 2, and state information output by the video data buffer module 2, and generate a control signal for controlling the pll module 6 according to the video data information, the state information of the dual port fifo module 3, and the state information of the video data buffer module 2.
The phase-locked loop module 6 is connected to the DP receiving and decoding module 1, the video timing generation module 7, and the dual-port fifo module 3, respectively, and is configured to receive a DP link clock output by the DP receiving and decoding module 1, use the DP link clock as a reference, and generate a recovered video clock under the control of the clock recovery control module 5, and the phase-locked loop module 6 outputs the generated recovered video clock to the dual-port fifo module 3, the video timing generation module 7, and the subsequent stage circuit.
The video timing generation module 7 is connected to the DP receiving and decoding module 1, and is configured to receive the control information output by the DP receiving and decoding module 1, generate an effective strobe signal DE, a field synchronization signal VSYNC, and a line synchronization signal HSYNC according to the control information and the video clock output by the phase-locked loop module 6, and output a read control signal to the dual-port fifo module 3.
Based on the above embodiments, as can be easily understood by those skilled in the art with reference to fig. 1 and fig. 2, the present invention further provides an operating method of a DP video signal timing recovery apparatus, including the following steps:
step 1, the DP receiving and decoding module 1 parses the received DP video signal and DP auxiliary signal to obtain video pixels, video pixel valid signals, video data information, control information, and DP link clock.
And 2, the phase-locked loop module 6 generates an initial video clock according to the DP link clock and the control information analyzed by the DP receiving and decoding module 1.
Specifically, the phase-locked loop module 6 generates the initial video clock in the following manner:
counting the time of each line of the DP video signal as T1 according to the DP link clock;
calculating the frequency Hfreq = 1/T1 of the line synchronization signal;
acquiring Htotal of each row of pixel points from the control information;
the initial video clock = Hfreq Htotal is calculated.
Step 3, the video Timing generation module 7 detects whether a signal output by the DP signal source is a FreeSync (AMD FreeSync, which supports variable refresh rate technology provided by AMD) signal according to the control information, and if the signal is a FreeSync signal, generates Timing information with reference to the control information, as shown in fig. 2, where the Timing information includes a line synchronization signal Width HSync _ Width, a distance from a line synchronization to a line Active pixel HSync _ Start, a field synchronization signal Width VSync _ Width, a distance from a field synchronization signal to a field Active line VSync _ Start, an Active pixel Width H _ Active of a line video signal, and an Active line number V _ Active of a field video signal.
Specifically, the manner of generating Timing information by referring to the control information in step 3 is as follows:
the Width HSync _ Width of the line synchronization signal uses an HSyncWidth field in the control information, and the unit is a pixel point;
the distance HSync _ Start from the line synchronization to the line effective pixel uses an HStart field in the control information, and the unit is a pixel point;
the effective pixel width H _ Active of a line of video signals uses HWidth fields in control information, and the unit is a pixel point;
the effective line number V _ Active of a field of video signal uses a VWidth field in the control information, and the unit is a line;
the field synchronizing signal Width VSync _ Width uses a configurable parameter VSW, and the unit is a line;
the distance VSync _ Start of the field sync signal to the field active lines is in lines using a configurable parameter VSS.
Step 4, after the storage control module 4 detects the first video pixel effective signal of one frame of video data, the video Timing generation module 7 is triggered to generate an effective gating signal DE, a field synchronizing signal VSYNC and a line synchronizing signal HSYNC according to Timing information, and the video data caching module 2 is controlled to cache the parameter Value (VSW) of the field synchronizing signal Width VSYNC _ Width and the parameter Value (VSS) -1 line video pixel of the distance VSYNC _ Start from the field synchronizing signal to the field effective line according to the field synchronizing signal Width VSYNC _ Width and the parameter value of the distance VSYNC _ Start from the field effective line VSYNC _ Width. For example, if VSW is 1 and VSS is 2, then 2 lines of video pixels need to be buffered. After the clock recovery control module 5 has tracked and stabilized, if the start of the first video pixel signal or the first line of video signal of each frame of video signal is detected, the start edge of the VSync generated by resynchronization of the start edge of the next HSync is waited, and the length of the buffered video pixel data of the video data buffer module 2 is adjusted accordingly. The above-mentioned tracking stability means that the clock recovery control module 5 adjusts the output recovered video clock in real time to keep the read-write balance of the fifo module state 3.
And 5, controlling the cached video pixels to be written into the double-port first-in first-out module 3 by the storage control module 4.
And 6, after the video timing generation module 7 outputs the field synchronizing signal VSYNC, controlling the double-port first-in first-out module 3 to output the video pixel signal through an effective gating signal DE.
And 7, continuously detecting the state of the double-port first-in first-out module 3 by the clock recovery control module 5 in the V _ Active period, comparing the speed of writing the video pixel data into the clock recovery control module with the speed of reading the video pixel data, controlling the phase-locked loop module 6 by the clock recovery control module 5 according to the comparison result to adjust and output the recovered video clock on the basis of the initial video clock, and keeping the read-write balance of the video pixel data of the double-port first-in first-out module 3.
Specifically, the mode of the clock recovery control module 5 controlling the phase-locked loop module 6 to generate the recovered video clock based on the initial video clock according to the comparison result is as follows:
if the dual-port fifo 3 is biased to be empty, it indicates that the clock for reading the video pixels is too fast at this time, and the clock recovery control module 5 controls the pll module 6 to increase based on the initial video clock and output as the recovered video clock after increasing; if the dual-port fifo 3 is biased to be full, it means that the clock for reading the video pixels is too slow, and the clock recovery control module 5 controls the pll module 6 to decrease based on the initial video clock and output as the recovered video clock after decreasing.
And 8, after the video time sequence generation module 7 outputs the V _ Active time of one frame of picture, the clock recovery control module 5 stops tracking the generation of the video clock and waits for the DP receiving and decoding module 1 to output the next frame of video data.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that other parts not specifically described are within the skill or common general knowledge of one of ordinary skill in the art. Numerous modifications and adaptations may be made without departing from the principles of the present invention and such modifications and adaptations are intended to be within the scope of the present invention.
Claims (6)
1. A DP video signal time sequence recovery device is characterized by comprising a DP receiving and decoding module, a video data caching module, a double-port first-in first-out module, a storage control module, a clock recovery control module, a phase-locked loop module and a video time sequence generation module;
the DP receiving and decoding module is used for receiving a DP video signal and a DP auxiliary signal sent by a DP signal source and analyzing the DP video signal and the DP auxiliary signal to obtain and output a video pixel, a video pixel effective signal, video data information, control information and a DP link clock;
the video data caching module is respectively connected with the DP receiving and decoding module, the storage control module and the double-port first-in first-out module and is used for caching video pixels output by the DP receiving and decoding module under the control of the storage control module and sending the video pixels to the double-port first-in first-out module;
the double-port first-in first-out module is respectively connected with the storage control module and the video time sequence generation module and is used for receiving the video pixels sent by the video data caching module under the write control of the storage control module and outputting video pixel signals to the rear-stage circuit under the read control of the video time sequence generation module;
the storage control module is respectively connected with the DP receiving and decoding module and the video time sequence generating module and is used for receiving a video pixel effective signal output by the DP receiving and decoding module and an effective gating signal DE output by the video time sequence generating module, generating a control signal for controlling the video data caching module according to the video pixel effective signal and generating a writing control signal for controlling the double-port first-in first-out module according to the effective gating signal DE;
the clock recovery control module is respectively connected with the DP receiving and decoding module, the video data caching module, the double-port first-in first-out module and the phase-locked loop module, and is used for receiving video data information output by the DP receiving and decoding module, state information output by the double-port first-in first-out module and state information output by the video data caching module, and generating a control signal for controlling the phase-locked loop module according to the video data information, the state information of the double-port first-in first-out module and the state information of the video data caching module;
the phase-locked loop module is respectively connected with the DP receiving and decoding module, the video time sequence generating module and the double-port first-in first-out module, and is used for receiving a DP link clock output by the DP receiving and decoding module, taking the DP link clock as a reference, generating a recovered video clock under the control of the clock recovery control module, and outputting the recovered video clock to the double-port first-in first-out module, the video time sequence generating module and the post-stage circuit by the phase-locked loop module;
the video time sequence generating module is connected with the DP receiving and decoding module and used for receiving the control information output by the DP receiving and decoding module, generating an effective gating signal DE, a field synchronizing signal VSYNC and a line synchronizing signal HSYNC to a rear-stage circuit according to the control information and a video clock output by the phase-locked loop module, and outputting a reading control signal to the double-port first-in first-out module.
2. The method of claim 1, comprising the steps of:
the method comprises the following steps that 1, a DP receiving and decoding module analyzes received DP video signals and DP auxiliary signals to obtain video pixels, video pixel effective signals, video data information, control information and a DP link clock;
step 2, the phase-locked loop module generates an initial video clock according to the DP link clock and the control information analyzed by the DP receiving and decoding module;
step 3, the video time sequence generating module detects whether the signal output by the DP signal source is a FreeSeSync signal or not according to the control information, and if the signal is the FreeSeSync signal, the Timing information is generated by referring to the control information, wherein the Timing information comprises a line synchronization signal Width HSync _ Width, a distance HSync _ Start from line synchronization to a line effective pixel, a field synchronization signal Width VSync _ Width, a distance VSync _ Start from the field synchronization signal to a field effective line, an effective pixel Width H _ Active of a line video signal and an effective line number V _ Active of a field video signal;
step 4, after detecting a first video pixel effective signal of a frame of video data, the storage control module triggers the video Timing generation module to generate an effective gating signal DE, a field synchronizing signal VSYNC and a line synchronizing signal HSYNC according to the Timing information, and controls the video data caching module to cache a parameter value of the field synchronizing signal Width VSync _ Width + a parameter value of the field synchronizing signal distance VSync _ Start from the field synchronizing signal to the field effective line-1 line of video pixels according to the field synchronizing signal Width VSync _ Width and the parameter value of the field effective line distance VSync _ Start;
step 5, writing the cached video pixels into a double-port first-in first-out module under the control of a storage control module;
step 6, after the video time sequence generation module outputs a field synchronizing signal VSYNC, the effective gating signal DE controls the double-port first-in first-out module to output a video pixel signal;
step 7, the clock recovery control module continuously detects the state of the dual-port first-in first-out module in the V _ Active period, compares the speed of writing video pixel data into the clock recovery control module with the speed of reading the video pixel data, and controls the phase-locked loop module to generate a recovered video clock on the basis of the initial video clock according to the comparison result so as to keep the read-write balance of the video pixel data of the dual-port first-in first-out module;
and 8, after the video time sequence generation module outputs the V _ Active time of one frame of picture, the clock recovery control module stops tracking the generation of the video clock and waits for the DP receiving and decoding module to output the next frame of video data.
3. The method as claimed in claim 2, wherein in step 4, after the clock recovery control module has tracked and stabilized, if the start of the first video pixel signal or the first line of video signals of each frame of video signals is detected, the start edge of the VSync generated by the start edge resynchronization of the next HSync is waited, and the length of the video pixel data buffered by the video data buffer module is adjusted accordingly.
4. The method according to claim 2, wherein in step 7, the clock recovery control module controls the phase-locked loop module to generate the recovered video clock based on the initial video clock according to the comparison result in the following specific manner:
if the double-port first-in first-out module is deflected to be empty, the clock recovery control module controls the phase-locked loop module to increase on the basis of the initial video clock and outputs the increased phase-locked loop module as a recovered video clock;
if the double-port first-in first-out module is biased to be full, the clock recovery control module controls the phase-locked loop module to be lowered on the basis of the initial video clock and outputs the lowered phase-locked loop module as a recovered video clock.
5. The method according to claim 2, wherein the generating Timing information with reference to the control information in step 3 is specifically as follows:
the Width HSync _ Width of the line synchronization signal uses an HSyncWidth field in the control information, and the unit is a pixel point;
the distance HSync _ Start from the line synchronization to the line effective pixel uses an HStart field in the control information, and the unit is a pixel point;
the effective pixel width H _ Active of a line of video signals uses HWidth fields in control information, and the unit is a pixel point;
the effective line number V _ Active of a field of video signal uses a VWidth field in the control information, and the unit is a line;
the field synchronization signal Width VSync _ Width uses a configurable parameter VSW, and the unit is a line;
the distance VSync _ Start of the field sync signal to the field active lines is in lines using the configurable parameter VSS.
6. The method as claimed in claim 2, wherein the phase-locked loop module in step 2 generates the initial video clock by:
counting the time of each line of DP video signals as T1 according to the DP link clock;
calculating the frequency Hfreq = 1/T1 of the line synchronization signal;
acquiring Htotal of each row of pixel points from the control information;
the initial video clock = Hfreq Htotal is calculated.
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