CN115421904A

CN115421904A - Method and device for managing memory, electronic equipment and readable storage medium

Info

Publication number: CN115421904A
Application number: CN202210974392.6A
Authority: CN
Inventors: 刘重力; 朱凌刚
Original assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Current assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Priority date: 2022-08-15
Filing date: 2022-08-15
Publication date: 2022-12-02

Abstract

The application provides a method and a device for managing a memory, an electronic device and a readable storage medium. The method is used for managing a memory, the memory comprises a first memory address space, the first memory address space comprises a first data space of a migratable process and a second data space of a common process, and the first data space and the second data space comprise a plurality of physical address spaces, and the method comprises the following steps: receiving continuous physical address application requests sent by a main device; when the continuous physical address field matched with the physical address request does not exist in the memory, determining a plurality of target physical address spaces to be migrated in the first data space; on which a migration operation is performed to obtain consecutive physical address segments matching consecutive physical address application requests.

Description

Method and device for managing memory, electronic equipment and readable storage medium

Technical Field

The present application relates to the field of chip technologies, and in particular, to a method and an apparatus for managing a memory, an electronic device, and a readable storage medium.

Background

In current larger-scale soc chips, management of memory space in memory is typically based on a 4 KB-grained page table. After the system runs for a period of time, a lot of discrete address segments with 4KB granularity exist in the physical address space of the memory, so that when some new processes request for a larger continuous physical address, for example, request for a 2MB continuous physical address space in the form of a 2MB page table, at this time, software needs to be used to migrate the address segments of some processes in use, so as to free up the larger continuous physical address space for the new processes to use.

The address field occupied by the migration process is a pure software operation, and the problems of high software overhead, occupation of a large amount of CPU (central processing unit) resources and long consumed time exist during execution, so that the creation of a new process is system blockage, and the user experience is influenced.

Disclosure of Invention

The application provides a method and a device for managing a memory, an electronic device and a readable storage medium. Various aspects of embodiments of the present application are described below.

In a first aspect, a method for managing a memory is provided, where the memory includes a first memory address space, the first memory address space includes a first data space of a migratable process and a second data space of a common process, and the first data space and the second data space include multiple physical address spaces, the method including: receiving continuous physical address application requests sent by a main device; when the continuous physical address section matched with the continuous physical address application request does not exist in the memory, determining a plurality of target physical address spaces to be migrated in the first data space; and executing the migration operation on the target physical address spaces to be migrated to obtain a continuous physical address segment matched with the continuous physical address application request.

In a second aspect, an apparatus for managing a memory is provided, where the memory includes a first memory address space, the first memory address space includes a first data space of a migratable process and a second data space of a common process, and the first data space and the second data space include a plurality of physical address spaces, the apparatus including: a receiving unit, configured to receive continuous physical address application requests sent by a master device; a first determining unit, configured to determine, when there is no continuous physical address segment matching the continuous physical address application request in the memory, a plurality of target physical address spaces to be migrated in the first data space; and the migration unit executes migration operation on the target physical address spaces to be migrated to obtain continuous physical address segments matched with the continuous physical address application requests.

In a third aspect, an electronic device is provided, comprising: at least one host device, a memory, and a hardware accelerator; in the process of obtaining, the hardware accelerator is arranged between the at least one main device and the memory and is used for managing the memory; the memory comprises a first memory address space, the first memory address space comprises a first data space of a migratable process and a second data space of a common process, and the first data space and the second data space comprise a plurality of physical address spaces; the hardware accelerator is configured to: receiving continuous physical address application requests sent by a master device; when the continuous physical address section matched with the continuous physical address application request does not exist in the memory, determining a plurality of target physical address spaces to be migrated in the first data space; and executing the migration operation on the target physical address spaces to be migrated to obtain a continuous physical address segment matched with the continuous physical address application request.

In a fourth aspect, there is provided an electronic device comprising a memory for storing computer-executable instructions and a processor for executing the computer-executable instructions, when executed by the processor, implementing the method of the first aspect.

In a fifth aspect, a computer-readable storage medium is provided, wherein the storage medium stores computer-executable instructions, which when executed, implement the method according to the first aspect.

According to the memory management method provided by the embodiment of the application, the first data space used for storing the preset migratable process data is arranged in the memory, when continuous physical address application requests are received, the target physical address space needing to be migrated is determined from the first data space, and the data in the target physical address space are migrated, so that the physical address section meeting the requirements is obtained. The migration efficiency of the page table can be improved by migrating the physical address space of the preset migratable process, and meanwhile, the influence of the migration of the data stored in the part of the address space on the whole system is small, so that the CPU resource can be released, and the user experience is improved.

Drawings

Fig. 1 is a schematic flow chart of memory large page allocation in the related art.

Fig. 2 is a schematic diagram illustrating distribution of data spaces in a memory in the related art.

Fig. 3 is a schematic structural diagram of a memory to which the method provided in the embodiment of the present application is applied.

Fig. 4 is a schematic flow chart of a method for managing a memory according to an embodiment of the present application.

Fig. 5 is a schematic diagram illustrating a distribution of multiple physical address spaces in a memory according to an embodiment of the present application.

Fig. 6 is a schematic structural diagram of an apparatus for managing memory according to an embodiment of the present application.

Fig. 7 is a schematic structural diagram of an electronic device provided in an embodiment of the present application.

Fig. 8 is a schematic structural diagram of an electronic device according to another embodiment of the present application.

Detailed Description

The embodiments of the present application will be described below with reference to the drawings.

The terms "first," "second," "third," and "fourth," etc. in the description and claims of this application and in the accompanying drawings are used for distinguishing between different objects and not for describing a particular order; and the terms "first," "second," "third," and "fourth," etc., may describe objects that are the same, or have an inclusive or other relationship to each other. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements but may alternatively include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein may be combined with other embodiments.

As used in this specification, the terms "component," "module," "system," and the like are intended to refer to a computer-related entity, either hardware, firmware, a combination of hardware and software, or software in execution. For example, a component may be, but is not limited to being, a process running on a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a computing device and the computing device can be a component. One or more components can reside within a process and/or thread of execution and a component can be localized on one computer and/or distributed between 2 or more computers. In addition, these components can execute from various computer readable media having various data structures stored thereon. The components may communicate by way of local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from two components interacting with another component in a local system, distributed system, and/or across a network such as the internet with other systems by way of the signal).

Before describing the embodiments of the present application, a detailed example of a memory management method and its existing problems in the related art will be described.

In a current larger-scale System On Chip (SOC) chip, if a more complex operating system, such as an android operating system, a Linux operating system, etc., is involved, the operating system is generally required to manage a memory space such as a memory based on a virtual address. The mapping relationship from the virtual address to the physical address is stored in the memory in the form of a page table.

In the android system, a 4 Kilobyte (KB) granularity is generally used as the granularity for managing the page table, i.e., the memory is divided into a plurality of memory blocks of 4KB in size for management. After the android system runs for a period of time, there are many used 4 KB-granularity discrete address segments in the system physical address space, and the unused address segments that can be found at this time are scattered by these 4KB address segments, which is called fragmentation of the address space.

In a scene such as photo or video shooting, a new process requests a larger continuous physical address space, for example, a continuous physical address space with a capacity of 2MB in the form of a 2 Megabyte (MB) page table at a time. To be able to find such a larger contiguous physical address space, the operating system migrates the address segments occupied by some of the processes in use, freeing up the larger contiguous physical address space for use by new processes.

The above process is illustrated in detail below with reference to fig. 1 and 2. Fig. 1 is a schematic flow chart of memory large page allocation in the related art. Fig. 2 is a schematic diagram illustrating distribution of data spaces in a memory in the related art.

Referring to fig. 1, in step S11, the peripheral device initiates a request for applying a physical address, where the request message includes information such as the size of a continuous address field applied by the peripheral device. For example, the address field indicated by the address application request is 2MB of contiguous addresses.

In step S12, after receiving the request message sent by the peripheral device, software is used to detect whether there are consecutive physical addresses in the current memory.

The 2MB contiguous address space above is taken as an example. If there are 2MB consecutive physical addresses in the current memory, the distribution of the page table and the corresponding data space in the memory is the situation shown in fig. 2 (a), which shows 512 consecutive data spaces, wherein each data space is 4KB in size. It should be understood that each square in fig. 2 represents a data space, or may be referred to as a block of data in memory, where the data space labeled as grid lines is the currently occupied data space.

At this time, step S13 is executed to transfer data using the continuous physical addresses.

When there are no consecutive physical addresses in the current memory, the distribution of the page tables and the corresponding data spaces in the memory is as shown in fig. 2 (b), and each data space is a data block with a capacity of 4KB as in the case shown in fig. 2 (a). As can be seen from fig. 2 (b), in this case, there are a plurality of occupied data spaces in the memory, so that there are not 512 consecutive data spaces at this time to satisfy the above-mentioned requirement of 2MB address space.

At this point step S14 is performed to migrate the process address segment using software to create a larger contiguous physical address segment. Referring again to FIG. 2 (b), the data in data block 21 may be migrated back, for example, as in FIG. 2 (b). As shown in fig. 2 (c), the data space distribution after migration is that due to data migration in the data block 21, there are 512 continuous unoccupied data spaces in the memory, and the total capacity of the data spaces is 2MB, which can satisfy the transmission request of the peripheral device.

After the continuous physical address segment is obtained, step S15 is executed to build a table for the continuous physical address segment mapping. And establishing a mapping relation between the physical address of the continuous data space obtained in the previous step and the virtual address in the transmission request, using the mapping relation as a new page table entry, and storing the new page table entry into a page table of a memory.

After step S15, step S13 is performed to transfer data using consecutive physical addresses.

As can be seen from the above steps, in the related art, in the memory management method based on the 4KB granularity, when there is a request for a larger memory page, the efficiency of migrating a large number of address segments is low, and a large amount of time delay is generated. Meanwhile, in the related art, the migration of the address field is pure software operation, the software overhead is high, a large amount of CPU resources are required to be occupied, and meanwhile, the migration completion time can be too long, so that the system is blocked when a new process is created.

In order to solve the foregoing problems, embodiments of the present application provide a method and an apparatus for managing a memory, an electronic device, and a readable storage medium.

The following first illustrates embodiments of the method of the present application in detail with reference to the accompanying drawings. The method provided by the embodiment of the present application is used for memory management, and therefore, before introducing the method embodiment, a structure of a memory to which the method provided by the present application is applied is described by way of example.

Referring to fig. 3, the memory 30 includes a first memory address space 31 and a second memory address space 32. The first memory address space 31 is used to store data of each peripheral or multiple processes, and the second memory address space 32 is used to store page table entries of multiple data blocks in the first memory address space 31, where the page table entries are used to indicate a corresponding relationship between a virtual address and a physical address of multiple data blocks and a state of each data block.

It should be understood that the first memory address space 31 and the second memory address space 32 are not two completely independent storage spaces, but only two virtual storage spaces in the memory, and the size of the first memory address space 31 and the second memory address space 32 may be divided according to actual situations, for example, in some scenarios, more page table entries may need to be stored, and at this time, the capacity of the second memory address space 32 may be increased while the first memory address space 31 is reduced. For another example, when the data throughput is larger, the size of the first memory address space 31 may be correspondingly increased, so that more storage space is available for buffering the data in the storage unit. In other words, the first memory address space 31 and the second memory address space 32 share the storage space in the memory, and can be flexibly adjusted according to the actual situation.

With continued reference to fig. 3, the first memory address space 31 includes a first data space 311 of the migratable process and a second data space 312 of the normal process, wherein the first data space 311 and the second data space 312 include a plurality of

physical address spaces

3111 and 3121, respectively.

In some embodiments, the first data space 311 and the second data space 312 may be a segment of memory address space pre-allocated by software. It should be further noted that, similar to the foregoing first memory address space 31 and second memory address space 32, in this embodiment of the application, the first data space 311 and second data space 312 are not physically independent two storage spaces, and the capacities of the two storage spaces may be adjusted according to actual situations, for example, when there are more consecutive physical address application requests in the read/write request of the host device, the size of the first data space 311 may be increased, so as to improve the speed of data read/write.

In some embodiments, the plurality of

physical address spaces

3111 and 3121 may also be understood as a plurality of data blocks in a memory. Among them, the plurality of physical address spaces 3111 in the first data space 311 are physical address spaces dedicated to migratable processes. The migratable process may be, for example, a non-system process or a process that is not frequently called by the system, and the physical address space occupied by the process and the corresponding page table occupy fewer system resources such as CPUs and the like during migration, and the migration efficiency is higher.

When the read-write instruction of the host device includes a continuous physical address application request, the physical address space occupied by the migratable process may be migrated, so that a physical address segment matched with the continuous physical address application request can be obtained in the first data space 311.

With continued reference to fig. 3, the second memory address space 32 includes a first page table space 321 and a second page table space 322, wherein the first page table space 321 stores a plurality of page table entries corresponding to the plurality of physical address spaces 3111 in the first data space 311, and the second page table space 322 stores a plurality of page table entries corresponding to the plurality of physical address spaces 3121 in the second data space 312.

It should be understood that the first page table space 321 and the second page table space 322 are not two completely independent memory spaces, but only two virtual memory spaces in the memory, and the size of the first page table space 321 and the second page table space 322 may be matched with the number of physical address spaces in the first data space 311 and the second data space 312.

The method for managing memory provided in the embodiment of the present application is described in detail below with reference to fig. 4, and the method shown in fig. 4 may be applied to the memory shown in fig. 3, where the method includes steps S41 to S43.

In step S41, consecutive physical address application requests sent by the master device are received.

The master device may be, for example, a component in an SOC of a CPU, a GPU, an NPU, an APU, an ISP, and the like in the electronic device, or may also be a multimedia device that is disposed outside the SOC, such as a video playing device, an audio playing device, and the like, and the embodiment of the present application is not limited to a specific type of the master device.

In some embodiments, the continuous physical address application request may be included in a data read/write request of the master device.

Thus, in some embodiments, the method in the examples of the present application may further include: analyzing a data read-write request of the main equipment, and determining a continuous physical address request contained in the data read-write request.

In some embodiments, when there is a continuous physical address segment matching the continuous physical address request in the memory, the operations such as reading and writing of data can be directly performed in the continuous physical address segment, without performing operations such as data migration on data blocks in the memory.

Fig. 5 shows a distribution of a plurality of physical address spaces in a memory in the embodiment of the present application. The following describes the above process with reference to fig. 5 (a), taking the example of continuous physical address application requests as a continuous physical address space with a request capacity of 2 MB. As shown in fig. 5 (a), the memory includes a first memory address space 51 and a second memory address space 52, wherein the first memory address space 51 further includes a first data space 511 and a second data space 512, wherein a plurality of physical address spaces (such as a plurality of grid regions shown in the figure) in the first data space 511 are physical address spaces of migratable processes, and a plurality of physical addresses in the second data space 512 are physical address spaces of normal processes.

The plurality of physical address spaces 511A, \8230; 511N which are not occupied in the first data space 511 shown in fig. 5 (a) are consecutive physical address segments which match the consecutive physical address application requests as described above, and at this time, data reading and writing can be performed on values in the physical address segments.

It should be understood that the plurality of physical address spaces 511A, \ 8230; 511N in the first data space 511 shown in fig. 5 (a) is merely an example. In fact, in the embodiment of the present application, the continuous physical address segment may be in any location of the memory, for example, the physical address segment may also be a plurality of continuous physical address spaces in the second data space 512; alternatively, the consecutive physical address segments may also include a part of the physical address space in both the first data space 511 and the second data space 512, which is not specifically limited in this embodiment of the application.

When there is no continuous physical address segment matching the continuous physical address application request in the memory, that means the address space in the memory represents fragmented data blocks, then it is necessary to migrate a part of the data blocks in the memory.

In step S42, a plurality of target physical address spaces to be migrated in the first data space are determined.

Referring to fig. 5 again, fig. 5 (b) illustrates the above situation, the memory shown in fig. 5 (b) includes a first memory address space 53 and a second memory address space 54, wherein the first memory address space 53 further includes a first data space 531 and a second data space 532, and each of the first data space 531 and the second data space 532 includes a plurality of physical address spaces. Second memory address space 54 includes a plurality of first page table entries 5411A, \8230; 5411N stored in first page table space 541 and a plurality of second page table entries 5421A, \8230; 5421N stored in second page table space 542. The first page table entries 5411A, \ 82305411N and the second page table entries 5421A, \ 8230, 5421N correspond to the physical address spaces in the first data space 531 and the second data space 532, respectively.

As described above, data of the migratable processes are all stored in the first data space 531, and therefore, in the embodiment of the present application, selection of multiple target physical address spaces to be migrated needs to be performed in the first data space, that is, only data in the physical address space occupied by the migratable processes is migrated.

It is understood that, for each physical address space, the address information and the current state information of the physical address space are recorded in the corresponding page table entry.

Thus, in some embodiments, the plurality of target physical address spaces to be migrated in the first data space may be determined from page tables of the plurality of physical address spaces in the first data space.

The method for determining the target data space is illustrated below with reference to fig. 5 (b): the physical address space in the plurality of physical address spaces that is in the occupied state at the current time is determined by traversing and searching the plurality of first page table entries 5411A, \8230'. 5411N in the first page table space 541. For example, if a certain page table entry (e.g., page table entry 5411G) in fig. 5 (b) indicates that at the current time, the corresponding physical address space (e.g., physical address space 5311G in the figure) is in a state occupied by data, the physical address space is taken as one of the target physical address spaces to be migrated.

In step S43, a migration operation is performed on the data in the target physical address spaces to be migrated, and a continuous physical address segment matched with the continuous physical address application request is obtained.

Taking fig. 5 as an example, the migration operation is performed on the physical address space 5311G, for example, the data stored in the physical address space can be moved to the last bit of the first data space 531, and the distribution of the physical address space after migration can be seen in fig. 5 (c). In fig. 5 (c), after the data in the physical address space 5311G is migrated, a plurality of physical address spaces 5311A, \ 8230and 5311N which are not occupied by the data are obtained, and the plurality of physical address spaces 5311A, \8230and5311N are the continuous physical address segments.

In some embodiments, after determining a continuous physical address segment matching the physical address application request according to the above steps S41 to S43, the master device may be controlled to perform operations such as reading and writing data in the continuous physical address segment.

According to the memory management method provided by the embodiment of the application, the first data space used for storing the preset migratable process data is arranged in the memory, when continuous physical address application requests are received, the target physical address space needing to be migrated is determined from the first data space, and the data in the target physical address space are migrated, so that the physical address section meeting the requirements is obtained. The efficiency of page table migration can be improved by migrating the physical address space of the preset migratable process, and meanwhile, the influence of migration of data stored in the part of address space on the whole system is small, so that CPU resources can be released, and user experience is improved.

In some embodiments, since the data in the target physical address spaces are migrated, the page table entries corresponding to the target physical address spaces also need to be updated. In other words, after determining consecutive physical address segments matching consecutive physical address application requests, the method of the embodiment of the present application further includes: and updating a plurality of first page table entries in the first page table space, which are matched with the target physical address spaces.

By updating the first page table entries of the target physical address spaces, the actual physical addresses can be quickly acquired from the first page table spaces when the main device needs to access the target physical address spaces in the subsequent data reading and writing process.

The method embodiment of the present application is described above with reference to fig. 1 to 5, and the apparatus embodiment of the present application is described in detail below with reference to the accompanying drawings. It should be understood that the description of the apparatus embodiments corresponds to the method embodiments and therefore reference may be made to the preceding description of the method embodiments for parts that are not described in detail.

Fig. 6 is a schematic structural diagram of an apparatus for managing a memory according to an embodiment of the present application, where the apparatus in fig. 6 is configured to manage a memory, where the memory may be the memory according to any of the foregoing embodiments, and the memory includes a first memory address space, where the first memory address space includes a first data space of a migratable process and a second data space of a normal process, and the first data space and the second data space include multiple physical address spaces.

The apparatus 60 in fig. 6 comprises:

the receiving unit 61 is configured to receive consecutive physical address application requests sent by a master device.

A first determining unit 62, configured to determine, when there is no continuous physical address segment matching the continuous physical address application request in the memory, a plurality of target physical address spaces to be migrated in the first data space.

And a migration unit 63, configured to perform a migration operation on the multiple target physical address spaces to be migrated, so as to obtain a continuous physical address segment matched with the continuous physical address application request.

Optionally, the memory further includes a second memory address space, where the second memory address space includes: a first page table space for storing a plurality of page table entries of the first data space and a second page table space for storing a plurality of page table entries of the second data space; the second determination unit is configured to: traversing the plurality of page table entries in the first page table space, determining a plurality of physical address information in the plurality of page table entries; and determining a plurality of target physical address spaces needing to be migrated in the first data space according to the plurality of physical address information and the size of the address field indicated by the continuous physical address application request.

Optionally, the apparatus 60 further comprises: and the updating unit is configured to update the physical address information of a plurality of page table entries matched with the continuous physical address segments in the first page table space after the migration operation is performed on the plurality of target physical address spaces to be migrated.

An embodiment of the present application further provides an electronic device, and fig. 7 is a schematic structural diagram of the electronic device 70. The electronic device 70 in fig. 7 includes:

at least one host device 71, a memory 72, and a hardware accelerator 73, wherein the hardware accelerator 73 is disposed between the host device 71 and the memory 72, and is configured to manage the memory.

The memory 72 may be, for example, the memory shown in fig. 5, where the memory 72 includes a first memory address space, the first memory address space includes a first data space of a migratable process and a second data space of a normal process, and the first data space and the second data space include a plurality of physical address spaces.

The hardware accelerator 73 is configured to: receiving continuous physical address application requests sent by a main device; when the continuous physical address section matched with the continuous physical address application request does not exist in the memory, determining a plurality of target physical address spaces to be migrated in the first data space; and executing the migration operation on the target physical address spaces to be migrated to obtain a continuous physical address segment matched with the continuous physical address application request.

The at least one host device 71 is configured to, after migrating a target physical address space to be migrated by using the hardware accelerator 73 to obtain a continuous physical address segment, perform data reading and writing in the continuous physical address segment.

Optionally, the memory further includes a second memory address space, where the second memory address space includes: a first page table space for storing a plurality of first page table entries of the first data space and a second page table space for storing a plurality of second page table entries of the second data space.

The determining a plurality of target physical address spaces to be migrated in the first data space includes: traversing the plurality of first page table entries in the first page table space, and determining a plurality of physical address information in the plurality of first page table entries; and determining the target data spaces to be migrated according to the physical address information and the size of the address field indicated by the continuous physical address application request.

Optionally, after determining the consecutive physical address segments matching the consecutive physical address application requests, the hardware accelerator is further configured to: and updating the physical address information of a plurality of page table entries in the first page table space which are matched with the continuous physical address segment.

Fig. 8 is a schematic structural diagram of an electronic device 80 provided in an embodiment of the present application, where the electronic device may be, for example, a mobile terminal device. The electronic device 80 comprises a memory 81 and a processor 82. Wherein the memory 81 is adapted to store executable code and the processor 82 is adapted to execute the executable code, which when executed by the processor implements the method steps as described above.

In some embodiments, the electronic device 80 further includes a network interface 83, and data exchange between the processor 82 and an external device can be achieved through the network interface 83.

The embodiment of the application also provides a readable storage medium for storing the program. The computer-readable storage medium can be applied to the terminal device or the network device provided in the embodiments of the present application, and the program causes the computer to execute the method performed by the terminal device or the network device in the embodiments of the present application.

The embodiment of the application also provides a computer program product. The computer program product includes a program. The computer program product can be applied to the terminal device or the network device provided in the embodiments of the present application, and the program causes the computer to execute the method performed by the terminal device or the network device in the embodiments of the present application.

The embodiment of the application also provides a computer program. The computer program can be applied to the terminal device or the network device provided in the embodiments of the present application, and the computer program enables a computer to execute the method performed by the terminal device or the network device in the embodiments of the present application.

In the above embodiments, all or part of the implementation may be realized by software, hardware, firmware or any other combination. When implemented in software, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. The procedures or functions described in accordance with the embodiments of the disclosure are all or partially produced when the computer program instructions are loaded and executed on a computer. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions can be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., a floppy Disk, a hard Disk, a magnetic tape), an optical medium (e.g., a Digital Video Disc (DVD)), or a semiconductor medium (e.g., a Solid State Disk (SSD)), among others.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

In the several embodiments provided in the present disclosure, it should be understood that the disclosed system, apparatus, and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method for managing a memory, wherein the memory includes a first memory address space, the first memory address space includes a first data space of a migratable process and a second data space of a common process, the first data space and the second data space include a plurality of physical address spaces, the method comprising:

receiving continuous physical address application requests sent by a master device;

when the continuous physical address segments matched with the continuous physical address application requests do not exist in the memory, determining a plurality of target physical address spaces to be migrated in the first data space;

and executing the migration operation on the target physical address spaces to be migrated to obtain a continuous physical address segment matched with the continuous physical address application request.

2. The method of claim 1,

the memory further includes a second memory address space, where the second memory address space includes: a first page table space for storing a plurality of first page table entries of the first data space and a second page table space for storing a plurality of second page table entries of the second data space;

the determining a plurality of target physical address spaces to be migrated in the first data space includes:

traversing the first page table entries in the first page table space, and determining a plurality of physical address information in the first page table entries;

and determining the target data spaces to be migrated according to the physical address information and the size of the address field indicated by the continuous physical address application request.

3. The method of claim 2, wherein after performing the migration operation on the plurality of target physical address spaces to be migrated, the method further comprises:

and updating a plurality of first page table entries matched with the target physical address spaces in the first page table space.

4. An apparatus for managing a memory, the memory including a first memory address space, the first memory address space including a first data space of a migratable process and a second data space of a common process, the first data space and the second data space including a plurality of physical address spaces, the apparatus comprising:

a receiving unit, configured to receive continuous physical address application requests sent by a master device;

a first determining unit, configured to determine, when there is no continuous physical address segment matching the continuous physical address application request in the memory, a plurality of target physical address spaces to be migrated in the first data space;

and the migration unit executes migration operation on the target physical address spaces to be migrated to obtain continuous physical address segments matched with the continuous physical address application requests.

5. The apparatus of claim 4,

the memory further includes a second memory address space, where the second memory address space includes: a first page table space for storing a plurality of page table entries of the first data space and a second page table space for storing a plurality of page table entries of the second data space;

the second determination unit is configured to:

traversing the plurality of page table entries in the first page table space, and determining a plurality of physical address information in the plurality of page table entries;

and determining a plurality of target physical address spaces needing to be migrated in the first data space according to the plurality of physical address information and the size of the address field indicated by the continuous physical address application request.

6. The apparatus of claim 5, further comprising:

and the updating unit is configured to update the physical address information of a plurality of page table entries matched with the continuous physical address segments in the first page table space after the migration operation is performed on the plurality of target physical address spaces to be migrated.

7. An electronic device, comprising:

at least one host device, a memory, and a hardware accelerator;

in the process of the operation, the hardware accelerator is arranged between the at least one main device and the memory and is used for managing the memory;

the memory comprises a first memory address space, the first memory address space comprises a first data space of a migratable process and a second data space of a common process, and the first data space and the second data space comprise a plurality of physical address spaces;

the hardware accelerator is configured to:

receiving continuous physical address application requests sent by a main device;

8. The electronic device of claim 7,

9. The electronic device of claim 8, wherein after performing the migration operation on the plurality of target physical address spaces to be migrated, the hardware accelerator is further to:

and updating the physical address information of a plurality of page table entries in the first page table space, which are matched with the continuous physical address segment.

10. An electronic device comprising a memory for storing executable code and a processor for executing the executable code, the executable code when executed by the processor implementing the method of any one of claims 1-3.

11. A computer-readable storage medium characterized in that the storage medium stores executable code that, when executed, implements the method of any of claims 1-3.