CN115411102A - Cold source transistor device and preparation method thereof - Google Patents

Abstract

The present disclosure provides a cold source transistor device, comprising: the cold source layer is arranged on the substrate layer; wherein the cold source layer is prepared by a cold source material capable of opening a band gap; the transition region is arranged on the substrate layer and is connected with the cold source layer; the channel layer is arranged on the substrate layer and is connected with the transition region; at least part of the first gate dielectric layer is formed on the part of the channel layer, and at least part of the first gate dielectric layer is formed on the part of the transition region; and the first gate electrode is arranged on the first gate dielectric layer. The disclosure also provides a method for manufacturing the cold source transistor device.

Description

Cold source transistor device and preparation method thereof

Technical Field

The disclosure relates to a cold source transistor device and a method for manufacturing the same.

Background

The integrated circuit industry, which is centered on silicon-based CMOS (metal oxide semiconductor) technology, is continuously striving for higher performance, lower power consumption, and higher integration. However, as the feature size of the device is reduced to 5nm and below, the performance improvement of the silicon-based CMOS is much smaller than the increasing power consumption, so the development trend of the integrated circuit is gradually changed from the pursuit of the improvement of performance and integration level to the reduction of power consumption, and the most effective method for reducing dynamic power consumption is to reduce the operating voltage.

The power consumption is reduced, the Subthreshold Swing (SS) of the field effect transistor is reduced fundamentally, the theoretical limit of a silicon-based field effect transistor (SS) at room temperature is broken through by 60mV/dec, and meanwhile, other performance indexes such as on-state current, on-off ratio and the like of the transistor are not reduced.

The main sub-60 mV/dec devices at present are: a tunneling transistor, a negative capacitance transistor and a cold source transistor. A Dirac source transistor in the cold source transistor takes graphene as a source and a low-dimensional semiconductor material (such as a carbon nano tube and single-layer molybdenum sulfide) as a conducting channel, and is a sub-60 mV/dec device with better performance in the current experiment. For example, the Dirac source PMOS made by using a single carbon nano tube channel can realize 40mV/dec, the sub-60 characteristic can maintain 4 orders of magnitude, I60 reaches 40 muA/mum, and the working voltage can be reduced to 0.5V; if the channel material is replaced by the carbon nano tube array, the performance of the device can reach the performance index of the CMOS predicted by an international device and system roadmap (IRDS) in 2034 years theoretically.

However, taking the N-type dirac source transistor as an example, when the conduction band bottom of the gate-regulated semiconductor channel and the dirac point in the dirac source are at equal potentials, the gate voltage continues to increase in the forward direction, and since the electron density in the upper half dirac cone is an increasing function with the energy, the SS at each point thereafter is greater than 60mV/dec, thereby increasing the power consumption and the switching speed of the dirac source transistor.

Disclosure of Invention

In order to solve one of the above technical problems, the present disclosure provides a cold source transistor device and a method for manufacturing the same.

According to one aspect of the present disclosure, there is provided a heat sink transistor device comprising:

a base layer, a substrate layer,

the cold source layer is arranged on the substrate layer; wherein the cold source layer is prepared by a cold source material capable of opening a band gap;

the transition region is arranged on the substrate layer and is connected with the cold source layer;

the channel layer is arranged on the substrate layer and is connected with the transition region;

at least part of the first gate dielectric layer is formed on the part of the channel layer, and at least part of the first gate dielectric layer is formed on the part of the transition region; and

and the first gate electrode is arranged on the first gate dielectric layer.

According to the cold source transistor device of at least one embodiment of the present disclosure, the cold source layer is made of a double-layer graphene material.

The heat sink transistor device according to at least one embodiment of the present disclosure, further includes:

the second gate dielectric layer is at least partially formed on the part of the cold source layer; and

the second gate electrode is arranged on the second gate dielectric layer; wherein an electric field perpendicular or substantially perpendicular to the heat sink layer is applied to the heat sink layer by controlling the second gate electrode.

According to the transistor device of the cold source of at least one embodiment of the present disclosure, the transition region is prepared by single-layer graphene or double-layer graphene which is not regulated by an electric field.

The heat sink transistor device according to at least one embodiment of the present disclosure, further includes:

a first electrode, a part of which is disposed on the base layer, a part of which is disposed on the cold source layer, and which enables electrical conduction between the first electrode and the cold source layer; and

a second electrode, a portion of which is disposed on the base layer and a portion of which is disposed on the channel layer, and which enables electrical conduction between the second electrode and the channel layer.

According to the cold source transistor device of at least one embodiment of the present disclosure, the first electrode and the second electrode have a predetermined interval therebetween, wherein a majority of the area of the cold source layer and a majority of the area of the stripe layer are located at an area between the first electrode and the second electrode.

According to the cold source transistor device of at least one embodiment of the present disclosure, the first electrode and the first gate dielectric layer have a preset interval therebetween.

In accordance with at least one embodiment of the present disclosure, the first gate dielectric layer covers at least part of a sidewall of the second electrode and/or covers at least part of an upper surface of the second electrode.

According to the heat sink transistor device of at least one embodiment of the present disclosure, a connection direction of the heat source layer and the channel layer is a length direction of the heat source layer and the channel layer.

According to the cold source transistor device of at least one embodiment of the present disclosure, the first gate dielectric layer extends across both ends of the channel layer in the width direction of the cold source layer and the channel layer, and the width of the first gate dielectric layer is made larger than the width of the channel layer and the cold source layer.

In accordance with a heat sink transistor device of at least one embodiment of the present disclosure, the channel layer is fabricated from a two-dimensional semiconductor material or a quasi-one-dimensional array of materials.

According to another aspect of the present disclosure, there is provided a method for manufacturing a heat sink transistor device, which can manufacture the heat sink transistor device, the method comprising:

s101, preparing a basal layer;

s102, manufacturing a cold source layer and a transition region on the substrate layer through multiple exposure and phase shift mask technology;

s103, forming a channel layer on the substrate layer;

s104, depositing a first electrode on the substrate layer and the cold source layer, and depositing a second electrode on the substrate layer and the channel layer;

s105, forming a first gate dielectric layer on the part of the substrate layer, the part of the channel layer and the part of the transition region;

and S106, growing gate metal on the first gate dielectric layer to form a first gate electrode.

According to the manufacturing method of the cold source transistor device of at least one embodiment of the present disclosure, the cold source layer is formed as double-layer graphene controlled by an electric field, the transition region is formed as double-layer graphene, and the channel layer is formed as a double-layer graphene nanoribbon.

According to the method of manufacturing the cold source transistor device of at least one embodiment of the present disclosure, when the cold source layer, the transition region, and the channel layer are all formed by the double-layer graphene, the cold source layer, the transition region, and the channel layer are simultaneously formed by the multiple exposure, phase shift mask technique.

According to the preparation method of the cold source transistor device of at least one embodiment of the present disclosure, when the cold source layer is double-layer graphene, the preparation method further includes:

s107, forming a second gate dielectric layer on the base layer part and the cold source layer part; and

and S108, growing gate metal on the second gate dielectric layer to form a second gate electrode.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

Fig. 1 and 2 are schematic structural diagrams of a heat sink transistor device according to one embodiment of the present disclosure.

Fig. 3 and 4 are schematic structural diagrams of a heat sink transistor device according to another embodiment of the present disclosure.

Fig. 5 is a schematic diagram of a structure-energy band correspondence for a heat sink transistor device, according to one embodiment of the present disclosure.

FIG. 6 is a sub-threshold region energy band diagram of a cold source transistor device according to one embodiment of the present disclosure.

Fig. 7 is an on-band schematic diagram of a heat sink transistor device according to one embodiment of the present disclosure.

Fig. 8 is a graph comparing transfer characteristics of a heat sink transistor device and a conventional transistor according to one embodiment of the present disclosure.

Fig. 9 and 10 are process flow diagrams of the fabrication of a heat sink transistor device according to various embodiments of the present disclosure.

The reference numbers in the figures are in particular:

100. cold source transistor device

110. Base layer

120. Cold source layer

130. Transition zone

140. Channel layer

150. First gate dielectric layer

160. A first gate electrode

170. A first electrode

180. Second electrode

190. Second gate dielectric layer

200. A second gate electrode

Detailed Description

The present disclosure will be described in further detail with reference to the drawings and embodiments. It is to be understood that the specific embodiments described herein are for purposes of illustration only and are not to be construed as limitations of the present disclosure. It should be further noted that, for the convenience of description, only the portions relevant to the present disclosure are shown in the drawings.

It should be noted that the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. Technical solutions of the present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Unless otherwise indicated, the illustrated exemplary embodiments/examples are to be understood as providing exemplary features of various details of some ways in which the technical concepts of the present disclosure may be practiced. Accordingly, unless otherwise indicated, features of the various embodiments may be additionally combined, separated, interchanged, and/or rearranged without departing from the technical concept of the present disclosure.

The use of cross-hatching and/or shading in the drawings is generally used to clarify the boundaries between adjacent components. As such, unless otherwise noted, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, proportion, commonality between the illustrated components and/or any other characteristic, attribute, property, etc., of a component. Further, in the drawings, the size and relative sizes of components may be exaggerated for clarity and/or descriptive purposes. While example embodiments may be practiced differently, the specific process sequence may be performed in a different order than that described. For example, two processes described consecutively may be performed substantially simultaneously or in reverse order to that described. In addition, like reference numerals denote like parts.

When an element is referred to as being "on" or "over," "connected to" or "coupled to" another element, it can be directly on, connected or coupled to the other element or intervening elements may be present. However, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element, there are no intervening elements present. For purposes of this disclosure, the term "connected" may refer to physically connected, electrically connected, and the like, with or without intervening components.

For descriptive purposes, the present disclosure may use spatially relative terms such as "under 8230; \8230;,"' under 8230; \8230; below 8230; under 8230; above, on, above 8230; higher "and" side (e.g., as in "side wall)", etc., to describe the relationship of one component to another (other) component as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and/or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "at 8230 \8230;" below "may encompass both an orientation of" above "and" below ". Further, the devices may be otherwise positioned (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, when the terms "comprises" and/or "comprising" and variations thereof are used in this specification, the presence of stated features, integers, steps, operations, elements, components and/or groups thereof are stated but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof. It is also noted that, as used herein, the terms "substantially," "about," and other similar terms are used as approximate terms and not as degree terms, and as such, are used to interpret inherent deviations in measured values, calculated values, and/or provided values that would be recognized by one of ordinary skill in the art.

Fig. 1 and 2 are schematic structural diagrams of a heat sink transistor device according to one embodiment of the present disclosure. Fig. 3 and 4 are schematic structural diagrams of a heat sink transistor device according to another embodiment of the present disclosure.

Referring to fig. 1 to 4, according to an embodiment of the present disclosure, a cold source transistor device 100 of the present disclosure includes a substrate layer 110, a cold source layer 120, a transition region 130, a channel layer 140, a first gate dielectric layer 150, and a first gate electrode 160.

In the present disclosure, the base layer 110 may be a silicon wafer covered with silicon dioxide, and the substrate layer 110 may also be made of glass, quartz, ITO, or flexible PI, PET, or the like.

According to an embodiment of the present disclosure, the heat sink layer 120 of the heat sink transistor device 100 of the present disclosure is disposed on the substrate layer 110, wherein the heat sink layer 120 is made of a heat sink material capable of opening a band gap, that is, a heat sink material with a certain band gap and a carrier state density that decreases with an increase in energy is used.

In one embodiment, as shown in fig. 3 and 4, the cold source layer 120 is made of a double-layer graphene material, which has no band gap but can be gated so that the double-layer graphene has an openable band gap; in another embodiment, as shown in fig. 1 and 2, the cold source layer can be prepared from doped single layer graphene, which itself has a bandgap.

Preferably, the cold source layer 120 and the channel layer 140 of the present disclosure employ an N-type doped two-dimensional cold source material or a P-type doped two-dimensional cold source material. The cold source transistor device 100 is an NMOS transistor device, and a P-type doped two-dimensional cold source material is adopted; the cold source transistor device 100 is a PMOS transistor device, and adopts an N-type doped two-dimensional cold source material; furthermore, for different doped heat sink materials, metals with different work functions should be selected as the first electrode or the second electrode.

In the present disclosure, the transition region 130 is disposed on the substrate layer 110 and connected to the cold source layer 120; thus, by gating the transition region 130, klein tunneling or an effect similar to Klein tunneling (a tunneling coefficient of about 1) is achieved. In one embodiment, the transition region 130 is prepared from single layer graphene or double layer graphene that is not modulated by an electric field. In one embodiment, when both the heat sink layer 120 and the transition region 130 are prepared from bi-layer graphene, they can be formed on the substrate layer 110 at the same time.

The channel layer 140 is disposed on the substrate layer 110 and connected to the transition region 130; in a preferred embodiment, the channel layer 140 is fabricated from a two-dimensional semiconductor material or a quasi-one-dimensional material array; more specifically, the two-dimensional semiconductor material may be molybdenum disulfide, two-dimensional indium arsenide, or the like; the quasi-one-dimensional material array comprises a semiconductor carbon nanotube array, a graphene nanoribbon array and the like.

At least a portion of the first gate dielectric layer 150 is formed on a portion of the channel layer 140, and at least a portion of the first gate dielectric layer 150 is formed on a portion of the transition region 130; that is, the projection of the first gate dielectric layer 150 on the plane where the heat sink layer 120 and the channel layer 140 are located should cover at least a portion of the channel layer 140 (the energy band of the channel material is adjusted to realize the switching of the transistor) and a portion of the transition region 130 (to realize Klein tunneling). In the present disclosure, the first gate dielectric layer 150 may be formed in a bottom gate, a local bottom gate, a gate-all-around, a top gate, or the like.

Accordingly, when the heat sink layer 120 has a bandgap, the heat sink layer 120 cannot be covered by the gate dielectric layer, otherwise, the on-state occurs, and carriers tunnel through the forbidden band of the heat sink material having a bandgap, and the tunneling coefficient is smaller than Klein tunneling coefficient, resulting in a decrease in the on-state current.

In the present disclosure, the first gate electrode 160 is disposed on the first gate dielectric layer 150; the projection of the first gate electrode 160 on the plane where the cold source layer 120 and the channel layer 140 are located covers at least the channel layer 140 and a portion of the transition region 130, so as to enable band modulation on the channel layer 140 to realize switching of the cold source transistor device 100 and Klein tunneling among the cold source layer 120, the transition region 130 and the channel layer 140.

Specifically, the first gate dielectric layer 150 covers at least a portion of a sidewall of the second electrode 180 and/or at least a portion of an upper surface of the second electrode 180, and the first gate dielectric layer 150 extends across both ends of the channel layer 140 in a width direction of the heat sink layer 120 and the channel layer 140 such that the width of the first gate dielectric layer 150 is greater than the widths of the channel layer 140 and the heat sink layer 120.

On the other hand, as shown in fig. 3 and 4, when the cold source layer 120 does not have a band gap, the cold source layer 120 needs to be gated when the band gap needs to be opened by an electric field.

Specifically, as shown in fig. 3 and 4, the cold source transistor device further includes a second gate dielectric layer 190 and a second gate electrode 200, wherein at least a portion of the second gate dielectric layer 190 is formed on a portion of the cold source layer 120; the second gate electrode 200 is disposed on the second gate dielectric layer 190; wherein an electric field perpendicular or substantially perpendicular to the cold source layer 120 is applied to the cold source layer 120 by controlling the second gate electrode 200; thereby, when a voltage is applied to the second gate electrode 200, the band gap of the cold source layer 120 can be opened.

Thus, the cold source transistor device of the present disclosure uses the first gate electrode 160 to regulate the channel layer 140 and the portion of the transition region 130 adjacent to the channel layer 140, to obtain a sub-threshold swing (SS) that breaks the theoretical limit (60 mV/dec at room temperature), and is an ultra-low power transistor.

Compared with a traditional Dirac source transistor, the cold source transistor device disclosed by the invention has the advantages that the band gap is introduced into double-layer graphene or doped single-layer graphene, so that the SS and the working voltage are theoretically smaller; meanwhile, as the transition region assists Klein tunneling (or other tunneling mechanism with a tunneling coefficient of about 1), the on-state current of the transistor is theoretically equivalent to that of a Dirac source transistor and has a high I60. The semiconductor device is expected to become a basic device of a future high-energy-efficiency (high-performance and ultra-low-power consumption) integrated circuit.

Referring to fig. 1 and 2, the heat sink transistor device 100 of the present disclosure further includes a first electrode 170 and a second electrode 180, according to an embodiment of the present disclosure.

The first electrode 170 is partially disposed on the substrate layer 110, and a portion of the first electrode 170 is disposed on the cold source layer 120, so that the first electrode 170 and the cold source layer 120 can conduct electricity. More preferably, one end of the cold source layer 120 in the length direction is connected to the transition region 130, and the first electrode 170 is disposed at the other end of the cold source layer 120 in the length direction.

More preferably, both ends of the first electrode 170 extend beyond both ends of the cold source layer 120 in the width direction of the cold source layer 120, whereby the first electrode 170 can play a role of fixing the cold source layer 120.

A portion of the second electrode 180 is disposed on the substrate layer 110, and a portion of the second electrode 180 is disposed on the channel layer 140, so that the second electrode 180 and the channel layer 140 can conduct electricity. More preferably, one end of the channel layer 140 in the length direction is connected to the transition region 130, and the second electrode 180 is disposed at the other end of the channel layer 140 in the length direction.

More preferably, both ends of the second electrode 180 extend beyond both ends of the channel layer 140 in the width direction of the channel layer 140, whereby the second electrode 180 can function to fix the channel layer 140.

Preferably, there is a predetermined interval between the first electrode 170 and the second electrode 180 such that most regions of the cold source layer 120, the transition region 130, and most regions of the channel layer 140 are located at a region between the first electrode 170 and the second electrode 180.

Preferably, the electrode material of the first electrode 170 and/or the second electrode 180 should be selected from metals with different work functions in case that the two-dimensional heat sink material with different doping is used for the heat sink layer 120 and the channel layer 140. Specifically, when the cold source transistor device is an NMOS, a P-type doped graphene is used, and a low work function metal such as Sc, Y, al, or Ni is used to fabricate a first electrode and a second electrode; accordingly, when the heat sink transistor device is a PMOS, N-type doped graphene is used, and a high work function metal such as Pd, au, or Pt is used to fabricate the first and second electrodes.

In a preferred embodiment, the cold source layer 120 and the channel layer 140 have the same or substantially the same width; more preferably, a connection line direction of the cold source layer 120 and the channel layer 140 is a length direction of the cold source layer 120 and the channel layer 140, wherein the cold source layer 120 and the channel layer 140 have the same length or substantially the same length.

The first gate dielectric layer 150 extends across both ends of the channel layer 140 in the width direction of the cold source layer 120 and the channel layer 140, and makes the width of the first gate dielectric layer 150 greater than the width of the channel layer 140 and the cold source layer 120.

Regarding the second gate dielectric layer 190, it is formed to extend to the edge of the transition region 130, and does not cover the transition region 130; that is, the first gate dielectric layer 150 and the second gate dielectric layer 190 have a certain gap and are spaced apart from each other, and the transition region 130 is located below the gap region. Moreover, the second gate dielectric layer 190 may also be formed on the side surface and the upper surface of the first electrode 170, which will not be described in detail herein.

In the present disclosure, the first electrode 170 may be formed as a source terminal electrode (source) of the heat sink transistor device 100, and the second electrode 180 may be formed as a drain terminal electrode (drain) of the heat sink transistor device 100.

Fig. 5 is a schematic diagram of a structure-energy band correspondence for a heat sink transistor device, according to one embodiment of the present disclosure. Fig. 6 is a sub-threshold region energy band schematic of a heat sink transistor device according to one embodiment of the present disclosure. Fig. 7 is a schematic on-band diagram of a cold source transistor device, according to one embodiment of the present disclosure. Fig. 8 is a graph comparing transfer characteristics of a heat sink transistor device and a conventional transistor according to one embodiment of the present disclosure.

The working principle of the transistor device with a double-layer graphene cold source is described below by taking an NMOS based on the cold source as an example. As shown in fig. 5 to 7, when the voltage Vds of the drain with respect to the source is greater than 0V, the electric field strength is directed from the drain to the source; when the voltage Vgs of the gate relative to the source is increased forward to a value near the fermi level of the source of the double-layer graphene so that electrons can pass through the semiconductor channel without being blocked by a barrier, this corresponds to the on-state of the transistor.

If the gate voltage Vgs is gradually decreased from the on-state gate voltage in the negative direction, the valence band and the conduction band of the semiconductor channel in the energy band diagram are gradually raised relative to the Fermi level, so that part of electrons near the Fermi level of the double-layer graphene source need to cross a potential barrier to be able to enter the conduction band of the channel material to pass through the channel. In the NMOS, the electron state density of the valence band part of the double-layer graphene source is reduced along with the rise of energy, the attenuation speed of the electron number distribution in the double-layer graphene source along with the rise of energy is faster than the attenuation speed of an E exponential function, so that in a subthreshold region, the gate voltage is reduced by 60mV every time, the potential barrier is raised by 60meV (ideally), the electron number attenuation of a channel can exceed one magnitude, the source-drain current attenuation exceeds one magnitude, and the transistor is rapidly turned off.

Therefore, as shown in fig. 8, the transistor based on the double-layer graphene cold source can realize SS <60mV/dec at room temperature, and the working voltage is less than the limit of 0.64V of the traditional silicon-based transistor. In particular, a bi-layer graphene cold source transistor has a smaller SS than a dirac source transistor, and the SS does not increase again to more than 60mV/dec in the subthreshold region, since there is a band gap in the cold source, there is no electron distribution in its forbidden band, and the electron density drops sharply to 0 at the top of the valence band of bi-layer graphene.

Fig. 9 and 10 are process flow diagrams of the fabrication of a heat sink transistor device according to various embodiments of the present disclosure.

According to an embodiment of the present disclosure, as shown in fig. 9, a method S100 for manufacturing a heat sink transistor device of the present disclosure includes the steps of:

s101, preparing a base layer 110;

s102, manufacturing a cold source layer 120 and a transition region 130 on a substrate layer 110 through multiple exposure, a phase shift mask technology and the like, wherein the cold source layer 120 is formed into double-layer graphene regulated by a vertical electric field, and the transition region is formed into the double-layer graphene; the channel layer is formed as a double-layer graphene nanoribbon.

S103, forming a channel layer 140 on the base layer 110; when the channel layer 140 is formed by the graphene nanoribbon, the channel layer 140 can be formed simultaneously with the cold source layer 120 and the transition region 130;

s104, depositing a first electrode 170 on the base layer 110 and the cold source layer 120, and depositing a second electrode 180 on the base layer 110 and the channel layer 140;

s105, forming a first gate dielectric layer 150 on the part of the substrate layer 110, the part of the channel layer 140 and the part of the transition region 130;

and S106, growing a gate metal on the first gate dielectric layer 150 to form a first gate electrode 160.

On the other hand, as shown in fig. 10, when the heat sink layer 120 is a double-layer graphene controlled by a vertical electric field, the method for manufacturing the heat sink transistor device further includes:

s107, forming a second gate dielectric layer 190 on the part of the substrate layer 110 and the part of the cold source layer 120;

and S108, growing a gate metal on the second gate dielectric layer 190 to form a second gate electrode 200.

In the description of the present specification, reference to the description of "one embodiment/mode", "some embodiments/modes", "example", "specific example", or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment/mode or example is included in at least one embodiment/mode or example of the present application. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment/mode or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments/modes or examples. Furthermore, the various embodiments/modes or examples and features of the various embodiments/modes or examples described in this specification can be combined and combined by one skilled in the art without being mutually inconsistent.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

It will be understood by those skilled in the art that the foregoing embodiments are provided merely for clarity of explanation and are not intended to limit the scope of the disclosure. Other variations or modifications may be made to those skilled in the art, based on the above disclosure, and still be within the scope of the present disclosure.

Claims (10)

1. A heat sink transistor device, comprising:

a base layer, a first substrate layer,

the cold source layer is arranged on the base layer; wherein the cold source layer is prepared by a cold source material capable of opening a band gap;

the transition region is arranged on the substrate layer and is connected with the cold source layer;

the channel layer is arranged on the substrate layer and is connected with the transition region;

at least part of the first gate dielectric layer is formed on the part of the channel layer, and at least part of the first gate dielectric layer is formed on the part of the transition region; and

and the first gate electrode is arranged on the first gate dielectric layer.

2. The heat sink transistor device of claim 1, wherein the cold source layer is fabricated from a bi-layer graphene material.

3. The heat sink transistor device of claim 2, further comprising:

the second gate dielectric layer, at least part of the said second gate dielectric layer is formed in part of the said cold source layer; and

the second gate electrode is arranged on the second gate dielectric layer; wherein an electric field perpendicular or substantially perpendicular to the heat sink layer is applied to the heat sink layer by controlling the second gate electrode.

4. The heat sink transistor device of claim 1, wherein the transition region is fabricated from single layer graphene or double layer graphene without electric field regulation.

5. The cold source transistor device of claim 1, further comprising:

a first electrode, a part of which is arranged on the substrate layer, and a part of which is arranged on the cold source layer, and enables electricity to be conducted between the first electrode and the cold source layer; and

a second electrode, a portion of which is disposed on the base layer and a portion of which is disposed on the channel layer, and which enables electrical conduction between the second electrode and the channel layer.

6. The heat sink transistor device of claim 5, wherein the first electrode and the second electrode have a predetermined spacing therebetween, wherein a majority of the area of the cold source layer and a majority of the area of the strip layer are located in an area between the first electrode and the second electrode.

7. The heat sink transistor device of claim 5, wherein the first electrode is spaced from the first gate dielectric layer by a predetermined distance.

8. The heat sink transistor device of any of claims 1-7, wherein the first gate dielectric layer covers at least a portion of a sidewall of the second electrode and/or covers at least a portion of an upper surface of the second electrode;

optionally, a connection line direction of the cold source layer and the channel layer is a length direction of the cold source layer and the channel layer;

optionally, the first gate dielectric layer extends across two ends of the channel layer along the width direction of the cold source layer and the channel layer, and the width of the first gate dielectric layer is larger than the width of the channel layer and the cold source layer;

optionally, the channel layer is prepared by a two-dimensional semiconductor material or a quasi-one-dimensional material array.

9. A method of fabricating a cold source transistor device capable of fabricating the cold source transistor device of claims 1-8, the method comprising:

s101, preparing a basal layer;

s102, manufacturing a cold source layer and a transition region on the substrate layer through multiple exposure and phase shift mask technology;

s103, forming a channel layer on the substrate layer;

s104, depositing a first electrode on the substrate layer and the cold source layer, and depositing a second electrode on the substrate layer and the channel layer;

s105, forming a first gate dielectric layer on the part of the substrate layer, the part of the channel layer and the part of the transition region;

and S106, growing gate metal on the first gate dielectric layer to form a first gate electrode.

10. The method of claim 9, wherein the cold source layer is formed as electric field-controlled double-layer graphene, the transition region is formed as double-layer graphene, and the channel layer is formed as a double-layer graphene nanoribbon;

optionally, when the cold source layer, the transition region and the channel layer are all formed by double-layer graphene, the cold source layer, the transition region and the channel layer are simultaneously formed by multiple exposure and phase-shift mask technology;

optionally, when the cold source layer is double-layer graphene, the preparation method further includes:

s107, forming a second gate dielectric layer on the base layer part and the cold source layer part; and

and S108, growing gate metal on the second gate dielectric layer to form a second gate electrode.

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