CN115411099A - Preparation method of pure platinum gold barrier Schottky diode - Google Patents
Preparation method of pure platinum gold barrier Schottky diode Download PDFInfo
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- 230000004888 barrier function Effects 0.000 title claims abstract description 50
- JUWSSMXCCAMYGX-UHFFFAOYSA-N gold platinum Chemical compound [Pt].[Au] JUWSSMXCCAMYGX-UHFFFAOYSA-N 0.000 title claims abstract description 11
- 238000002360 preparation method Methods 0.000 title claims description 7
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims abstract description 80
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 67
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 67
- 239000010703 silicon Substances 0.000 claims abstract description 67
- 238000000034 method Methods 0.000 claims abstract description 43
- 229910052697 platinum Inorganic materials 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 22
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims abstract description 18
- 238000000151 deposition Methods 0.000 claims abstract description 16
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052750 molybdenum Inorganic materials 0.000 claims abstract description 15
- 239000011733 molybdenum Substances 0.000 claims abstract description 15
- 230000003647 oxidation Effects 0.000 claims abstract description 14
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 14
- 229910052786 argon Inorganic materials 0.000 claims abstract description 13
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 10
- -1 argon ions Chemical class 0.000 claims abstract description 8
- 238000001259 photo etching Methods 0.000 claims abstract description 8
- 238000002161 passivation Methods 0.000 claims abstract description 7
- 230000007547 defect Effects 0.000 claims abstract description 6
- 238000005468 ion implantation Methods 0.000 claims abstract description 4
- 238000009740 moulding (composite fabrication) Methods 0.000 claims abstract description 4
- 229910052751 metal Inorganic materials 0.000 claims description 35
- 239000002184 metal Substances 0.000 claims description 35
- 238000004544 sputter deposition Methods 0.000 claims description 12
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 claims description 9
- 239000010936 titanium Substances 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 229910001080 W alloy Inorganic materials 0.000 claims description 2
- 230000000903 blocking effect Effects 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 claims description 2
- 238000005036 potential barrier Methods 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 71
- 235000012431 wafers Nutrition 0.000 description 38
- 238000004519 manufacturing process Methods 0.000 description 10
- 238000005245 sintering Methods 0.000 description 8
- 238000000137 annealing Methods 0.000 description 7
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 238000004140 cleaning Methods 0.000 description 5
- 230000007797 corrosion Effects 0.000 description 5
- 238000005260 corrosion Methods 0.000 description 5
- 239000000047 product Substances 0.000 description 5
- 239000011265 semifinished product Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 229910021339 platinum silicide Inorganic materials 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910010038 TiAl Inorganic materials 0.000 description 1
- XRZCZVQJHOCRCR-UHFFFAOYSA-N [Si].[Pt] Chemical compound [Si].[Pt] XRZCZVQJHOCRCR-UHFFFAOYSA-N 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000011031 large-scale manufacturing process Methods 0.000 description 1
- 238000011068 loading method Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 238000000717 platinum sputter deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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Abstract
A method for preparing a pure platinum-gold barrier Schottky diode comprises the steps of firstly depositing a layer of platinum metal on a molybdenum big disc, then placing a silicon wafer on the molybdenum big disc, bombarding the surface of the silicon wafer through high-purity argon ions, removing a natural oxidation layer on the surface of the silicon wafer, bombarding the big disc outside the silicon wafer through the argon ions, and depositing the platinum metal on the big disc on the surface of the silicon wafer after bombarding; and depositing a TiW layer on the surface of the platinum layer of the silicon wafer. Preparing a pure platinum gold barrier Schottky diode after depositing a TiW layer silicon wafer, wherein a substrate is an n + monocrystalline silicon substrate; generating an n-epitaxial layer on the n + monocrystalline silicon substrate; forming PN junction by regional oxidation and ion implantation, and forming a passivation layer by field oxidation; photoetching and corroding to expose the epitaxial layer of Si; and (3) preparing the silicon wafer with the Schottky barrier front surface cleaned to ensure that the surface of the silicon wafer is sufficiently clean and the exposed surface has no process defects.
Description
Technical Field
The invention relates to the field of semiconductor chips, in particular to a process method of a pure platinum barrier of a Schottky diode.
Background
Schottky diodes are widely used in power management due to their relatively low turn-on voltage (low forward voltage drop) and relatively fast switching time, and are commonly found in switching power supplies and high frequency applications. Typical schottky diodes typically employ either a low barrier height metal (e.g., titanium (Ti), nickel (Ni), chromium (Cr), etc.) or a high barrier height metal (e.g., platinum (Pt), etc.) to form a contact on N-type silicon. In many applications, low barrier height metal schottky diodes have a lower forward voltage drop and a greater reverse leakage current than high barrier height metal schottky diodes. In some applications, however, it is desirable for the schottky diode to maintain the low forward voltage drop characteristics of schottky while having relatively low reverse leakage current. The rectifying performance (forward voltage drop and reverse leakage) of the schottky diode is mainly determined by schottky barrier metal, when the metal is in close contact with silicon, a barrier is formed, the barrier height is phi B, and different phi B generate different rectifying characteristics. The higher the value of Φ B, the lower the reverse leakage current. For applications with low reverse leakage current, barrier metal materials with high Φ B need to be used. Φ B of platinum barrier: 0.80-0.90eV, which is the highest Φ B material among metal materials, and is also widely used in semiconductor fabrication. How to form a good platinum silicide barrier is the subject of the main study herein. In general, schottky barriers formed from noble metals such as titanium, platinum, and palladium have stability and repeatability.
The west ampere microelectronic technology institute 202110287682.9 discloses a schottky diode of NiPt15 alloy and a preparation method thereof, wherein the preparation method comprises the steps of sequentially preparing an epitaxial layer, a P + ring, a schottky barrier layer, an aluminum alloy layer and an anode conducting layer on a substrate, and preparing a cathode conducting layer on the lower surface of the substrate, and the preparation method uses LPCVD equipment to complete the NiPt15 alloy, so that higher vacuum degree can be obtained, the gas pressure in the alloy process is controllable, and the alloy process is effectively optimized. Because the NiPt15 alloy is adopted to permeate into the epitaxial layer of the first conduction type to form the Schottky barrier layer, the generated metal silicide comprises nickel silicon and platinum silicon components to form good Schottky contact, and the addition of the platinum metal can improve the thermal stability of the nickel silicon film.
The traditional platinum barrier process is that a layer of platinum is deposited on the surface of N <111> silicon, then platinum silicide is formed by sintering (annealing) of a furnace tube, the reaction rate of the platinum and the silicon is high, the temperature and the time of sintering (annealing) are tightly controlled, the uniformity in a chip or in a batch is easy to occur, the phenomenon of poor process repeatability is caused, the main defect is that reverse leakage of a Schottky product is large, and the deviation of leakage is large. By adopting the process researched by the invention, a process method capable of realizing repeated production is found for manufacturing the Schottky diode.
Disclosure of Invention
Aiming at the problems in the prior art, the invention aims to provide a pure platinum barrier process of a Schottky diode to realize process repeatability, and the process is suitable for a wider furnace tube sintering (annealing) process. The reverse leakage rate of the product is reduced, and the stability is good.
The purpose of the invention is realized by the following technical scheme, the preparation method of the pure platinum barrier Schottky diode comprises the steps of firstly depositing a layer of platinum metal on a molybdenum big disc, then placing a silicon wafer on the molybdenum big disc, bombarding the surface of the silicon wafer (semi-finished product) by high-purity argon ions, removing a natural oxidation layer on the surface of the silicon wafer, bombarding the big disc outside the silicon wafer by the argon ions, and depositing the platinum metal on the big disc on the surface of the silicon wafer after bombarding, wherein the method can form a very thin platinum layer with good uniformity on the surface of the silicon wafer; then depositing a TiW layer on the surface of the platinum layer of the (semi-finished product) silicon wafer; a platinum layer may be deposited on the TiW layer which provides a good starting point for the next run. The TiW layer is used for blocking the diffusion of the front metal to the barrier layer and protecting the characteristic of the Schottky barrier.
Wherein the sputtering process uses the following main materials: the weight ratio of tungsten to titanium in the titanium-tungsten alloy target is 9. The purity of the platinum target metal is 99.99 percent, the purity of the argon is 99.999 percent, and the platinum target metal and the argon are high-purity materials.
Bombarding the platinum metal on the large disc and depositing the platinum metal on the large disc to the surface of the silicon wafer below 10 nm; sputtering a layer of barrier protection layer TiW20nm, and then sputtering a layer of platinum 20-60nm. The (semi-finished product) silicon chip is prepared in the following way, and the substrate chip can be an n + monocrystalline silicon substrate; producing an n-epitaxial layer by using an n + monocrystalline silicon substrate; forming PN junction by local oxidation and ion implantation, and forming a passivation layer by field oxidation; photoetching and corroding the epitaxial layer (namely the Schottky hole region) with exposed Si; cleaning the surface of the silicon wafer before the Schottky barrier to ensure that the surface of the silicon wafer is clean enough and the exposed surface of the silicon wafer (semi-finished product) without process defects is exposed;
after depositing a TiW layer silicon wafer, preparing a pure platinum gold barrier Schottky diode, wherein the substrate can be an n + monocrystalline silicon substrate; producing an n-epitaxial layer by using an n + monocrystalline silicon substrate; forming PN junction by regional oxidation and ion implantation, and forming a passivation layer by field oxidation; photoetching and corroding to expose the epitaxial layer of Si; and (3) preparing the silicon wafer with the Schottky barrier front surface cleaned to ensure that the surface of the silicon wafer is sufficiently clean and the exposed surface has no process defects.
The prepared device comprises an n + substrate layer 1, an n-epitaxial layer 2, a pn junction 3, an oxidation layer 4, a Schottky barrier layer 5, a titanium-tungsten layer 6, a front metal 7 and a back metal 8, wherein the front metal 7, the titanium-tungsten layer 6, the Schottky barrier layer 5, the n-epitaxial layer 2, the n + substrate layer 1 and the back metal 8 are sequentially arranged from top to bottom in a chip screenshot manner, and the oxidation layer 4 and the front metal 7 are sequentially arranged from right to left in the chip screenshot manner. The schottky barrier layer 5 is a conventional schottky junction.
Compared with the prior art, the invention has the advantages that:
(1) The chip is simple in structure, is divided into three layers from right to left, is easy to manufacture, and is good in adaptability and high in compatibility;
(2) The most important thing is the formation of the barrier throughout the schottky fabrication process. Since schottky diodes are a surface effect device, cleaning of the silicon surface is critical. Any residual photoresist and other contaminants can seriously affect the formation of the schottky barrier. Special care must be taken to ensure the cleanliness of the silicon surface. Prior to deposition, the wafer is subjected to a reverse sputter clean of argon + to remove any residual oxide that may affect silicide formation. The repetitive production is realized, and the uniformity among batches is ensured;
(3) The platinum barrier is manufactured by a (magnetron) sputtering process, the thickness is more than 60nm, special manufacturing process and equipment are not required to be introduced, and the manufacturability of products and the compatibility of the process are improved.
(4) 8 pieces can be operated in one sputtering process, and a platinum sputtering layer provides a good starting point for the next operation in the sputtering process, so that the cost is reduced;
(5) The sintering (annealing) window of the furnace tube is wider than 400-500C, the time is 20-60min, the process adaptability is strong, and the repeated production is easy to realize.
Drawings
FIG. 1 is a schematic cross-sectional view of a Schottky barrier diode of the present invention;
FIG. 2 is a schematic diagram of the molybdenum platter 13 (deposited on the molybdenum platter after bombardment with platinum metal) and the silicon wafer fabrication of the present invention;
figure 3 is a graph of the profile of the process of the present invention compared to the prior art (parameter comparison of the finished product).
Detailed Description
The invention is described in detail below with reference to the drawings and specific examples.
In fig. 1, the device comprises an n + substrate layer 1, an n-epitaxial layer 2, a pn junction 3, a passivation layer 4, a schottky barrier layer 5, a titanium tungsten layer 6, a front metal 7 and a back metal 8, wherein the front metal 7, the titanium tungsten layer 6, the schottky barrier layer 5, the n-epitaxial layer 2, the n + substrate layer 1 and the back metal 8 are sequentially arranged from top to bottom, and the chip, the passivation layer 4 and the front metal 7 are sequentially arranged from right to left in the screenshot of the chip.
As shown in fig. 2, a molybdenum large plate 13 (deposited on the molybdenum large plate after being bombarded by platinum metal) is provided with a circular hole 11 for loading and unloading silicon wafers and a silicon wafer 12.
Firstly, depositing a layer of platinum metal on a molybdenum big disc, then placing a silicon wafer on the molybdenum big disc, bombarding the surface of the silicon wafer (semi-finished product) by high-purity argon ions, removing a natural oxidation layer on the surface of the silicon wafer, simultaneously bombarding the big disc outside the silicon wafer by the argon ions, and depositing the platinum metal on the molybdenum big disc on the surface of the silicon wafer after bombarding the platinum metal, wherein the method can form a very thin platinum layer with good uniformity on the surface of the silicon wafer; depositing a TiW layer on the surface of the platinum layer of the (semi-finished) silicon wafer; a platinum layer may be deposited over the TiW layer.
The development and manufacture of the Schottky diode by the platinum barrier process comprises the following steps:
1. substrate slice: the resistivity of the n + monocrystalline silicon substrate 1, n + substrate is < =0.005ohm-cm, and the thickness is 300-625um.
2. And (3) epitaxial wafer: producing an n-epitaxial layer 2 in an n + monocrystalline silicon substrate area, wherein the thickness of the n-epitaxial layer is 2-30 mu m, and the resistivity of the n-epitaxial layer is 0.3-30.0 ohm.cm;
3. oxidizing, ion implanting to form PN junction 3, field oxidizing to form passivation layer 4
4. Photoetching and corroding the epitaxial layer (namely the Schottky hole region) with exposed Si;
5. surface cleaning before Schottky barrier: cleaning the surface of the silicon wafer processed in the previous step by using the cleaning solution of No. 1, no. 2 and HF commonly used in the industry, so as to ensure that the surface of the silicon wafer is sufficiently clean and the silicon without process defects on the surface is exposed;
6. schottky barrier formation: and depositing a layer of platinum film with the thickness of 50nm on the molybdenum large disc by a magnetron sputtering instrument. Then, the silicon wafer processed in step 5 is loaded on a molybdenum large plate with a platinum film (50 nm) deposited on the surface, and as shown in fig. 2, the silicon wafer is cleaned by argon + reverse sputtering under high vacuum so as to remove the natural oxide layer on the silicon surface and simultaneously sputter the platinum layer on the large plate onto the silicon wafer to form a very thin platinum film with the thickness of 5nm, and then a barrier protective layer TiW (20 nm) is sputtered, and a platinum layer (50 nm) is sputtered, so that the schottky barrier layer 5 is formed.
7. Metal photoetching, corrosion and photoresist removal: firstly, metal photoetching is carried out, then, metals of aqua regia and H2O2 are used for respectively corroding platinum and TiW, and the photoresist is removed after the corrosion is finished.
8. Sintering and alloying: putting the silicon wafer after the step 7 into a furnace tube for sintering to form metal silicide, wherein the sintering temperature is 400-500 ℃, the sintering time is 20-60mins, and the gas is N2;
9. sputtering titanium tungsten: sputtering the silicon wafer processed in the step 12 with a magnetron sputtering instrument to form a titanium-tungsten layer with the thickness of 0.1-0.3 um for protecting the metal silicide at the bottom to form a titanium-tungsten layer 6;
10. metallization: according to different requirements, different front metals such as TiAl or TiNiAg and the like can be evaporated, and through metal photoetching and metal corrosion, photoresist is removed to form a front metal 7;
11. annealing: placing the silicon wafer processed in the step 10 into an annealing furnace tube for eliminating stress among all layers of metal, wherein the temperature of the annealing furnace tube is 400-500 ℃, the time is more than 20min, and N2, N2/H2 or vacuum can be used;
12. back thinning: carrying out chemical mechanical polishing on the silicon wafer obtained by the step 11, thinning the thickness of the silicon wafer from the back to 260 microns, carrying out back silicon corrosion, releasing the mechanical capability of the thinning process, removing a silicon damage layer on the surface, and adopting back thinning and silicon corrosion processes to reduce the forward on-resistance of the diode, improve the on-performance of the diode and improve the reliability of the diode;
13. evaporating back metal: and (4) performing electron beam evaporation on the back surface of the silicon wafer obtained by the treatment in the step (12), and depositing back metal on the silicon wafer to form back metal 8. The back is silver, a back electrode is formed, and the silver has good conductivity, so that the chip has better conductivity and lower power consumption; table 1 shows the comparison of the reverse leakage uniformity of the new process and the conventional process (taking 70mil/200V,25 degree test data as an example)
Figure 3 is a graph showing the distribution of the process of the present invention compared to the prior art (parameter comparison of the finished product, mainly leakage parameters). The new platinum process has small leakage deviation value, so that the stability of the new process is proved, the repeatability is good, and the method is more suitable for large-scale production.
The invention and its embodiments have been described above schematically, without limitation, and the embodiments shown in the drawings are only one of the embodiments of the invention, and the actual structure is not limited thereto. Therefore, if the person skilled in the art receives the teaching, without departing from the spirit of the present invention, the person skilled in the art shall not inventively design the similar structural modes and embodiments to the technical solution, but shall fall within the protection scope of the present invention.
Claims (5)
1. A preparation method of a pure platinum gold potential barrier Schottky diode is characterized in that a layer of platinum metal is deposited on a molybdenum big disc at first, then a silicon wafer is placed on the molybdenum big disc, the surface of the silicon wafer is bombarded by high-purity argon ions, a natural oxidation layer on the surface of the silicon wafer is removed, meanwhile, the argon ions bombard the big disc outside the silicon wafer, and the platinum metal on the big disc is bombarded and then deposited on the surface of the silicon wafer; and depositing a TiW layer on the surface of the silicon wafer platinum layer.
2. The method for preparing a pure platinum gold barrier schottky diode according to claim 1, wherein a platinum layer is deposited on the TiW layer; the TiW layer is used for blocking diffusion of the front metal to the barrier layer and protecting the Schottky barrier.
3. The method for preparing a pure platinum gold barrier schottky diode according to claim 1, wherein the sputtering process uses the following main materials: the weight ratio of tungsten to titanium in the titanium-tungsten alloy target is 9. The purity of the platinum target metal was 99.99%, and the purity of argon was 99.999%.
4. The method for preparing pure platinum gold barrier Schottky diode according to one of claims 1 to 3, wherein the platinum metal on the large disc is bombarded and deposited on the surface of the silicon wafer below 10 nm; sputtering a layer of barrier protection layer TiW20nm, and then sputtering a layer of platinum 20-60nm.
5. The method for preparing a pure platinum gold barrier Schottky diode according to any one of claims 1 to 4, wherein the pure platinum gold barrier Schottky diode is prepared after a TiW layer silicon wafer is deposited, and an n + monocrystalline silicon substrate is selected as a substrate; generating an n-epitaxial layer on the n + monocrystalline silicon substrate; forming PN junction by regional oxidation and ion implantation, and forming a passivation layer by field oxidation; photoetching and corroding to expose the epitaxial layer of Si; and (3) preparing the silicon wafer with the Schottky barrier front surface cleaned to ensure that the surface of the silicon wafer is sufficiently clean and the exposed surface has no process defects.
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| CN202211189058.6A Active CN115411099B (en) | 2022-09-28 | 2022-09-28 | Preparation method of pure platinum barrier Schottky diode |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4119446A (en) * | 1977-08-11 | 1978-10-10 | Motorola Inc. | Method for forming a guarded Schottky barrier diode by ion-implantation |
| JPS6476756A (en) * | 1987-09-18 | 1989-03-22 | Nec Corp | Semiconductor integrated circuit device and manufacture thereof |
| US5139633A (en) * | 1990-08-08 | 1992-08-18 | Shin-Etsu Chemical Co., Ltd. | Film-forming on substrate by sputtering |
| JPH06132243A (en) * | 1992-10-16 | 1994-05-13 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| CN107785251A (en) * | 2016-08-26 | 2018-03-09 | 英飞凌科技股份有限公司 | Formed using the barrier layer of heat treatment |
-
2022
- 2022-09-28 CN CN202211189058.6A patent/CN115411099B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4119446A (en) * | 1977-08-11 | 1978-10-10 | Motorola Inc. | Method for forming a guarded Schottky barrier diode by ion-implantation |
| JPS6476756A (en) * | 1987-09-18 | 1989-03-22 | Nec Corp | Semiconductor integrated circuit device and manufacture thereof |
| US5139633A (en) * | 1990-08-08 | 1992-08-18 | Shin-Etsu Chemical Co., Ltd. | Film-forming on substrate by sputtering |
| JPH06132243A (en) * | 1992-10-16 | 1994-05-13 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| CN107785251A (en) * | 2016-08-26 | 2018-03-09 | 英飞凌科技股份有限公司 | Formed using the barrier layer of heat treatment |
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| Publication number | Publication date |
|---|---|
| CN115411099B (en) | 2024-07-02 |
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