CN115407227A - Sampling holding and knee point detection circuit with self-adaptive precharge capability - Google Patents

Sampling holding and knee point detection circuit with self-adaptive precharge capability Download PDF

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CN115407227A
CN115407227A CN202211041122.6A CN202211041122A CN115407227A CN 115407227 A CN115407227 A CN 115407227A CN 202211041122 A CN202211041122 A CN 202211041122A CN 115407227 A CN115407227 A CN 115407227A
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tube
voltage
nmos tube
drain electrode
pmos
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周泽坤
何金阳
林镇熙
王卓
张波
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University of Electronic Science and Technology of China
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University of Electronic Science and Technology of China
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/40—Testing power supplies
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16504—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the components employed
    • G01R19/16519—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the components employed using FET's
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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Abstract

The invention belongs to the technical field of power management, and particularly relates to a sample-hold and knee point detection circuit with self-adaptive pre-charging capability. The invention mainly designs and realizes a sample-hold and knee-point detection circuit with self-adaptive pre-charging capability, and in order to prevent the problem that the charging time of a sampling capacitor in a smaller turn-off time is not enough, the circuit is additionally provided with a transient enhancement circuit to pre-charge the sampling capacitor, and the pre-charge is carried out through a buffer and a C delay And R delay The voltage difference formed between the delayed voltage signal and the original signal makes the second comparator turn over, so as to sample the capacitor C in the blanking period of the leading edge delay Pre-charging is performed to reduce the sampling capacitance C delay The need for charging time. Compared with the traditional sampling hold and knee point detection circuit, the knee point voltage can be obtained more accurately.

Description

Sampling holding and knee point detection circuit with self-adaptive precharge capability
Technical Field
The invention belongs to the technical field of power management, and particularly relates to a sample-hold and knee point detection circuit with self-adaptive pre-charging capability.
Background
In recent years, with the development of electronic devices, the conventional linear voltage-stabilized power supply gradually fails to meet the demand of electronic products on power management chips, and the switching power supply gradually becomes the mainstream of the market. The flyback converter is generally used in a low-power device due to the advantages of small size, low power consumption, good input and output isolation characteristics and the like. The flyback converter can be divided into a primary side feedback type and a secondary side feedback type according to a feedback regulation mode. The output sampling of the secondary side feedback flyback converter is accurate, but the primary side feedback flyback converter with a simpler structure becomes a current hotspot because of the defect of poor anti-interference capability of elements such as an optical coupler and the like.
In the primary side feedback mode, output voltage information is obtained through the primary side of the flyback converter, the sampling accuracy determines the accuracy of the output voltage, and one of the key points of the design of the primary side feedback flyback converter is the design of a sample-hold and knee point detection circuit. When the secondary side inductive current is zero, namely at the knee point, the voltage drop generated by the parasitic impedance of the secondary side is not opposite to V SW Influence is produced, so V at this time SW The output voltage information can be described more accurately. As shown in fig. 1, this is a schematic diagram of a conventional sample-and-hold and knee point detection circuit, which utilizes the characteristic that the voltage waveform drops sharply when the feedback voltage reaches the knee point, and utilizes the comparison between the buffer delay and the original signal to obtain the knee point. However, in the conventional scheme, when the secondary side conduction time is short, the sampling circuit cannot be set to a steady-state working point, so that the sampling voltage is smaller than the real knee point voltage, and the accuracy of the output voltage is affected.
Disclosure of Invention
The invention mainly designs and realizes a self-adaptive pre-charging circuit which can be used for optimizing a sample-hold and knee-point detection circuit, in order to prevent the problem that the charging time of a sampling capacitor is not enough in a smaller turn-off time, the circuit is additionally provided with a transient enhancement circuit to pre-charge the sampling capacitor, and the sampling capacitor is subjected to buffer and C delay And R delay The voltage difference between the delayed voltage signal and the original signal is used to make the second comparator turn overLeading edge blanking period sampling capacitor C delay Pre-charging is performed to reduce the sampling capacitance C delay The need for charging time.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a sampling hold and knee point detection circuit with a self-adaptive pre-charging scheme is used for detecting knee point voltage of a primary side feedback flyback converter when secondary side inductance current is zero, and comprises a buffer, a first comparator, a second comparator, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a third NMOS tube, a first PMOS (P-channel metal oxide semiconductor) tube, a first resistor, a first capacitor, a second capacitor, a first voltage source, a second voltage source and a current source;
the in-phase input end of the buffer A1 is connected with the feedback voltage, the reverse-phase input end of the buffer A1 is connected with the output end of the buffer, the output end of the buffer is grounded after passing through the first resistor and the first capacitor in sequence, the enable signal of the buffer is defined as a first enable signal, and the buffer outputs a voltage V buf Defined as the buffer voltage, the voltage V at the other end of the first resistor delay Defined as the delay voltage;
the non-inverting input of the first comparator A2 is connected with the buffer voltage, and the inverting input thereof is connected with the first voltage source V OS1 The negative end of the voltage source is connected with a feedback voltage, an enabling signal of the first comparator is defined as a second enabling signal, an output voltage COMP _ knee is defined as a judgment voltage, and the first voltage source generates a fixed offset voltage;
the non-inverting input of the second comparator A3 is connected with the delay voltage, and the inverting input thereof is connected with the second voltage source V OS2 The negative end of the voltage source is connected with the feedback voltage, the enable signal of the second comparator is a second enable signal, the output voltage precharge is defined as a precharge voltage, and the second voltage source generates a fixed offset voltage;
the drain electrode of the first NMOS tube is connected with the delay voltage, and the grid electrode of the first NMOS tube is connected with a third enabling signal;
the source electrode and the drain electrode of the second NMOS tube are connected with the source electrode of the first NMOS tube, the grid electrode of the second NMOS tube is connected with a reverse signal of a third enabling signal, the connection point of the source electrode of the first NMOS tube and the source drain electrode of the second NMOS tube is grounded through a second capacitor, and the output voltage of the connection point of the source electrode of the first NMOS tube, the source drain electrode of the second NMOS tube and the second capacitor is defined as knee point voltage holding voltage;
the drain electrode of the third NMOS tube is connected with the connection point of the first resistor, the first capacitor and the drain electrode of the first NMOS tube, the grid electrode of the third NMOS tube is connected with the PWM pulse signal, and the source electrode of the third NMOS tube is grounded; when the primary side is conducted, the pulse signal is at a high level, the third NMOS tube is opened, and when the secondary side is conducted, the pulse signal is at a low level, and the third NMOS tube is closed;
the drain electrode of the first PMOS tube is connected with a connection point of the first resistor, the first capacitor and the drain electrode of the first NMOS tube, the grid electrode of the first PMOS tube is connected with a pre-charging voltage, the source electrode of the first PMOS tube is connected with the positive end of a current source, and the negative end of the current source is connected with a power supply rail.
When the secondary side is conducted and the feedback voltage rises, the first enabling signal controls the buffer to be started, the second enabling signal controls the first comparator and the second comparator to be switched off, the buffer voltage is enabled to always follow the feedback voltage, and therefore the voltage value of the first capacitor is updated; when the feedback voltage enters the plateau period, the second enabling signal controls the first comparator and the second comparator to be started, when the leading edge blanking time is within the leading edge blanking time, if the delay voltage is smaller than the feedback voltage, the second comparator is turned over, the first PMOS tube is turned on to charge the first capacitor, if the delay voltage is charged to the feedback voltage, the second comparator is turned over again, the first PMOS tube is controlled to be turned off, and the current source does not charge the first capacitor any more. When the knee point arrives, the first comparator is turned over, the voltage is judged to be turned over from a low potential to a high potential, the third enabling signal is correspondingly turned over, the first NMOS tube is opened for sampling, the charge of the first capacitor is shared by the second capacitor, and the first enabling signal controls the buffer to be turned off so that the delay voltage keeps the knee point voltage; after a narrow pulse time, the third enable signal is turned down, the first NMOS transistor is turned off, the second NMOS transistor is turned on, the second enable signal controls the first comparator to be turned off, and the first enable signal controls the buffer to be turned on.
Further, the buffer comprises a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, a twelfth NMOS transistor, a second resistor, a third resistor, and a fourth resistor; the first comparator comprises a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, an eleventh NMOS tube, a second resistor, a third resistor and a fourth resistor;
the source electrodes of the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube, the sixth PMOS tube and the seventh PMOS tube are all connected with a power supply; the grid and the drain of the second PMOS tube are interconnected, and the drain of the second PMOS tube is connected with a current source; the grid electrodes of the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube, the sixth PMOS tube and the seventh PMOS tube are all connected with the drain electrode of the second PMOS tube;
the source electrode of the eighth PMOS tube is connected with the drain electrode of the third PMOS tube, the grid electrode of the eighth PMOS tube is connected with feedback voltage after passing through a fourth resistor, and the drain electrode of the eighth PMOS tube is grounded after passing through a second resistor;
the source electrode of the ninth PMOS tube is connected with the drain electrode of the third PMOS tube, the grid electrode of the ninth PMOS tube is connected with the drain electrode of the fourth NMOS tube, and the drain electrode of the ninth PMOS tube is grounded after passing through the third resistor;
the drain electrode of the ninth NMOS tube is connected with the feedback voltage through a fourth resistor, the grid electrode of the ninth NMOS tube is interconnected with the source electrode of the ninth NMOS tube, and the source electrode of the ninth NMOS tube is grounded;
the grid electrode and the drain electrode of the eighth NMOS tube are connected with the drain electrode of the fourth PMOS tube, and the source electrode of the eighth NMOS tube is grounded through the second resistor; the drain electrode of the seventh NMOS tube is connected with the drain electrode of the fifth PMOS tube, the grid electrode of the seventh NMOS tube is connected with the drain electrode of the eighth NMOS tube, and the source electrode of the seventh NMOS tube is grounded through a third resistor;
the drain electrode of the sixth NMOS tube is connected with the drain electrode of the sixth PMOS tube, the grid electrode of the sixth NMOS tube is connected with the drain electrode of the seventh NMOS tube, and the source electrode of the sixth NMOS tube is grounded;
the drain electrode of the eleventh NMOS tube is connected with the drain electrode of the seventh PMOS tube, the grid electrode of the eleventh NMOS tube is connected with a second enabling signal, and the source electrode of the eleventh NMOS tube is grounded;
the connection point of the drain electrode of the sixth PMOS tube, the drain electrode of the sixth NMOS tube and the drain electrode of the eleventh NMOS tube is the output end of the first comparator;
the drain electrode of the fifth NMOS tube is connected with the power supply, and the grid electrode of the fifth NMOS tube is connected with the drain electrode of the seventh NMOS tube; the grid electrode and the drain electrode of the tenth NMOS tube are connected with the drain electrode of the seventh PMOS tube, and the source electrode of the tenth NMOS tube is grounded; the drain electrode of the fourth NMOS tube is connected with the source electrode of the fifth NMOS tube, the grid electrode of the fourth NMOS tube is connected with the drain electrode of the tenth NMOS tube, and the source electrode of the fourth NMOS tube is grounded;
the drain electrode of the twelfth NMOS tube is connected with the drain electrode of the seventh PMOS tube, the grid electrode of the twelfth NMOS tube is connected with the first enabling signal, and the source electrode of the twelfth NMOS tube is grounded;
the connection point of the source electrode of the fifth NMOS tube, the grid electrode of the ninth PMOS tube and the drain electrode of the fourth NMOS tube is the output end of the buffer;
the beneficial effects of the invention are as follows: compared with the traditional sampling hold and knee point detection circuit, the knee point voltage can be obtained more accurately.
Drawings
FIG. 1 is a block diagram of a sample-and-hold and knee-point detection scheme.
FIG. 2 is a block diagram of a sample-and-hold and knee point detection circuit with adaptive precharge capability according to the present invention.
FIG. 3 is a timing diagram illustrating the control of the sample-and-hold and knee point detection scheme with the adaptive pre-charge scheme proposed by the present invention.
FIG. 4 is a circuit diagram of a sample-and-hold and knee point detection circuit with adaptive precharge capability according to the present invention.
Detailed Description
The technical scheme of the invention is described in detail below with reference to the accompanying drawings:
a schematic diagram of sample-and-hold and knee point detection using the optimization scheme of the present invention is shown in fig. 1. In the secondary side conduction period, the signal V is enabled hold And V LEB Controlling the knee point detection process by first enabling signal V when the secondary side is just turned on hold Control buffer A1 to open and enable signal V LEB Control comparator to turn off, V RREF The signal is buffered to obtain V buf A signal; enabling the signal when the ringing of the feedback voltage disappears into the platform areaNumber V LEB Controlling the comparator to start to finish leading edge blanking, when the knee point arrives, the output of the comparator turns over, controlling the sampling switch to be opened, and turning on the capacitor C delay The charge on the buffer is shared on the Chold, the buffer is controlled to be switched off to keep the knee voltage, and after a narrow pulse time, the sampling switch is switched off, the enable signal controls the buffer to work, and the comparator is controlled to be switched off. This samples the knee voltage.
Under this scheme, C delay A VDD power supply rail passes through a buffer source follower and a resistor R on the capacitor delay Charging is carried out if the time of the secondary side conduction is short and C delay If the capacitance is large, V may occur due to insufficient charging time delay Voltage lower than V RREF Voltage, appearing as V shown in FIG. 2 delay The curve of' eventually leads to a reduction in the accuracy of the output voltage. The invention provides a circuit scheme of sample-hold and knee point detection with adaptive precharge capability, which is shown in figure 2. The scheme mainly comprises a sample-hold and knee point detection part and an adaptive pre-charging part. The sample-hold and knee point detection part mainly comprises: buffer A1, comparator A2, first order low pass filter resistor R delay And a capacitor C delay Holding capacitance C hold A sampling switch MN1, a virtual switch MN2 and a reset switch MN3; the adaptive precharge part includes: comparator A3, precharge switch MP1, current source.
The control sequence of the sample-and-hold and knee point detection scheme with the adaptive precharge scheme proposed by the present invention is shown in fig. 3. When the secondary side is conducted, the MN3 tube is switched off, and the reference voltage V is fed back RREF Rapidly rises, V buffer And V delay Will follow V RREF The voltage starts to rise. At t 0 -t 1 When the secondary side is just conducted, the parasitic capacitance of the power tube and the primary side inductance can form resonance, and V is used for avoiding false triggering of the comparator A2 in the period of time LEB Not enabled, A2 does not operate. To avoid V appearing in fig. 3 delay ' in the case, the pre-charge current I is allowed by using the A3 control MP1 transistor charge To C delay Charging when V delay Voltage distance V RREF When it is largerComparator A3 outputs precharge to be turned low; when V is delay Is charged to be close to V REFF When the comparator A3 is turned over, precharge is turned over, MP1 is turned off, and the precharge current is cut off. The introduction of the comparator A3 can make the turn-on time of the pre-charge current follow V REFF The voltage auto-adjustment of (2) can be applied not only to the application of fixed leading edge blanking time, but also to the application of variable leading edge blanking time. At t 1 -t 2 ，V RREF Entering a platform zone, V LEB The signal controls the comparator A2 to be opened, the A1 continues to work and updates the C delay The voltage value of (2). At t 2 At that time, the secondary side inductor current decreases to 0, the knee point arrives, V RREF Fast droop due to the influence of pull-down slew rate and buffer delay, V buffer Cannot follow in time, so that V buffer And V RREF When a voltage difference exists between the first and second voltage sources, the comparator A2 is turned over, the COMP _ knee signal is turned over from a low potential to a high potential, and V is SES Is turned to a high potential to enable the signal V hold When the voltage is turned to a high level, the buffer A1 is closed, and V buffer Holding knee voltage, sampling switch on, C delay And C hold Charge sharing begins. Reaches t after a narrow pulse time 3 Time of day, V SES Turning down, the sampling switch MN1 is disconnected, the virtual switch MN2 is opened, clock feed-through is compensated, and simultaneously V hold Falls, buffer A1 begins to operate normally. t is t 4 At the moment, when the primary side is conducted, the MN3 tube is opened to connect C delay The voltage on is reset.
A sample-and-hold and knee point detection circuit diagram with adaptive precharge capability is shown in fig. 4. The buffer and the comparator of the circuit multiplex a folding type cascode structure, so that an additional circuit is omitted, and the power consumption and the cost of the circuit are reduced. MP2, MP3, MP4, MP5, MP6 and MP7 form a current mirror to provide bias current for the circuit. MP8 and MP9 are input geminate transistors, R1 and R2 are load resistors, R3 is a current-limiting resistor, MN9 is a GGNMOS (general-purpose gate-N-channel metal oxide semiconductor) tube for electrostatic discharge, and MN7 and MN8 and MP9 form a folded cascode structure together; the MP6, the MN6, the enable tube MN11 and the folded cascode structure together form a comparator; MN10 and MN4 form a current mirrorMN5 is used as a source follower tube, and an enabling tube MN12 and a folding cascode structure form a buffer together; r is delay And C delay Form a first-order low-pass filter, a holding capacitor C hold The sampling switch MN1, the dummy switch MN2, and the reset switch MN3 constitute a sample-and-hold circuit. In the circuit with the structure, the input common mode range is ensured, meanwhile, the structure is ensured to have larger gain, the output precision of the buffer can be ensured by the larger gain of the buffer, and the accuracy of the sampling voltage is further ensured. Knee point detection needs to be at V RREF When falling rapidly, V buffer Can not follow V RREF The negative slew rate of the buffer needs to be small. And upon arrival at the knee point, C delay And C hold Charge sharing is performed according to the conservation of charge, when C delay The larger C hold The smaller, V sam The error from the knee voltage is small, so the capacitance ratio of the two capacitors needs to be ten times or more.
I charge Is a pre-charge current source, and MP1 is a pre-charge switch. The gate of MP1 is connected with signal enable signal precharge for controlling MP1 to be turned on in the leading edge blanking period, so that pair C delay A pre-charge is performed. When V is delay Close to V RREF When the precharge signal is inverted, the charging is ended, and the offset comparator A3 ensures that V is not set delay And (5) point overcharging. If the LEB time is not yet charged to the plateau voltage, the charging is also ended.
An adaptive precharge circuit that may be used to optimize the sample-and-hold and knee point detection circuits is described in detail below. In the circuit of FIG. 2, V RREF When in the plateau region, C delay Can be expressed as
Figure BDA0003821008060000061
When the secondary side is just turned on, V buf Following V RREF Rises rapidly and V delay The initial potential of (2) is zero and the charging current is large. With V buf And V delay Becomes small in voltage difference and charging currentThe smaller. And R is delay Is also limited by stability and delay compensation, and therefore cannot be compensated for by reducing R delay To increase the charging current. Therefore, when the secondary side has a short on-time, a V-pass occurs delay The resulting sampled voltage is lower than the true knee voltage, and therefore an adaptive precharge circuit is added to the circuit of fig. 4.
Assuming that the charging time from the secondary side conduction to the charging is t, when V delay Can be charged to V in the leading edge blanking time RREF K times of (1), then C delay In which the stored charge is
Q C ＝kC delay V RREF (t)
During charging, a pre-charge current is supplied to C delay The electric charge provided is
Q C_pre ＝i charge t
Thus the precharge current is for C delay The charging speed is not following V buf May vary. Can make V delay To more nearly V RREF 。

Claims (2)

1. A sample-hold and knee point detection circuit with self-adaptive precharge capability is used for detecting knee point voltage of a primary side feedback flyback converter when secondary side inductive current is zero, and is characterized by comprising a buffer, a first comparator, a second comparator, a third comparator, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a third NMOS tube, a first PMOS (P-channel metal oxide semiconductor) tube, a first resistor, a first capacitor, a second capacitor, a first voltage source, a second voltage source and a current source;
the in-phase input end of the buffer is connected with the feedback voltage, the reverse-phase input end of the buffer is connected with the output end of the buffer, the output end of the buffer is grounded after passing through the first resistor and the first capacitor in sequence, the enable signal of the buffer is defined as a first enable signal, and the buffer outputs a voltage V buf Defined as the buffer voltage, the voltage V of the junction of the first resistor and the first capacitor delay Defined as the delay voltage;
the in-phase input end of the first comparator is connected with buffer voltage, the inverted input end of the first comparator is connected with the positive end of a first voltage source, the negative end of the voltage source is connected with feedback voltage, an enabling signal of the first comparator is defined as a second enabling signal, an output voltage COMP _ knee is defined as judgment voltage, and the first voltage source generates fixed offset voltage;
the non-inverting input end of the second comparator is connected with the delay voltage, the inverting input end of the second comparator is connected with the positive end of a second voltage source, the negative end of the voltage source is connected with the feedback voltage, the enable signal of the second comparator is a second enable signal, the output voltage precharge is defined as the precharge voltage, and the second voltage source generates the fixed offset voltage;
the drain electrode of the first NMOS tube is connected with the delay voltage, and the grid electrode of the first NMOS tube is connected with a third enabling signal;
the source electrode and the drain electrode of the second NMOS tube are connected with the source electrode of the first NMOS tube, the grid electrode of the second NMOS tube is connected with a reverse signal of a third enabling signal, the connection point of the source electrode of the first NMOS tube and the source drain electrode of the second NMOS tube is grounded through a second capacitor, and the output voltage of the connection point of the source electrode of the first NMOS tube, the source drain electrode of the second NMOS tube and the second capacitor is defined as knee point voltage holding voltage;
the drain electrode of the third NMOS tube is connected with the connection point of the first resistor, the first capacitor and the drain electrode of the first NMOS tube, the grid electrode of the third NMOS tube is connected with the PWM pulse signal, and the source electrode of the third NMOS tube is grounded; when the primary side is conducted, the pulse signal is at a high level, the third NMOS tube is opened, and when the secondary side is conducted, the pulse signal is at a low level, and the third NMOS tube is closed;
the drain electrode of the first PMOS tube is connected with a connection point of a first resistor, a first capacitor and the drain electrode of the first NMOS tube, the grid electrode of the first PMOS tube is connected with a pre-charging voltage, the source electrode of the first PMOS tube is connected with the positive end of a current source, and the negative end of the current source is connected with a power rail;
when the secondary side is conducted and the feedback voltage rises, the first enabling signal controls the buffer to be started, the second enabling signal controls the first comparator and the second comparator to be switched off, the buffer voltage is enabled to always follow the feedback voltage, and therefore the voltage value of the first capacitor is updated; when the feedback voltage enters the plateau period, the second enabling signal controls the first comparator and the second comparator to be started, when the leading edge blanking time is within the leading edge blanking time, if the delay voltage is smaller than the feedback voltage, the second comparator is turned over, the first PMOS tube is turned on to charge the first capacitor, if the delay voltage is charged to the feedback voltage, the second comparator is turned over again, the first PMOS tube is controlled to be turned off, and the current source does not charge the first capacitor any more; when the knee point arrives, the first comparator is turned over, the voltage is judged to be turned over from a low potential to a high potential, the third enabling signal is correspondingly turned over, the first NMOS tube is opened for sampling, the charge of the first capacitor is shared by the second capacitor, and the first enabling signal controls the buffer to be turned off so that the delay voltage keeps the knee point voltage; after a narrow pulse time, the third enabling signal is turned down, the first NMOS transistor is turned off, the second NMOS transistor is turned on, the second enabling signal controls the first comparator to be turned off, and the first enabling signal controls the buffer to be turned on.
2. The sample-hold-and-knee detection circuit with adaptive precharge capability of claim 1, wherein the buffer comprises a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, a twelfth NMOS transistor, a second resistor, a third resistor, a fourth resistor; the first comparator comprises a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, an eleventh NMOS tube, a second resistor, a third resistor and a fourth resistor;
the source electrodes of the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube, the sixth PMOS tube and the seventh PMOS tube are all connected with a power supply; the grid and the drain of the second PMOS tube are interconnected, and the drain of the second PMOS tube is connected with a current source; the grid electrodes of the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube, the sixth PMOS tube and the seventh PMOS tube are all connected with the drain electrode of the second PMOS tube;
the source electrode of the eighth PMOS tube is connected with the drain electrode of the third PMOS tube, the grid electrode of the eighth PMOS tube is connected with feedback voltage after passing through a fourth resistor, and the drain electrode of the eighth PMOS tube is grounded after passing through a second resistor;
the source electrode of the ninth PMOS tube is connected with the drain electrode of the third PMOS tube, the grid electrode of the ninth PMOS tube is connected with the drain electrode of the fourth NMOS tube, and the drain electrode of the ninth PMOS tube is grounded after passing through the third resistor;
the drain electrode of the ninth NMOS tube is connected with the feedback voltage through a fourth resistor, the grid electrode of the ninth NMOS tube is interconnected with the source electrode of the ninth NMOS tube, and the source electrode of the ninth NMOS tube is grounded;
the grid electrode and the drain electrode of the eighth NMOS tube are connected with the drain electrode of the fourth PMOS tube, and the source electrode of the eighth NMOS tube is grounded through the second resistor; the drain electrode of the seventh NMOS tube is connected with the drain electrode of the fifth PMOS tube, the grid electrode of the seventh NMOS tube is connected with the drain electrode of the eighth NMOS tube, and the source electrode of the seventh NMOS tube is grounded through a third resistor;
the drain electrode of the sixth NMOS tube is connected with the drain electrode of the sixth PMOS tube, the grid electrode of the sixth NMOS tube is connected with the drain electrode of the seventh NMOS tube, and the source electrode of the sixth NMOS tube is grounded;
the drain electrode of the eleventh NMOS tube is connected with the drain electrode of the seventh PMOS tube, the grid electrode of the eleventh NMOS tube is connected with the second enabling signal, and the source electrode of the eleventh NMOS tube is grounded;
the connection point of the drain electrode of the sixth PMOS tube, the drain electrode of the sixth NMOS tube and the drain electrode of the eleventh NMOS tube is the output end of the first comparator;
the drain electrode of the fifth NMOS tube is connected with the power supply, and the grid electrode of the fifth NMOS tube is connected with the drain electrode of the seventh NMOS tube; the grid electrode and the drain electrode of the tenth NMOS tube are connected with the drain electrode of the seventh PMOS tube, and the source electrode of the tenth NMOS tube is grounded; the drain electrode of the fourth NMOS tube is connected with the source electrode of the fifth NMOS tube, the grid electrode of the fourth NMOS tube is connected with the drain electrode of the tenth NMOS tube, and the source electrode of the fourth NMOS tube is grounded;
the drain electrode of the twelfth NMOS tube is connected with the drain electrode of the seventh PMOS tube, the grid electrode of the twelfth NMOS tube is connected with the first enabling signal, and the source electrode of the twelfth NMOS tube is grounded;
and the connection point of the source electrode of the fifth NMOS tube, the grid electrode of the ninth PMOS tube and the drain electrode of the fourth NMOS tube is the output end of the buffer.
CN202211041122.6A 2022-08-29 2022-08-29 Sampling holding and knee point detection circuit with self-adaptive precharge capability Pending CN115407227A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211041122.6A CN115407227A (en) 2022-08-29 2022-08-29 Sampling holding and knee point detection circuit with self-adaptive precharge capability

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211041122.6A CN115407227A (en) 2022-08-29 2022-08-29 Sampling holding and knee point detection circuit with self-adaptive precharge capability

Publications (1)

Publication Number Publication Date
CN115407227A true CN115407227A (en) 2022-11-29

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211041122.6A Pending CN115407227A (en) 2022-08-29 2022-08-29 Sampling holding and knee point detection circuit with self-adaptive precharge capability

Country Status (1)

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CN (1) CN115407227A (en)

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