CN1154020A - Matched filter circuit - Google Patents

Abstract

The present invention has an object to provide a matched filter circuit which is possible to synchronize a spreading code with an input signal. A matched filter according to the present invention samples input signal in response to three clocks from the first to the third shifted by a half cycle of a sampling signal so as to judge whether the sampling clock is ahead or behind of the input signal according to signs of input signal sampled. One clock is selected to be the sampling clock.

Description

Circuit matched with wave filter

The present invention relates to a kind of circuit matched with wave filter that is used for mobile spread spectrum communication system and individual radio LAN, specially refer to and a kind ofly can reduce under the situation of power loss to use small size LSI to carry out the matched filter of high speed processing.

Matched filter is a kind of filter that is used to identify two signal identifications.In spread spectrum communication, a unique extended code sequence is assigned to the user.Each user obtains a signal that is transferred to this user by a matched filter, and this matched filter has been applied in an extended code sequence.When this signal is to be used to gather and during the subscriber signal that keeps, correlation peak of matched filter output.

Suppose extended code be PN (i), top time are Tc, spreading rate be M, time are (t), the input signal located in the time (t) is that S (t) and the related output signal located in the time (t) are R (t), so, can obtain formula (1): $R\left(t\right)=\underset{i=0}{\overset{M-1}{\mathrm{\Σ}}}\mathrm{PN}\left(i\right)\·S(t-i\·\mathrm{Tc})----\left(1\right)$

Here, PN (i) is a Bit data sequence.

S (t-iTc) is a value of carrying out sampling at a chip in the time.When the hyposynchrony of input signal and sampling clock is enough, the low and output level step-down of R (T) subsequently of each S (t-iTc) level.Thereby make Peak detection accuracy reduce.

When needing the sampling of two rank or higher-order for collection, use a plurality of matched filters in a plurality of systems, to carry out the calculating of formula (1) simultaneously, and, result of calculation is carried out addition.In order to realize such " matched filter system " (representing mutually combining of a plurality of matched filters and some other circuit), use a kind of digital circuit or SAW (surface acoustic wave) device usually with this expression formula.But, when using digital circuit, because circuit size is very big, so electrical piano power loss is very big.Therefore, it is unsuitable for mobile communication.When using the SAW element, it is not easy to use the LSI device to realize entire circuit, so S/N ratio step-down.

Because described extended code is a bit information string, so the inventor has advised a kind of matched filter of the high speed processing with small size and low-power consumption LSI by following processing in Japanese patent application NO.7-212438 document, this processing comprises i) input signal is sampled and kept with as the analog signal of time series, ii) utilize the multiplexer device they to be branched into a plurality of sets of signals of " 1 " and " 1 " and iii) utilize capacitive coupling with each the group in the signal parallel addition.

But clearly expression relates to synchronous any solution of input signal and sampling clock in the above-mentioned application.

The present invention will address the above problem exactly, and purpose of the present invention will provide a kind of circuit matched with wave filter exactly, and this circuit can make extended code and input signal synchronous.

Input signal is sampled by three clocks of from first to the 3rd of sampled signal half period displacement according to matched filter according to the present invention response, so that be in advance or lag behind input signal according to the symbol decision sampling clock of institute's sampled input signal.Select a clock as sampling clock.

The block diagram of Fig. 1 shows the total according to the embodiment of a circuit matched with wave filter of the present invention.

The sampling clock that the block diagram of Fig. 2 shows in the present embodiment produces circuit.

The phase signal that Fig. 3 shows in the present embodiment produces circuit.

Fig. 4 shows the calculating section of matched filter in the present embodiment.

Fig. 5 shows sampling and the holding circuit in Fig. 4.

Fig. 6 shows the switch among Fig. 5.

Fig. 7 shows the multiplexer in Fig. 5.

Fig. 8 shows the first adder in Fig. 4.

Fig. 9 shows the circuit of slender acanthopanax musical instruments used in a Buddhist or Taoist mass in Fig. 4.

Figure 10 shows the circuit of the 6th adder in Fig. 4.

Figure 11 shows the circuit that is used to produce reference voltage.

Figure 12 shows the curve that concerns between input signal and the sampling clock.

The sampling clock that Figure 13 shows in a second embodiment produces circuit.

Figure 14 shows the curve of output of the loop filter of sampling clock generation circuit in Figure 13.

Below, an embodiment according to matched filter of the present invention is described with reference to the accompanying drawings.

In Fig. 1, respond a sampling clock ACLK and utilize matched filter MF that input signal S (t) is sampled, and, by a matched filter MF output output signal R (t).Sampled signal is produced by the sampling clock generation circuit of Fig. 2 and by the phase regulating circuit PA output of sampling clock generation circuit.A high frequency fundamental clock CLK who is higher than the sampling clock of sampling clock the 8th Cycle Length is transfused to phase regulating circuit, and this phase regulating circuit produces sampling clock from fundamental clock.Signal that matched filter MF produces and sampling clock ACLK is synchronous within master clock MCLK and the inversion signal SCLK of MCLK, as shown in Figure 3.Input signal S (t) response is sampled by these signals MCLK of continuous one by one three displacements of sampling clock half period and SCLK signal.Phase regulating circuit output expression is sampled signal MSE and the MS that the symbol of input signal combines.

In Fig. 2, sampling clock produces circuit PHC and is made up of an adjusting clock generation circuit FD and a clock multiplexer MUX2.FD produces continuous 8 the different sampling clocks that are shifted continuously one by one by 1/8 cycle.Clock CLK is divided into 8 short pulses that are used for 8 sampling clocks.Work period is divided into 8.Multiplexer MUX2 exports in 8 kinds of sampling clocks one selectively as ACLK.

Utilize phase signal to produce circuit PSG and produce signal MSE and MS, and sampling clock produces circuit PHC and utilizes convergence decision circuitry CJ that signal MSE and MS are judged.Circuit PSJ and CJ have constituted a phase place decision circuitry PJ, and this phase place decision circuitry PJ judges the relation between sampling clock and the input signal.

In Fig. 3, circuit PSG is made up of the MOS inverter I31 and the I32 of series connection, and input signal S (t) is transfused to first inverter 131.When S (t) is a plus signal, I31 and I32 output supply voltage Vdd, and when S (t) was a cut signal, I31 and I32 exported a no-voltage, that is: they produce a plurality of mark signals.The output of I32 is transfused to the data input pin to trigger FF31 in parallel and FF32.MCLK is transfused to the input end of clock of FF31 and SCLK and is transfused to FF32.The rising of FF31 and FF32 response clock keeps data.When FF32 kept the mark signal of S (t), FF31 had kept the mark signal of S (t-Tc/2).The data input pin of trigger FF33 is connected to the noninverting output Q of FF31, and MCLK is transfused to the input end of clock to FF33.Therefore, FF33 keeps the mark signal of S (t-Tc).The data input pin of trigger FF34 is connected to the noninverting output of FF32, and MCLK is transfused to the input end of clock to FF34.FF34 keeps the mark signal of S (t-Tc/2) in this point.Mark signal by the continuous input signal that is shifted of 1/2 cycle is kept by FF33, FF34, FF31 and FF32.These mark signals are by SGN (t-TC), SGN (t-Tc/2), SGN (t) and SGN (t+Tc/2) expression.The noninverting output Qs of trigger FF33 and FF34 is connected respectively to logic gates LG1 and LG2.The noninverting output of FF31 and FF33 is inputed to LG1 and LG2 simultaneously respectively.LG1 and LG2 are respectively the logic gates of EX_OR and EX_NOR, and MSE and MS are calculated in the logical operation below they utilize.

MSE＝SGN(t)SGN(t-Tc) (2)

MS＝SGN(t-Tc/2)SGN(t-Tc) (3)

Formula (2) means that the symbol of the input signal in current period and cycle in the past is different, and it has provided the prerequisite that phase place is judged.When the symbol of input signal keeps continuous when constant, can not carry out phase place and judge.Utilizing circuit CJ to carry out phase place when MSE=1 in formula (2) judges.

Formula (3) shows the difference between the signal code when the signal code of the leading Tc/2 than S (t) and further leading Tc/2.As shown in figure 12, when input signal S (t) by with continuous three whens sampling on an A, B and C one by one in 1/2 cycle, the S (t) in the formula (3), S (t-Tc/2) and S (t-Tc) correspond respectively to an A, B and C.When the phase place of sampling clock was ahead of input signal, the time span of the starting point from A to described cycle tA was equal to or less than (Tc/2).B was included in the one-period identical with A, and C is included in A in the cycle different with B.(not shown) when sampling clock lags behind, the time span from A to this cycle starting point is equal to or greater than Tc/2.B was included in the cycle different with A, and C was included in the cycle identical with B.When S (t-Tc/2) and S (t-Tc) are arranged in one-period, MS=1, when being arranged in the different cycles when them, MS=0.That is: when MS=1, sampling clock is leading, and when MS=0, sampling clock lags behind.

Circuit CJ judges and to import the expression sampling clock be in advance or a signal that lags behind is given control signal generation circuit SG above-mentioned.Control signal generation circuit SG response is from the conversion of signals multiplexer MUX2 of CJ, so that make sampling clock under the leading situation of this sampling clock, be delayed for 1/8 cycle, and under the situation that sampling clock lags behind, making clock by 1/8 cycle of shifting to an earlier date, circuit FD, Mux2 and SG constitute phase-adjusting circuit PA.Clock unit needed not to be for 1/8 cycle, also needed not to be a constant.

Circuit CJ judges when repeating to import MS=1 and MS=0, whether input signal and sampling clock be synchronized with each other, promptly, when repeating the input sample clock with a predetermined times (for example 10 times), it judge that phase adjusted is assembled and for a predetermined cycle (for example cycle of tens symbols) not excute phase regulate.

In the circuit matched with wave filter MF of Fig. 4, an input voltage S (t) is connected on a plurality of samplings and holding circuit SH1, SH2, SH3, SH4, SH5 and the SH6 concurrently, and produces H (height) and two kinds of outputs of L (low) from each sampling and holding circuit.(TRL is connected to this sampling and holding circuit to a control circuit, so that control is imported into the S (t) of a sampling and holding circuit in succession.

Sampling and holding circuit are introduced input voltage S (t) to H side or L side according to the control of control circuit.Utilize control circuit that a reference voltage V r is connected to the other end.This Path selection is according to each execution of extended code (PN code), and only utilizes this to select to realize that input voltage and described code multiply each other.

The structure of sampling and holding circuit SH1 as shown in Figure 5.In the figure, input voltage S (t) is connected on the switch SW.The output of switch SW is connected on the capacitor C 51, and three grades of MOS inverter I1, I2 and I3 are connected on the output of capacitor C 51.The output of the MOS inverter I3 of afterbody V05 is connected on the input of I1 through feedback capacity 52.Then, the output generation at I3 has the opposite voltage of good linear S (t).The output of I3 is transfused to two multiplexer MUX51 and MUX52.A common reference voltage is connected to described multiplexer.When SW was closed, C51 was by being recharged with the corresponding electric charge of S (t), and, utilize I1 to guarantee the linearity of output to the feedback function of I3.When switch SW was opened after this, sampling and holding circuit SH1 just kept S (t).

Switch SW, multiplexer MUX51 and MUX52 are by control signal S1, S2 and S3 control.In case after S1 was closed, only SW just was opened when the input voltage sampling timing.S2 and S3 are two opposite signals.When one in described multiplexer output Vin5, another exports Vr.

Multiplexer MUX51 produces above-mentioned H (high type) output and multiplexer MUX52 produces L (low type) output.H and L are corresponding to each position (bit) in extended code " 1 " and " 1 ".When code " 1 " need be multiplied by an input voltage, from described MUX51 output Vin5, and when code " 1 " need be multiplied by input voltage, from MUX52 output Vin5.

Output from afterbody I3 is grounded through ground capacity C53.The output of second level I2 is connected to power supply Vdd, and through a pair of balance resistance R51 and R52 ground connection.Can avoid comprising the unstable oscillation of the inverting amplifier of feedback circuit by a kind of like this structure.

As shown in Figure 6, switch SW comprises a transistor circuit T6, and in this transistor circuit T6, the source electrode of a n type MOS transistor and drain electrode are connected to respectively in the drain electrode and source electrode of a P type MOS transistor.Vin6 is connected to the drain electrode end of the n type MOS transistor of this transistor circuit, and the source terminal of this n type MOS transistor is connected to output end vo ut6 by the similar emulation transistor DT6 of process and n type MOS transistor.S1 is imported into the grid of the n type MOS transistor of transistor circuit T6, and signal by the anti-phase S1 of inverter 16 is transfused to the grid to P type MOS transistor.When S1 was high level, T6 was switched on, and when it was low level, T6 was cut off.

As shown in Figure 7, in multiplexer MUX51, the source terminal of transistor circuit T71 and T72 is connected to public output Vout7.The output of MOS inverter I3 (" vin71 " in Fig. 7) is connected to the drain electrode end of the n type MOS transistor of T71D, and reference voltage V r is connected to the drain electrode end (" Vin72 " in Fig. 7) of T72.Signal S2 is transfused to the gate terminal to the P type MOS transistor of the gate terminal of the n type MOS transistor of transistor circuit T71 and transistor circuit T72.Be transfused to gate terminal by inverter 17 anti-phase signal S2 to the n type MOS transistor of the P type MOS transistor of T71 and T72.When S2 is high level, T71 conducting and T72 ends, and when S2 is low level, T72 conducting and T71 ends.That is: MUX51 can alternately export V05 or Vr by responsive control signal S2.

Though do not illustrate in the drawings,, structure and the MUX51 of multiplexer MUX52 are similar, and V05 is to be connected on the contrary with Vr.V05 among Fig. 7 and Vr are connected to T72 and T71 respectively, this inverted configuration lucky and Fig. 7.Then, the output of MUX52 is opposite with the output of MUX51, that is: when MUX51 output V03, MUX52 exports Vr.When MUX51 output Vr, MUX52 exports V05.

Signal S2 is corresponding with extended code, and when S2=1, output 1XS (t)=S (t) give AD41.At this moment, S3 is " 1 " and be exported to ADD42 with " 0 " corresponding Vr.When S2=-1, corresponding Vr is exported to ADD41 with " 0 ".Here, S3=+1, and output 1XS (t)=S (t) gives ADD42.

S (t-iTc) in formula (1) is an input voltage that remains in each sampling and the holding circuit, and PN (i) is the signal S2 (extended code) that will input to each sampling and holding circuit.The rank of extended code are predetermined corresponding to the rank of input signal.When being taken into a new signal, from up-to-date signal, deduct the oldest signal.This makes and changes to the relation between SH6 and the PN (i) in each sampling and holding circuit SH1, thus the displacement of PN (i) controlled signal.When not having the run time version displacement, code is through continuous sampling and holding circuit transmission, and because transfer of data may produce some error.Should be appreciated that run time version displacement can effectively avoid producing error in the process of transfer of data.

Adding up of formula (1) is to be performed in the addition section from ADD41 to ADD46, and the VH and the VL of each sampling and holding circuit output voltage add up in ADD45 and ADD46 respectively.This adds up and does not directly carry out.Sampling and holding circuit are divided into a plurality of groups, and output VH and VL once add up by each group in ADD46 at ADD41.The ADD41 of the VH that adds up that is useful on and the output of ADD43 are transfused to ADD45 and the ADD42 of the VL that adds up that is useful on and the output of ADD44 and are transfused to ADD46.In addition, the output of ADD45 also is transfused to ADD46.In Fig. 4, six samplings and holding circuit are illustrated, and are divided into every group of two groups that three circuit are arranged.Usually extended code comprises from 100 to hundreds of or more position (bit).Sampling and holding circuit are configured to suitable numeral.

As shown in Figure 8, addition section ADD41 comprises by quantity and equals in one group the capacitive coupling CP8 that capacitor C 81, C82 and the C83 of sampling and holding circuit quantity constitute.The output of CP8 is connected to MOS inverter I81, I82 and the I83 of three grades of series connection.The output of afterbody MOS inverter I83 is connected on the input of I81 through feedback capacity C84.Produce the output of CP8 at the output of the I83 with good linear.Suppose that the input voltage of capacitor C 81, C82 and C83 is Vin81, Vin82 and Vin83, so, the output Vout8 of I83 can use equation (4) expression. $\mathrm{Vout}8=-\frac{C81\mathrm{Vin}81+C82\mathrm{Vin}82+C83\mathrm{Vin}83}{C84}----\left(4\right)$

Here, Vin81 is the voltage of reference data voltage Vr to Vin83.Also the capacity ratio of regulation capacitor C 81, C82, C83 and C84 is 1: 1: 1 in addition: 3.The normalization output of anti-phase addition value can be obtained by following equation (5). $\mathrm{Vout}8=-\frac{\mathrm{Vin}81+\mathrm{Vin}82+\mathrm{Vin}83}{3}----\left(5\right)$ By means of normalization, maximum voltage is limited under the supply voltage.

The output of afterbody I83 is grounded through ground capacity C85.The output of second level inverter I82 is connected to supply voltage Vdd and a pair of balance resistance R81 of process and R82 ground connection.Utilize this structure to avoid comprising the unstable oscillation of the see-saw circuit of feedback line.

As shown in Figure 9, addition section ADD45 comprises a capacitive coupling CP9, and this CP9 includes capacitor C 91 and the C92 with the corresponding quantity of quantity of addition section ADD41 and ADD43.The output of CP9 is connected to three grades of series connection MOS inverter I91, I92 and I93.The output of afterbody MOS inverter 193 is connected on the input of I91 through feedback capacity C93.On the output of the I93 with good linear, produce the output of CP9.Suppose that the input voltage of capacitor C 91 and C92 is Vin91 and Vin92, the output Vout9 of I93 can use equation (6) expression so. $\mathrm{Vout}9=-\frac{C91\mathrm{Vin}91+C92\mathrm{Vin}92}{C93}----\left(6\right)$

Here, Vin91 and Vin92 are the voltage of reference data voltage Vr.Described capacity ratio is C91: C92: C93=1: 1: 2.So, the normalization of anti-phase addition output can be obtained by equation (7). $\mathrm{Vout}9=-\frac{\mathrm{Vin}91+\mathrm{Vin}92}{2}----\left(7\right)$

By normalization, maximum is limited under the supply voltage.

The output of afterbody inverter I93 is through ground capacity C94 ground connection.The output of second level inverter I92 is connected on the supply voltage and a pair of balance resistance R91 of process and R92 ground connection.Avoided comprising the unstable oscillation of the see-saw circuit of feedback line.

As shown in figure 10, addition ADD46 comprises capacitive coupling CP10, this CP10 comprises the corresponding capacitor C 101 of the quantity of quantity and connected addition section ADD42, ADD44 and ADD45, C102H and C103, and the output of CP10 is connected on three grades of series connection MOS inverter I101, I102 and the I103.The output of afterbody MOS inverter I103 is connected on the input of I101 through feedback capacity C104.Produce the output of CP10 at the output of the I103 with good linear.The input voltage (with reference to the voltage of Vr) of supposing capacitor C 101, C102 and C103 is Vin101, Vin102 and Vin103, and so, the output Vout10 of I103 (with reference to the voltage of Vr) can be represented by equation (8). $\mathrm{Vout}10=-\frac{C101\mathrm{vin}101+C102\mathrm{vin}102+C103\mathrm{Vin}103}{C104}----\left(8\right)$

Its regulation: capacity ratio is C101: C102: C103: C104=1: 1: 2: 2.The normalization output of anti-phase addition value can be represented by equation (9). $\mathrm{Vout}10=-\frac{\mathrm{Vin}101+\mathrm{Vin}102+2\mathrm{Vin}103}{2}----\left(9\right)$

Here, it is that the twice of C101 and C102 is big that the power of C103 is prescribed, so that cancellation ADD45 is to normalized interference and admit not normalized V101 and 102.By normalization, maximum voltage is limited under the supply voltage.

The output of afterbody inverter I103 is grounded through ground capacity C105.The output of second level inverter I102 is connected to supply voltage Vdd and a pair of balance resistance R101 of process and R102 ground connection.Avoided comprising the unstable oscillation of the see-saw circuit of feedback line.

Utilize the reference voltage generating circuit Vref of Figure 11 to produce reference voltage V r.Reference voltage generating circuit comprises three grades of series connection inverter I111, I112 and I113, and the output of afterbody is fed the input to the first order.Similar to anti-phase amplifier section, utilize ground capacity C116 and balance resistance R 111 and R112 to avoid unstable oscillation.The output of reference voltage circuit Vref converges on the point of safes, and at that point, input and output voltage is equal to each other, and, can produce a reference voltage by the threshold value that changes each MOS inverter.Usually, in many cases, enough big in order to remain on the dynamic range that adds and subtract on the both direction, Vr is arranged to equal Vdd/2.At this moment, Vdd is the supply voltage of MOS inverter.

Consider above-mentioned circuit matched with wave filter owing to utilize a capacity coupled analogue system to carry out addition, so and digital filter its circuit size of comparing reduce widely, and, owing to parallel addition makes processing speed improve.When the input and output of all samplings and holding circuit and addition section all were voltage signal, the loss of power was low-down.

The output accuracy of addition section depends on the Dispersion of capacity ratio between the anti-phase characteristic of MOS and a plurality of electric capacity.Can be by they being placed to such an extent that the frequency dispersion that makes closer to each other minimizes.The precision of the capacity ratio of a capacitor can be improved by disperseing to connect a plurality of cell capacitance.

Sampling clock in the above-described embodiments produces circuit PHC and carries out the discrete phase adjusting, and the sampling clock among Figure 13 produces circuit PHC can also carry out continuous adjusting.

In Figure 13, described sampling clock produces circuit PHC and produces circuit PSG and one by a phase signal and form with Fig. 1 and similar convergence decision circuitry CJ shown in Figure 3.The MSE of this circuit PSG and the output of MS are imported into circuit CJ.The output of circuit CJ is transfused to gate LG3, and sampling clock ACLK and signal MSE also are transfused to this gate LG3.The output of LG3 is transfused to the input end of clock to forward-backward counter CNT.Signal MS is transfused to the reversible appointment input U/D to contrary counter cnt.The door LG3 be an AND (with) door.When it can not be judged phase place, that is, when MSE=0, door LG3 is closed.When phase-adjusted judgement converged at circuit CJ, output signal was closed door LG3.When door was opened, clock ACLK was transfused to counter cnt and counts.On this time point, MS illustrates advancing of this phase place and lags behind.This counter cnt is carried out and the corresponding two-way counting of MS

The count value of counter cnt is used as a numeral output and inputs to loop filter LF, and utilizes this loop filter LF to come the accumulation in time of count value by a voltage.As shown in figure 14, the output of loop filter LF advancing or lagging behind and increase or reduce according to a phase place.After the output of counter cnt being carried out smoothly, loop filter LF exports a correspondent voltage.The reference voltage of output is V0.The output of loop filter LF is transfused to voltage controlled oscillator VC0 and carries out the phase adjusted of clock ACLK.In VC0, when being higher than reference voltage V 0 with the count value correspondent voltage, according to the differential delay phase place, and when voltage is low, according to the fixing described phase place of difference.Therefore, the clock ACLK of output through overregulating.Regulate the phase place of ACLK according to following equation (10).(reference: " spread spectrum communication system ", Mitsuo YOKOYAMA, Kagaku-Gijutsu Shuppansha, 1988). $\frac{\mathrm{d\φ}\left(t\right)}{\mathrm{dt}}=2\mathrm{\πfc}+\mathrm{Ke}\left(t\right)-----\left(10\right)$

φ (t): the phase place of sampling clock (radian)

T: time (second)

Fc: the frequency of sampling clock (Hz)

The constant-gain of K:VC0 (radian per second * volt)

E (t): input voltage (volt)

According to three clocks that matched filter according to the present invention response was shifted by half sampling clock cycle from first to the 3rd input signal is sampled, so that be in advance or lag behind input signal according to the symbol decision sampling clock of institute's sampled input signal.Clock is selected as sampling clock and regulates according to this sampling clock excute phase.Therefore, can make input signal and sampling clock synchronous.

Claims (14)

1, a kind of circuit matched with wave filter comprises

I) sampling section is used to respond a sampling clock input signal is sampled;

Ii) a multiplication part is used for described input signal be multiply by a PN code sequence;

Iii) part that adds up, the output of the described multiplication part that is used to add up; And

Iv) a sampling clock produces part, is used to produce described sampling clock, and described sampling clock generating unit branch comprises:

(a) phase place decision circuitry, the response of this circuit by the half period of described sampling clock one by one from first to the 3rd continuously three clocks of displacement described input signal is sampled so that be in advance or lag behind described input signal according to the described sampling clock of symbol decision of the described input of sample; With

(b) phase regulating circuit is used for regulating according to the output of described phase place decision circuitry the phase place of described sampling clock.

2, circuit matched with wave filter as claimed in claim 1, described phase regulating circuit comprises:

I) regulate clock generation circuit for one, be used to be created in a plurality of clocks within the described input signal one-period, the frequency of these clocks equals the frequency of described sampling clock;

Ii) clock multiplexer, one that is used for exporting selectively a plurality of clocks of being produced by described adjusting clock generation circuit as described sampling clock;

Iii) a clock selection circuit is used for controlling and change described clock multiplexer according to the output of described phase place decision circuitry.

3, circuit matched with wave filter as claimed in claim 1, described phase regulating circuit comprises:

Whether i) forward-backward counter is used for leading or lag behind and count described sampling clock up or down according to described sampling clock;

Ii) a loop filter is used for the described count value by comprehensive described forward-backward counter of time;

Iii) one is used to receive the voltage controlled oscillator that described loop filter is exported.

4, circuit matched with wave filter as claimed in claim 2, wherein, described phase regulating circuit judges that described phase place was stable when the lead and lag that replaces when described clock was in described sampling clock, and stops phase adjusted at a predetermined period of time.

5, circuit matched with wave filter as claimed in claim 1 wherein, has only when by described first and the symbol of the described input signal of the 3rd clock sampling when inequality, just carries out a judgement by described phase place decision circuitry.

6, circuit matched with wave filter as claimed in claim 1, wherein, when the symbol by the described input signal of described first and second clock samplings was equal to each other, described phase place decision circuitry judged that described sampling clock is leading, and when described symbol differs from one another, judge that it lags behind.

7, circuit matched with wave filter as claimed in claim 1 comprises:

(I) a plurality of samplings and holding circuit; Wherein each comprises:

I) be connected to a switch of input voltage,

Ii) be connected to first electric capacity of an output of described switch,

The iii) first anti-phase amplifier section, this part has the odd level MOS inverter that is connected to the described first electric capacity output,

Iv) first feedback capacity is used for the output of the described first anti-phase amplifier section is connected to its input, and

V) first and second multiplexers are used for alternately exporting the output or the reference voltage of the described first anti-phase amplifier section;

(II) first addition section; This part comprises;

I) with described sampling and corresponding a plurality of second electric capacity of holding circuit, the output of a circuit in described sampling and the holding circuit is connected on wherein each,

The ii) second anti-phase amplifier section, this amplifier section have the coupled odd level MOS inverter of output of described second electric capacity usually,

Iii) second feedback capacity is used for the output of the described second anti-phase amplifier section is connected to its input;

(III) second addition section, this part comprises:

I) the 3rd corresponding electric capacity of a plurality of and described sampling and holding circuit, wherein each all are connected to the output of described second multiplexer and the output of described each sampling and described first addition section of holding circuit,

Ii) the 3rd anti-phase amplifier section, this amplifier section have usually the coupled odd level MOS inverter of the output of described the 3rd electric capacity and

Iii) the 3rd feedback capacity is used for the output of described the 3rd anti-phase amplifier section is connected to its input;

(IV) subtraction part is used for deducting from the output of described first addition section output of described second addition section,

(V) control circuit, this circuit is closed described switch in a described sampling and holding circuit, open another switch simultaneously, and utilize a predetermined combination that described first and second multiplexers of each sampling and holding circuit are changed.

8, circuit matched with wave filter as claimed in claim 7, wherein, described sampling and holding circuit are divided into a plurality of groups, and wherein each group comprises:

(I) be connected to the 4th addition section of the described first multiplexer output, the output of all described the 4th addition section of described group is transfused to described second addition section, and described the 4th addition section comprises:

Each links to each other the output and its of described first multiplexer in (a) a plurality of the 4th electric capacity, each described a plurality of sampling and holding circuit;

(b) the 4th anti-phase amplifier section, this amplifier section have the MOS inverter of odd number series connection, a plurality of outputs of described the 4th electric capacity coupled usually and

(c) the 4th feedback capacity is used for the output of described the 4th anti-phase amplifier section is connected to its input,

(II) be connected to the slender acanthopanax method part of described second multiplexer, outputs of all described slender acanthopanax method parts of described group all are transfused to described first addition section, and described slender acanthopanax method partly comprises:

(a) a plurality of the 5th electric capacity, the output of the described output of described second multiplexer of circuit and described first addition section is transfused to in described a plurality of the 5th electric capacity each in each described a plurality of sampling and the holding circuit;

(b) the 5th anti-phase amplifier section, this amplifier section have odd number series connection MOS inverter, and these inverters are connected on the output of described the 5th electric capacity usually;

(c) the 5th feedback capacity is used for the output of described the 5th anti-phase amplifier section is connected to its input.

9, circuit matched with wave filter as claimed in claim 7, wherein, described reference voltage is produced by a reference voltage generating circuit, and described reference voltage generating circuit comprises the 6th anti-phase amplifier section with odd level MOS inverter, and its output is connected to its input.

10, circuit matched with wave filter as claimed in claim 7, described anti-phase amplifier section also are included in a ground capacity and a pair of balance resistance that the output of another MOS inverter is connected to power supply and ground except last MOS inverter that connects between described output and the ground.

11, circuit matched with wave filter as claimed in claim 9, wherein, described reference voltage is set to be 1/2 of described MOS inverter supply voltage.

12, circuit matched with wave filter as claimed in claim 7, wherein, described control circuit described all samplings of control and holding circuit, thus the cycle of states of described sampling and holding circuit is changed.

13, circuit matched with wave filter as claimed in claim 7, wherein, described first multiplexer is exported the described output or the described reference voltage of the described first anti-phase amplifier section in turn, and described second multiplexer is exported the described output or the described reference voltage of the described first anti-phase amplifier section in turn by the opposite selection of described first multiplexer.

14, circuit matched with wave filter as claimed in claim 7, wherein, the described output of the described first anti-phase amplifier section of one of described first and second multiplexers output, perhaps their boths export described reference voltage.

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