CN115389911B - Chip scheduler fault judgment method and device, electronic equipment and storage medium - Google Patents
Chip scheduler fault judgment method and device, electronic equipment and storage medium Download PDFInfo
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Abstract
The embodiment of the application discloses a chip scheduler fault judgment method and device, electronic equipment and a storage medium. The method comprises the following steps: the method comprises the steps that a scheduler obtains binary codes of all scheduling units in a scheduling table, converts the binary code patterns of all scheduling units into unique hot code patterns, and obtains the unique hot codes of all scheduling units; the scheduler performs scheduling operation based on the one-hot codes of the scheduling units and preset scheduling operation logic to obtain a scheduling result of the scheduling; the scheduler sends the scheduling result to the safety inspection module after caching the scheduling result by the signal buffer; the safety check module judges whether the scheduling result meets the requirement of the one-hot code type or not, and judges that the scheduler fails under the condition that the scheduling result does not meet the requirement of the one-hot code type. By utilizing the higher identifiability of the one-hot code type, the failure of the scheduler can be quickly determined, so that the scheduling function reaches the safety level specified by the ISO26262 standard. Meanwhile, the chip resources occupied by the scheduler module are prevented from being increased by times.
Description
Technical Field
The embodiment of the application relates to the technical field of chip fault determination, in particular to a chip scheduler fault judgment method and device, electronic equipment and a storage medium.
Background
In a car-scale chip, a plurality of gates are usually provided, for example, a scheduler module in the car-scale chip is usually composed of electrical elements such as gate devices, resistors and capacitors, as electronic devices, in a use process, permanent damage of the gates or transient level inversion caused by environmental interference, such as particle rays, may occur, so that a scheduler fails, and at this time, a scheduling function of the car-scale chip cannot be guaranteed by a corresponding safety level.
At present, various functions in a vehicle-specification-level chip need to reach corresponding safety levels based on the ISO26262 standard, and for a scheduler module corresponding to a scheduling function, in order to identify whether the scheduler module has a fault in the related art, a design manner of dual-module redundancy or triple-module redundancy is usually adopted, so that the scheduling function reaches the corresponding safety levels of the ISO26262 standard.
Taking dual-module redundancy as an example, two identical scheduler modules are usually set, the inputs of the two scheduler modules are identical, and whether the scheduler modules have faults is judged by judging whether the outputs of the comparators are identical. The method usually doubles the chip resources occupied by the scheduler module, and also puts extra restrictions on the back-end layout and wiring, which not only pays high resource cost, but also increases the development difficulty.
Disclosure of Invention
The embodiment of the application provides a method and a device for judging the fault of a chip scheduler, electronic equipment and a storage medium, which can realize fault judgment, avoid multiplying chip resources occupied by a scheduler module and reduce development difficulty.
In a first aspect, an embodiment of the present application provides a method for determining a fault of a chip scheduler,
a signal buffer is arranged in the chip, the input end of the signal buffer is connected with the output end of the scheduler, and the output end of the signal buffer is connected with the safety inspection module;
the chip scheduler fault judgment method comprises the following steps:
the scheduler acquires the binary codes of all scheduling units in the scheduling table, converts the binary code patterns of all the scheduling units into unique hot code patterns and acquires the unique hot codes of all the scheduling units;
the scheduler performs scheduling operation based on the one-hot codes of the scheduling units and preset scheduling operation logic to obtain a scheduling result of the scheduling;
the scheduler sends the scheduling result to the safety check module after caching the scheduling result through the signal buffer;
and the safety check module judges whether the scheduling result meets the requirement of the one-hot code type or not, and judges that the scheduler breaks down under the condition that the scheduling result does not meet the requirement of the one-hot code type.
In a second aspect, an embodiment of the present application further provides a device for determining a fault of a chip scheduler,
a signal buffer is arranged in the chip, the input end of the signal buffer is connected with the output end of the scheduler, and the output end of the signal buffer is connected with the safety inspection module;
the chip scheduler fault judgment device comprises:
the code pattern conversion module is used for acquiring the binary codes of all scheduling units in the scheduling table by the scheduler, and converting the binary code patterns of all scheduling units into unique hot code patterns to obtain the unique hot codes of all scheduling units;
the scheduling module is used for the scheduler to perform scheduling operation based on the one-hot codes of the scheduling units and preset scheduling operation logic to obtain a scheduling result of the scheduling;
the buffer module is used for sending the scheduling result to the safety check module after the scheduler buffers the scheduling result through the signal buffer;
and the safety judgment module is used for judging whether the scheduling result meets the requirement of the one-hot code type or not by the safety check module and judging that the scheduler breaks down under the condition that the scheduling result does not meet the requirement of the one-hot code type.
In a third aspect, an embodiment of the present application further provides an electronic device, where the electronic device includes:
one or more processors;
a storage device for storing one or more programs,
when the one or more programs are executed by the one or more processors, the one or more processors are enabled to implement the chip scheduler fault diagnosis method provided in any embodiment of the present application.
In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored, where the computer program is executed by a processor to implement the chip scheduler fault determination method according to any embodiment of the present application.
In the technical scheme of the embodiment of the application, a signal buffer and a safety check module are arranged in a chip, the input end of the signal buffer is connected with the output end of a scheduler, and the output end of the signal buffer is connected with the safety check module. When the scheduling method is specifically executed, a scheduler acquires the binary code of each scheduling unit in a scheduling table, converts the binary code pattern of each scheduling unit into a unique hot code pattern to obtain the unique hot code of each scheduling unit, then carries out scheduling operation on the basis of the unique hot code of each scheduling unit and preset scheduling operation logic to obtain a scheduling result of the scheduling, caches the scheduling result through a signal buffer, and sends the scheduling result to a safety check module, the safety check module checks whether the scheduling result meets the requirement of the unique hot code pattern, and under the condition that the scheduling result does not meet the requirement of the unique hot code pattern, the scheduler is judged to have a fault. By utilizing the higher identifiability of the one-hot code type, after the scheduler has a problem, the scheduling result does not accord with the one-hot code type generally, and the scheduling result with the non-one-hot code type can be identified relatively quickly, so that the failure of the scheduler can be determined relatively quickly. Meanwhile, the method can be realized by only adding the signal buffer and the safety check module, thereby avoiding multiplying chip resources occupied by the scheduler module and reducing the development difficulty.
Drawings
Fig. 1 is a schematic flowchart of a method for determining a fault of a chip scheduler according to an embodiment of the present application;
fig. 2 is a diagram illustrating a chip scheduler architecture according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a chip scheduler fault determination apparatus according to a second embodiment of the present application;
fig. 4 is a schematic structural diagram of an electronic device according to a third embodiment of the present application.
Detailed Description
The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. It should be further noted that, for the convenience of description, only some of the structures related to the present application are shown in the drawings, not all of the structures.
Example one
Fig. 1 is a schematic flowchart of a method for determining a chip scheduler failure according to an embodiment of the present disclosure, which is applicable to a scenario of determining whether a chip scheduler fails.
In order to implement the method of the present embodiment, the present embodiment further adjusts the architecture of the chip, and specifically, refer to fig. 2, where fig. 2 is a diagram of a chip scheduler architecture provided in the first embodiment of the present application. As shown in fig. 2, in this embodiment, a signal buffer is disposed in the chip, an input end of the signal buffer is connected to an output end of the scheduler, and an output end of the signal buffer is connected to the security check module.
The signal buffer can be a trigger, the trigger is provided with an input end D and an output end Q, wherein the input end D is connected with the scheduler and used for receiving the scheduling result, the output end Q is divided into two paths, one path is output to a rear-stage module of the scheduler through the decoder, and the other path is output to the safety check module and used for checking whether the scheduling result is correct or not and reporting the scheduling result to the CPU through an interrupt interface when the scheduling result is incorrect.
It should be noted that the scheduler mentioned in this embodiment may be, but is not limited to, a scheduling circuit capable of implementing a scheduling function, and the buffer may be, but is not limited to, a buffer circuit capable of implementing a buffering function.
Based on the above architecture, the method of this embodiment may specifically include the following steps:
The scheduling table contains all scheduling units, the scheduling units refer to some basic units which can be scheduled by the chip, and the scheduling table can store the identification of each scheduling unit. In one specific example, there are 10 scheduling units in the schedule, as shown in table 1 below.
TABLE 1
It should be noted that the identifier of each scheduling unit in the scheduling table may be binary code, and may be obtained directly, and the binary codes of each scheduling unit are different from each other, and may play a role in identifying each scheduling unit.
Of course, the identifiers in some schedules may also be irregular names, for example, named by using the basic role of the scheduling unit as the identifier. For this situation, the present embodiment may first perform binary coding to obtain binary coding of each scheduling unit.
Specifically, the unit number of the scheduling units in the scheduling table may be obtained first, and binary coding may be performed on each scheduling unit according to the unit number to obtain the binary code corresponding to each scheduling unit.
When each scheduling unit is binary-coded according to the number of units, the scheduling units can be sequentially identified from small to large by using binary values, and the maximum binary value is the number of the units.
For example, after the unit number is obtained, binary values of the unit number are generated, for more specification, a difference between adjacent binary values from small to large is 1, the maximum binary data is a binary value corresponding to the unit number, for example, the unit number is 10, then the maximum binary value is 1010, and the generated binary values sequentially from small to large are: 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010.
The generated binary values are then assigned to each scheduling unit in sequence (the order of the scheduling units in the schedule) as the binary code for each scheduling unit.
In addition, when the code pattern is converted into the one-hot code pattern, the conversion can be performed according to the requirement of the one-hot code pattern. It should be noted that, in the one-hot code pattern, only one bit is 1, and the other bits are all 0, such as 100000, or 001000.
When the code pattern conversion is carried out, the number of the single hot codes can be determined according to the number of the units, and the binary codes of each scheduling unit correspond to different single hot codes; then, for any scheduling unit, determining the one-hot code corresponding to the binary code of the scheduling unit as the one-hot code of the scheduling unit.
Specifically, due to the characteristic of the one-hot code pattern, in order to make each scheduling unit have a corresponding one-hot code, the number of bits of the one-hot code needs to be determined first, and the number of the bits is consistent with the number of units of the scheduling unit, for example, the number of the units is 5, then the number of the bits of the one-hot code is also 5, the number of the units is 10, and the number of the bits of the one-hot code is also 10.
In a specific example, the number of cells is 10, then the one-hot codes with all bits of 10 are listed as 0000000001, 0000000010, 0000000100, 0000001000, 0000010000, 0000100000, 0001000000, 0010000000, 0100000000, 1000000000.
Then, the binary codes of the scheduling units correspond to different unique hot codes, it should be noted that the unique hot codes and the binary codes are converted into decimal numbers, and corresponding numerical values exist, so that codes with the same decimal value can correspond to each other, for example, when the binary 0001 and the unique hot code 0000000001 are both expressed as 1 in decimal numbers, the two codes are corresponding to each other.
The specific correspondence is shown in table 2 below.
TABLE 2
And 102, the scheduler performs scheduling operation based on the one-hot codes of the scheduling units and the preset scheduling operation logic to obtain a scheduling result of the current scheduling.
In this step, the preset scheduling operation logic mainly functions to obtain the scheduling unit to be scheduled for this scheduling, and in addition to the unique hot code of this embodiment, the preset scheduling operation logic may need an additional input signal to control the operation details of scheduling.
Since the specific scheduling operation process is not the content of interest in this embodiment, reference may be made to related technologies in this section, and details are not described here. It should be noted that after the scheduling operation in this step, a corresponding scheduling result is output, and the scheduling result includes a code corresponding to the scheduling unit to be scheduled.
In the case of a scheduler without a fault, the code is typically a one-hot code of some scheduling unit of the input.
And step 103, after the scheduling result is buffered by the scheduler through the signal buffer, the scheduling result is sent to the safety check module.
In this step, in order to send the scheduling result of the scheduler to the security check module without affecting the subsequent work after the scheduler sends the scheduling result, a signal buffer is specially provided, and the signal buffer can buffer the scheduling result and send the scheduling result out.
It should be noted that, the related principle of the trigger may refer to the related art, and is not described herein. In addition, the output end of the signal buffer is also connected with a rear-stage module of the scheduler. Specifically, a transcoder may be further disposed between the output end and a subsequent module of the scheduler, and the transcoder is configured to convert a code pattern of the scheduling result from a unique hot code pattern to a binary code pattern, so as to facilitate normal identification of the subsequent module.
Further, the method of this embodiment may further include: and converting the code pattern of the scheduling result from the one-hot code pattern into a binary code pattern, and sending the binary code pattern to a back-stage module of the scheduler.
Specifically, when the code pattern of the scheduling result is converted from the one-hot code pattern to the binary code pattern, the conversion may be performed by the correspondence between the determined binary code and each of the different one-hot codes. Specifically, according to the corresponding relationship between the binary code and each of the different unique hot codes, the binary code corresponding to the unique hot code of the scheduling result is determined as the binary code of the scheduling result. The correspondence relationship can be as shown in the aforementioned table 2.
In a specific example, if the scheduling result is 0000000100, the corresponding binary code is 0011 as shown in table 2.
And step 104, the safety check module judges whether the scheduling result meets the requirement of the one-hot code type, and judges that the scheduler fails under the condition that the scheduling result does not meet the requirement of the one-hot code type.
In the foregoing description, it has been pointed out that the unique hot code pattern is that only one of all bits is 1, and the rest bits are 0, so that when determining whether the scheduling result meets the requirement of the unique hot code pattern, it can be determined that the bit value in the scheduling result is the bit of the target value, and if the bit number is 1, it is determined that the scheduling result meets the requirement of the unique hot code pattern; if the digit is not 1, the scheduling result is judged not to meet the requirement of the one-hot code type.
In a specific example, the target value is 1, if the scheduling result is 1001000001, the number of bits of the target value is 3, which is not 1, and this indicates that the scheduling result does not meet the requirement of the unique hot code pattern, and if the scheduling result is 1000000000, the number of bits of the target value is 1, which indicates that the scheduling result meets the unique hot code pattern.
In addition, the chip is also provided with an interrupt interface, the interrupt interface is connected with a CPU in the chip, and after the scheduler is judged to have a fault, the present embodiment may pull up the potential of the interrupt interface, so that the CPU receives the high potential of the interrupt interface and knows that the scheduler has a fault based on the high potential.
Taking 10 scheduling units mentioned in the foregoing embodiment as an example, the number of possible scheduling results is 10, since the number of bits of the corresponding unique hot code is 10, after passing through the scheduler, regardless of whether the scheduler fails, the scheduling result that the scheduler may output may be 10 powers of 2, that is, 1024, and for each scheduling, the correct scheduling result may be only 1, but 10 possible scheduling results satisfying the unique hot code pattern (that is, the unique hot code of each scheduling unit) may exist, where the unique hot code pattern is satisfied, but the incorrect scheduling result is 9.
Since the present embodiment determines whether a fault occurs according to the coincidence of the one-hot code pattern, 9 scheduling results with errors cannot be identified in the present embodiment, and therefore, for this embodiment, the method of the present embodiment diagnoses that the coverage rate is 1- (9/1024) =99.12%.
According to the above calculation procedure, for different numbers of scheduling results N, there are the following diagnostic coverage of table 3:
TABLE 3
For the scheduler, the single point failure indicator SPFM = DC, while the requirements for SPFM for different ASIL classes are shown in table 4 below.
TABLE 4
| ASIL | B | C | D |
| SPFM | 90％ | 97％ | 99％ |
Therefore, the scheme of the embodiment can meet the requirements of ASIL-B and even ASIL-D grades in most scenarios, and for the scenario that is not met (for example, when N = 5), it is only necessary to increase the diagnostic coverage of other modules of the chip (for example, the diagnostic coverage of a cache using ECC can easily reach 99%) to meet the corresponding ASIL grade requirement.
In the technical scheme of the embodiment of the application, a signal buffer and a safety check module are arranged in a chip, the input end of the signal buffer is connected with the output end of a scheduler, and the output end of the signal buffer is connected with the safety check module. When the method is specifically executed, the scheduler acquires the binary codes of each scheduling unit in the scheduling table, converts the binary code patterns of each scheduling unit into the unique hot code patterns to obtain the unique hot codes of each scheduling unit, then carries out scheduling operation on the basis of the unique hot codes of each scheduling unit and preset scheduling operation logic to obtain a scheduling result of the scheduling, caches the scheduling result through a signal buffer, and sends the scheduling result to the safety check module, the safety check module checks whether the scheduling result meets the requirement of the unique hot code patterns, and under the condition that the requirement of the unique hot code patterns is not met, the scheduler is judged to have faults. By utilizing the higher identifiability of the one-hot code type, after the scheduler has a problem, the scheduling result does not conform to the one-hot code type generally, and the scheduling result with the non-one-hot code type can be identified more quickly, so that the failure of the scheduler can be determined more quickly. Meanwhile, the method can be realized by only increasing the signal buffer and the safety check module, thereby avoiding multiplying chip resources occupied by the scheduler module and reducing the development difficulty.
Example two
Fig. 3 is a schematic structural diagram of a chip scheduler fault determination apparatus according to a second embodiment of the present application. The chip scheduler fault judgment device provided by the embodiment of the application can execute the chip scheduler fault judgment method provided by any embodiment of the application, and has the corresponding functional modules and beneficial effects of the execution method. The apparatus may be implemented in a software and/or hardware manner, and as shown in fig. 3, the apparatus for determining a fault of a chip scheduler specifically includes: a code pattern conversion module 301, a scheduling module 302, a cache module 303, and a security judgment module 304.
Wherein the content of the first and second substances,
the code pattern conversion module is used for the scheduler to obtain the binary codes of all the scheduling units in the scheduling table and convert the binary code patterns of all the scheduling units into one-hot code patterns to obtain the one-hot codes of all the scheduling units;
the scheduling module is used for the scheduler to perform scheduling operation based on the one-hot codes of the scheduling units and the preset scheduling operation logic to obtain a scheduling result of the scheduling;
the buffer module is used for sending the scheduling result to the safety inspection module after the scheduler buffers the scheduling result through the signal buffer;
and the safety judgment module is used for judging whether the scheduling result meets the requirement of the one-hot code type or not by the safety check module and judging that the scheduler breaks down under the condition that the scheduling result does not meet the requirement of the one-hot code type.
In this embodiment, a signal buffer and a security check module are disposed in the chip, an input end of the signal buffer is connected to an output end of the scheduler, and an output end of the signal buffer is connected to the security check module. When the scheduling method is specifically executed, a scheduler acquires the binary code of each scheduling unit in a scheduling table, converts the binary code pattern of each scheduling unit into a unique hot code pattern to obtain the unique hot code of each scheduling unit, then carries out scheduling operation on the basis of the unique hot code of each scheduling unit and preset scheduling operation logic to obtain a scheduling result of the scheduling, caches the scheduling result through a signal buffer, and sends the scheduling result to a safety check module, the safety check module checks whether the scheduling result meets the requirement of the unique hot code pattern, and under the condition that the scheduling result does not meet the requirement of the unique hot code pattern, the scheduler is judged to have a fault. By utilizing the higher identifiability of the one-hot code type, after the scheduler has a problem, the scheduling result does not conform to the one-hot code type generally, and the scheduling result with the non-one-hot code type can be identified more quickly, so that the failure of the scheduler can be determined more quickly. Meanwhile, the method can be realized by only adding the signal buffer and the safety check module, thereby avoiding multiplying chip resources occupied by the scheduler module and reducing the development difficulty.
Further, the safety judgment module comprises:
the digit judging unit is used for judging the digit of which the bit value is the target value in the scheduling result;
the first requirement judging unit is used for judging that the scheduling result meets the requirement of the one-hot code pattern if the digit is 1;
and the second requirement judging unit is used for judging that the scheduling result does not meet the requirement of the one-hot code pattern if the digit is not 1.
Furthermore, an interrupt interface is also arranged in the chip and is connected with a CPU in the chip;
the device still includes:
and the interrupt module is used for raising the electric potential of the interrupt interface so that the CPU receives the high electric potential of the interrupt interface and knows that the scheduler has a fault based on the high electric potential.
Further, the code pattern conversion module includes:
and the binary code acquisition unit is used for acquiring the unit number of the scheduling units in the scheduling table, and performing binary coding on each scheduling unit according to the unit number to obtain the binary code corresponding to each scheduling unit.
Further, the code pattern conversion module includes:
the unique hot code bit number determining unit is used for determining the bit number of the unique hot code according to the unit number and corresponding the binary code of each scheduling unit with each different unique hot code;
and the unique hot code corresponding unit is used for determining the unique hot code corresponding to the binary code of the scheduling unit as the unique hot code of the scheduling unit for any scheduling unit.
Furthermore, the output end of the signal buffer is also connected with a rear-stage module of the scheduler;
the device still includes:
and the decoding module is used for converting the code pattern of the scheduling result from the one-hot code pattern into a binary code pattern and sending the binary code pattern to the rear-stage module of the scheduler.
Further, the decoding module includes:
and the decoding unit is used for determining the binary codes corresponding to the one-hot codes of the scheduling results as the binary codes of the scheduling results according to the corresponding relation between the binary codes and different one-hot codes.
EXAMPLE III
Fig. 4 is a schematic structural diagram of an electronic device according to a third embodiment of the present application, as shown in fig. 4, the electronic device includes a processor 410, a memory 420, an input device 430, and an output device 440; the number of the processors 410 in the electronic device may be one or more, and one processor 410 is taken as an example in fig. 4; the processor 410, the memory 420, the input device 430 and the output device 440 in the electronic apparatus may be connected by a bus or other means, and the bus connection is exemplified in fig. 4.
The memory 420 is a computer-readable storage medium, and can be used for storing software programs, computer-executable programs, and modules, such as program instructions/modules corresponding to the method for upgrading a gateway or routing data in the embodiment of the present application (for example, the device for determining a fault of a chip scheduler specifically includes a code pattern conversion module 301, a scheduling module 302, a cache module 303, and a security determination module 304). The processor 410 executes software programs, instructions and modules stored in the memory 420 to execute various functional applications and data processing of the electronic device, that is, to implement the above-described chip scheduler fault determination method.
That is, the scheduler acquires the binary codes of each scheduling unit in the scheduling table, converts the binary code patterns of each scheduling unit into unique hot code patterns, and obtains the unique hot codes of each scheduling unit;
the scheduler performs scheduling operation based on the one-hot codes of the scheduling units and preset scheduling operation logic to obtain a scheduling result of the scheduling;
the scheduler sends the scheduling result to the safety check module after caching the scheduling result by the signal buffer;
the safety check module judges whether the scheduling result meets the requirement of the one-hot code type or not, and judges that the scheduler fails under the condition that the scheduling result does not meet the requirement of the one-hot code type.
The memory 420 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the terminal, and the like. Further, the memory 420 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some examples, the memory 420 can further include memory located remotely from the processor 410, which can be connected to electronic devices through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
Example four
A fourth embodiment of the present application further provides a storage medium containing computer-executable instructions, where the computer-executable instructions are used to execute a method for determining a failure of a chip scheduler when executed by a computer processor, and the method includes:
the scheduler acquires the binary codes of all scheduling units in the scheduling table, converts the binary code patterns of all scheduling units into unique hot code patterns and obtains the unique hot codes of all scheduling units;
the scheduler performs scheduling operation based on the one-hot codes of the scheduling units and preset scheduling operation logic to obtain a scheduling result of the scheduling;
the scheduler sends the scheduling result to the safety check module after caching the scheduling result by the signal buffer;
the safety check module judges whether the scheduling result meets the requirement of the one-hot code type or not, and judges that the scheduler fails under the condition that the scheduling result does not meet the requirement of the one-hot code type.
Of course, the storage medium including the computer-executable instructions provided in the embodiments of the present application is not limited to the above method operations, and may also execute the relevant operations in the method for determining a fault of a chip scheduler provided in any embodiment of the present application.
From the above description of the embodiments, it is obvious for those skilled in the art that the present application can be implemented by software and necessary general hardware, and certainly can be implemented by hardware, but the former is a better embodiment in many cases. Based on such understanding, the technical solutions of the present application or portions contributing to the prior art may be embodied in the form of a software product, which may be stored in a computer-readable storage medium, such as a floppy disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a FLASH Memory (FLASH), a hard disk or an optical disk of a computer, and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device) to execute the methods of the embodiments of the present application.
It should be noted that, in the embodiment of the above search apparatus, each included unit and module are merely divided according to functional logic, but are not limited to the above division as long as the corresponding functions can be implemented; in addition, specific names of the functional units are only used for distinguishing one functional unit from another, and are not used for limiting the protection scope of the present application.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present application and the technical principles employed. Those skilled in the art will appreciate that the present application is not limited to the particular embodiments described herein, and that various obvious changes, rearrangements and substitutions will now become apparent to those skilled in the art without departing from the scope of the application. Therefore, although the present application has been described in more detail with reference to the above embodiments, the present application is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present application, and the scope of the present application is determined by the scope of the appended claims.
Claims (10)
1. A chip dispatcher fault judgment method is characterized in that a signal buffer is arranged in a chip, the input end of the signal buffer is connected with the output end of the dispatcher, and the output end of the signal buffer is connected with a safety inspection module;
the chip scheduler fault judgment method comprises the following steps:
the scheduler acquires the binary codes of all scheduling units in the scheduling table, converts the binary code patterns of all scheduling units into unique hot code patterns and obtains the unique hot codes of all scheduling units;
the scheduler performs scheduling operation based on the one-hot codes of the scheduling units and preset scheduling operation logic to obtain a scheduling result of the scheduling;
the scheduler sends the scheduling result to the safety check module after caching the scheduling result through the signal buffer;
and the safety check module judges whether the scheduling result meets the requirement of the one-hot code type or not, and judges that the scheduler breaks down under the condition that the scheduling result does not meet the requirement of the one-hot code type.
2. The method of claim 1, wherein the determining, by the security check module, whether the scheduling result meets requirements of a one-hot code pattern comprises:
judging the digit of which the bit value is a target value in the scheduling result, and if the digit is 1, judging that the scheduling result meets the requirement of the one-hot code type;
and if the digit is not 1, judging that the scheduling result does not meet the requirement of the one-hot code type.
3. The method according to claim 1, wherein an interrupt interface is further provided in the chip, and the interrupt interface is connected with a CPU in the chip;
after the scheduler is judged to have a fault, the method further comprises:
and pulling up the electric potential of the interrupt interface so that the CPU receives the high electric potential of the interrupt interface and knows that the scheduler has a fault based on the high electric potential.
4. The method of claim 1, wherein the obtaining, by the scheduler, the binary code of each scheduling unit in the schedule table comprises:
and acquiring the unit number of the scheduling units in the scheduling table, and performing binary coding on each scheduling unit according to the unit number to obtain the binary coding corresponding to each scheduling unit.
5. The method of claim 4, wherein converting the binary code pattern of each scheduling unit into a unique hot code pattern to obtain a unique hot code of each scheduling unit comprises:
determining the number of the bits of the one-hot codes according to the number of the units, and corresponding the binary codes of each scheduling unit with each different one-hot code;
for any scheduling unit, determining the one-hot code corresponding to the binary code of the scheduling unit as the one-hot code of the scheduling unit.
6. The method of claim 5, wherein the output of the signal buffer is further connected to a subsequent module of the scheduler;
the method further comprises the following steps:
and converting the code pattern of the scheduling result from the one-hot code pattern into a binary code pattern, and sending the binary code pattern to a later-stage module of the scheduler.
7. The method of claim 6, wherein converting the pattern of the scheduling result from a one-hot pattern to a binary pattern comprises:
and determining the binary code corresponding to the one-hot code of the scheduling result as the binary code of the scheduling result according to the corresponding relation between the binary code and each different one-hot code.
8. The chip scheduler fault judgment device is characterized in that a signal buffer is arranged in a chip, the input end of the signal buffer is connected with the output end of the scheduler, and the output end of the signal buffer is connected with a safety check module;
the chip scheduler fault judgment device comprises:
the code pattern conversion module is used for acquiring the binary codes of all scheduling units in the scheduling table by the scheduler, and converting the binary code patterns of all scheduling units into unique hot code patterns to obtain the unique hot codes of all scheduling units;
the scheduling module is used for the scheduler to perform scheduling operation based on the one-hot codes of the scheduling units and preset scheduling operation logic to obtain a scheduling result of the scheduling;
the buffer module is used for sending the scheduling result to the safety check module after the scheduler buffers the scheduling result through the signal buffer;
and the safety judgment module is used for judging whether the scheduling result meets the requirement of the one-hot code type or not by the safety check module and judging that the scheduler breaks down under the condition that the scheduling result does not meet the requirement of the one-hot code type.
9. An electronic device, comprising:
one or more processors;
a storage device for storing one or more programs,
when executed by the one or more processors, cause the one or more processors to implement the chip scheduler fault diagnosis method of any of claims 1-7.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the method for chip scheduler fault diagnosis according to any one of claims 1-7.
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