CN115379561B - Target terminal positioning method, system, electronic equipment and storage medium - Google Patents
Target terminal positioning method, system, electronic equipment and storage medium Download PDFInfo
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Abstract
The invention relates to the field of communication, and provides a target terminal positioning method, a target terminal positioning system, electronic equipment and a storage medium, wherein the method comprises the following steps: processing the wireless data sampled by each cell based on a digital logic chip to obtain a target signal of each cell; synchronizing each cell and determining cell system frame information of each cell; processing the target signal of each cell in real time based on the digital logic chip to obtain target control information, and processing the target signal of each cell in non-real time based on the digital logic chip to obtain a non-real time processing result; and positioning a target terminal based on the microprocessor chip, the cell system frame information, the target control information and the non-real-time processing result of each cell. The target terminal positioning method provided by the invention combines real-time processing and non-real-time processing, balances processing capacity and processing resources, combines the coordination processing of a digital logic chip and a microprocessor chip, and improves the expansibility.
Description
Technical Field
The present invention relates to the field of communications, and in particular, to a method, a system, an electronic device, and a storage medium for locating a target terminal.
Background
Most of the existing LTE passive positioning methods are single-cell passive positioning methods, so that the processing capacity of passive positioning is limited. Meanwhile, in the expansion process, if a single-cell passive positioning method is used, processing resources need to be multiplied, which results in poor expansibility.
Disclosure of Invention
The invention provides a target terminal positioning method, a target terminal positioning system, electronic equipment and a storage medium, and aims to improve expansibility while balancing processing capacity and processing resources.
In a first aspect, the present invention provides a target terminal positioning method, including:
processing the wireless data sampled by each cell based on a digital logic chip to obtain a target signal of each cell;
synchronizing each cell and determining cell system frame information of each cell;
processing the target signal of each cell in real time based on the digital logic chip to obtain target control information, and processing the target signal of each cell in non-real time based on the digital logic chip to obtain a non-real time processing result;
and positioning a target terminal based on the microprocessor chip, the cell system frame information, the target control information and the non-real-time processing result of each cell.
In one embodiment, the processing the target signal of each cell in real time based on the digital logic chip to obtain target control information includes:
and carrying out real-time blind detection processing on the control channel data in the target signal of each cell through the digital logic chip to obtain target system control information and target user control information of each cell.
After the target signal of each cell is processed in real time based on the digital logic chip to obtain target control information, the method further comprises the following steps:
transmitting target system control information and target user control information of each cell to the microprocessor chip;
and transmitting the system frame information and the subframe information where the target system control information of each cell is to the microprocessor chip.
The non-real-time processing of the target signal of each cell based on the digital logic chip to obtain a non-real-time processing result comprises:
and performing non-real-time processing on the service channel data in the target signal of each cell through the digital logic chip so as to synchronize the service channel data of each cell to the memory chip according to the synchronized cell system frame information of each cell.
The method for positioning the target terminal based on the microprocessor chip and the cell system frame information, the target control information and the non-real-time processing result of each cell comprises the following steps:
based on the microprocessor chip and the cell system frame information, the target system control information and the target user control information of each cell, reading out the service channel data of the target user of each cell from the memory chip;
analyzing and decoding the service channel data of the target user of each cell based on the digital logic chip to obtain service decoding information of the target user of each cell;
and analyzing the service decoding information of the target user of each cell based on the microprocessor chip, and positioning the target terminal of the target user of each cell.
The processing of the wireless data sampled by each cell based on the digital logic chip to obtain the target signal of each cell comprises:
sampling wireless data of each cell based on a digital-to-analog converter;
performing time domain to frequency domain conversion processing on the wireless data sampled by each cell based on the digital logic chip to obtain frequency domain data of each cell;
performing frequency offset compensation on the frequency domain data of each cell based on the digital logic chip to obtain frequency domain data after frequency offset compensation of each cell;
and performing inter-cell parallel-serial conversion on the frequency domain data after the frequency offset compensation of each cell based on the digital logic chip to obtain a target signal of each cell.
The synchronizing each cell and determining the cell system frame information of each cell includes:
carrying out coarse synchronization of a main synchronization signal and an auxiliary synchronization signal on each cell according to the cell code of each cell, carrying out fine synchronization on a broadcast signal in each cell according to the cell code of each cell, and determining cell system frame information of each cell;
wherein the coarse synchronization and the fine synchronization are performed periodically in a loop.
In a second aspect, the present invention provides a target terminal positioning system, including:
the first processing module is used for processing the wireless data sampled by each cell based on the digital logic chip to obtain a target signal of each cell;
the synchronization module is used for synchronizing each cell and determining cell system frame information of each cell;
the second processing module is used for processing the target signal of each cell in real time based on the digital logic chip to obtain target control information, and processing the target signal of each cell in non-real time based on the digital logic chip to obtain a non-real time processing result;
and the positioning module is used for positioning the target terminal based on the microprocessor chip and the cell system frame information, the target control information and the non-real-time processing result of each cell.
In a third aspect, the present invention further provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the processor executes the computer program, the target terminal positioning method of the first aspect is implemented.
In a fourth aspect, the present invention also provides a non-transitory computer-readable storage medium comprising a computer program which, when executed by the processor, implements the target terminal positioning method of the first aspect.
In a fifth aspect, the present invention further provides a computer program product, where the computer program product includes a computer program, and when the computer program is executed by the processor, the target terminal positioning method in the first aspect is implemented.
The target terminal positioning method, the system, the electronic equipment and the storage medium provided by the invention process the wireless data sampled by each cell based on the digital logic chip to obtain the target signal of each cell; synchronizing each cell and determining cell system frame information of each cell; processing the target signal of each cell in real time based on the digital logic chip to obtain target control information, and processing the target signal of each cell in non-real time based on the digital logic chip to obtain a non-real time processing result; and positioning a target terminal based on the microprocessor chip, the cell system frame information, the target control information and the non-real-time processing result of each cell.
The process of passive positioning for each cell combines real-time processing and non-real-time processing, thereby balancing the processing power and processing resources of passive positioning. Meanwhile, the digital logic chip and the microprocessor chip are combined for coordination processing, so that the expansibility of passive positioning is improved.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings needed for the description of the embodiment or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic flowchart of a target terminal positioning method provided in the present invention;
FIG. 2 is a schematic overall flow chart of a target terminal positioning method provided by the present invention;
FIG. 3 is a schematic diagram illustrating a flow of controlling read/write storage of a memory chip according to the present invention;
FIG. 4 is a schematic structural diagram of a target terminal positioning system provided in the present invention;
fig. 5 is a schematic structural diagram of an electronic device provided in the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiments of the present invention provide an embodiment of a target terminal positioning method, and it should be noted that although a logical sequence is shown in a flow chart, in some data, the steps shown or described may be completed in a sequence different from that here.
In the embodiment of the present invention, a target terminal positioning system is taken as an example of an execution subject, referring to fig. 1, fig. 1 is a flowchart illustrating a target terminal positioning method provided by the present invention. The target terminal positioning method provided by the embodiment of the invention comprises the following steps:
103, processing the target signal of each cell in real time based on the digital logic chip to obtain target control information, and processing the target signal of each cell in non-real time based on the digital logic chip to obtain a non-real time processing result;
and step 104, positioning a target terminal based on the microprocessor chip and the cell system frame information, the target control information and the non-real-time processing result of each cell.
It should be noted that, in the embodiment of the present invention, the target terminal positioning system adopts a system architecture of a digital logic chip and a microprocessor chip, and a memory chip is externally connected.
Further, the digital logic chip may be, but is not limited to, a Programmable Array logic (FPGA) chip and a 74LS160 logic chip, and the FPGA chip is taken as an example of the digital logic chip according to the embodiment of the present invention. The microprocessor chip includes, but is not limited to, an AMD processor chip (Advanced Micro Devices) and an ARM processor chip (Advanced RISC Machine), and the embodiment of the present invention takes the ARM chip as an example of the microprocessor chip. The Memory chip includes, but is not limited to, a DDR (Double Data Rate Synchronous Dynamic Random Access Memory) chip and a RAM (Random Access Memory), and in the embodiment of the present invention, the DDR chip is taken as an example of the Memory chip.
It can be further understood that the target terminal positioning system in the embodiment of the present invention adopts an architecture of an FPGA chip and an ARM chip, and a DDR chip is externally attached. The signal processing part with large calculation amount in the target terminal positioning system is realized through the interior of an FPGA chip, and the scheduling control is realized through the interior of an ARM chip.
Further, the target terminal positioning system in the embodiment of the present invention at least includes 16 receiving antennas, and generally, each cell corresponds to 2 receiving antennas. That is to say, the target terminal positioning system in the embodiment of the present invention may receive wireless data of at least 8 cells at the same time. In the embodiment of the present invention, 16 receiving antennas are taken as an example, that is, wireless data of 8 channels of cells can be received simultaneously. Further, each Analog-to-digital converter (ADC) is responsible for sampling radio frequency signals of 2 cells, i.e. 4 ADCs are required to be configured in the target terminal positioning system.
Further, after the target terminal positioning system receives the air wireless data (wireless data or air interface data) of each cell in 8 cells, the FPGA chip processes the received wireless data of each cell in 8 cells to obtain a target signal of each cell.
It should be noted that, in LTE (long term evolution), one system frame is 10ms (milliseconds), and one system frame includes 10 subframes, that is, each subframe is 1ms.
Further, the target terminal positioning system synchronizes each cell in 8 cells, and determines cell system frame information of each cell, where the cell system frame information includes initial system frame information and system frame length of each cell, where the system frame length is determined by a synchronization period, and if the synchronization period is 2s (seconds), the synchronization period includes 200 system frames, that is, the system frame length is 200. Further, the target terminal positioning system determines the ending system frame information of each cell according to the starting system frame information and the system frame length of each cell. In an embodiment, the starting system frame information of the cell C1 is C1_ St =100, the synchronization period is 2s, and the terminating system frame information of the cell C1 is C1_ St =299.
Further, after the target terminal positioning system synchronizes each cell in 8 cells, that is, after the start system frame information, the end system frame information and the subframe information of each cell in 8 cells are synchronized, the FPGA chip divides the target signal of each cell in 8 cells into two paths of signals, and the two paths of signals are respectively marked as a first path of signal and a second path of signal.
Further, the FPGA chip processes the first path of signal of each cell in 8 cells in real time, and processes the second path of signal of each cell in 8 cells in non-real time, so as to obtain a real-time processing result and a non-real-time processing result of the target signal of each cell.
Further, the ARM chip locates a target terminal of a suspected target according to the initial system frame information, the termination system frame information and the subframe information of each cell in 8 cells, and the real-time processing result and the non-real-time processing result of the target signal of each cell.
The target terminal positioning method provided by the invention processes the wireless data sampled by each cell based on a digital logic chip to obtain a target signal of each cell; synchronizing each cell and determining cell system frame information of each cell; processing the target signal of each cell in real time based on the digital logic chip to obtain target control information, and processing the target signal of each cell in non-real time based on the digital logic chip to obtain a non-real time processing result; and positioning a target terminal based on the microprocessor chip, the cell system frame information, the target control information and the non-real-time processing result of each cell.
The process of passive positioning for each cell combines real-time processing and non-real-time processing, thereby balancing the processing power and processing resources of passive positioning. Meanwhile, the digital logic chip and the microprocessor chip are combined for coordination processing, so that the expansibility of passive positioning is improved.
Further, referring to fig. 2 and fig. 3, fig. 2 is a schematic overall flow chart of the target terminal positioning method provided by the present invention, and fig. 3 is a schematic flow chart of the memory chip read-write storage control provided by the present invention. The embodiment of the present invention is specifically analyzed with reference to fig. 2 and 3:
further, the processing of the wireless data sampled by each cell based on the digital logic chip described in step 101 to obtain a target signal of each cell includes:
sampling wireless data of each cell based on a digital-to-analog converter;
performing time domain to frequency domain processing on the wireless data sampled by each cell based on the digital logic chip to obtain frequency domain data of each cell;
performing frequency offset compensation on the frequency domain data of each cell based on the digital logic chip to obtain frequency domain data after frequency offset compensation of each cell;
and performing inter-cell parallel-serial conversion on the frequency domain data after the frequency offset compensation of each cell based on the digital logic chip to obtain a target signal of each cell.
Specifically, the target terminal positioning system receives wireless data of each cell in 8 channels of cells through 16 receiving antennas, performs radio frequency receiving processing on the wireless data of each cell in the 8 channels of cells, and samples the wireless data of each cell in the 8 channels of cells through 4 analog-to-digital converters (digital-to-analog converters) ADC.
Further, 4 digital-to-analog converters (ADC) transmit the wireless data sampled by each cell in the 8 paths of cells to the FPGA chip. Because the wireless data of each cell in the 8 channels of cells sampled by the digital-to-analog converter ADC is a time domain signal, and the LTE signal is processed in the frequency domain, the FPGA chip needs to perform time domain to frequency domain processing on the wireless data of each cell in the 8 channels of cells sampled by the digital-to-analog converter ADC, so as to obtain the frequency domain data of each cell in the 8 channels of cells.
Furthermore, the signals after time-frequency conversion need to be subjected to frequency offset compensation, and the clock offset of the crystal oscillator of the transceiver device is compensated, so that the quality of the received signals is improved, therefore, the frequency offset compensation is performed on the frequency domain data of each cell in 8 channels of cells by the FPGA chip, and the frequency domain data after the frequency offset compensation of each cell in 8 channels of cells is obtained. Furthermore, the FPGA chip performs inter-cell parallel-serial conversion on the frequency domain data after the frequency offset compensation of each cell in the 8 paths of cells, and outputs a target signal of each cell in the 8 paths of cells.
In an embodiment, the 8 cells are respectively denoted as cell 1, cell 2, cell 3 to cell 8, that is, the FPGA chip performs inter-cell parallel-to-serial conversion on the frequency domain data after the frequency offset compensation of each cell in the 8 cells, and serially outputs the target signals of the cell 1, the cell 2, the cell 3 to the cell 8.
The embodiment of the invention carries out time domain to frequency domain processing, frequency offset compensation and parallel-serial conversion on the wireless data sampled by each cell through the FPGA chip, thereby accurately obtaining the target signal of each cell and improving the expansibility of passive positioning.
Further, the step 102 of synchronizing each cell and determining the cell system frame information of each cell includes:
performing coarse synchronization of a main synchronization signal and an auxiliary synchronization signal on each cell according to the cell code of each cell, performing fine synchronization on a broadcast signal in each cell according to the cell code of each cell, and determining cell system frame information of each cell;
wherein the coarse synchronization and the fine synchronization are performed periodically in a loop.
Specifically, the FPGA chip sequentially searches for a cell code ID (Identity document) of each cell in the 8 cells.
In an embodiment, the FPGA chip sequentially searches for cell 1, cell 2 to cell 8 in 8 channels of cells to obtain cell code IDs of cell 1, cell 2 to cell 8.
Further, the FPGA chip performs cell search coarse Synchronization on each cell in the 8 cells according to the cell code ID of each cell in the 8 cells, where the cell search coarse Synchronization includes a Primary Synchronization Signal (PSS) and a Secondary Synchronization Signal (SSS). That is, the FPGA performs cell search coarse synchronization of the primary synchronization signal PSS and the secondary synchronization signal SSS for each cell in the 8 cells according to the cell code ID of each cell in the 8 cells.
Further, after the FPGA chip determines the cell code ID of each cell in the 8 channels of cells, fine synchronization in the cell is performed for capturing operation, demodulating operation, and decoding operation on a Broadcast signal (PBCH) in each cell in the 8 channels of cells, and cell system frame information in each cell in the 8 channels of cells can be determined through the fine synchronization in the cell, that is, initial system frame information, termination system frame information, and subframe information in each cell in the 8 channels of cells are determined.
Further, the two steps of cell search coarse synchronization and fine synchronization of the PBCH broadcast signal are periodically and cyclically executed, and synchronization of each cell in the 8-channel cell is maintained, that is, the cell search coarse synchronization and the fine synchronization of the PBCH broadcast signal are periodically executed, and a cycle execution period can be determined according to actual conditions, and generally, the cycle execution period is 4 seconds.
The embodiment of the invention periodically and circularly executes the cell search coarse synchronization and fine synchronization of each cell through the FPGA chip, thereby maintaining the synchronization of each cell.
Further, the processing, based on the digital logic chip, of the step 103 to perform real-time processing on the target signal of each cell to obtain target control information includes:
and carrying out real-time blind detection processing on the control channel data in the target signal of each cell through the digital logic chip to obtain target system control information and target user control information of each cell.
It should be noted that the target signal of each cell includes Control Channel data (PDCCH) and traffic Channel data, where the traffic Channel data can be divided into Uplink traffic Channel data (PUSCH) and Downlink traffic Channel data (PDSCH).
Specifically, after each cell is synchronized, the FPGA chip performs real-time processing, that is, blind detection processing, on control channel data in a target signal of each cell, and at the same time, non-real-time processing needs to be performed on traffic channel data in the target signal of each cell.
Further, for real-time processing: the FPGA chip carries out real-time blind detection processing on the Control channel data PDCCH of each cell in the 8 paths of cells to obtain target Control Information (DCI) of each cell in the 8 paths of cells, wherein the target Control Information comprises target system Control Information and target user Control Information.
Therefore, it can be understood that the FPGA chip performs a real-time blind detection process on the PDCCH of the control channel data of each cell in the 8 cells to obtain target system control information and target user control information of each cell in the 8 cells, specifically: the processing period of the real-time processing is 1ms (taking a subframe as a unit), the control channel data PDCCH of each cell in the 8 paths of cells is transmitted to the PDCCH control channel blind detection module by the FPGA chip, the real-time blind detection processing is carried out for 1ms in the minimum blind detection period, a blind detection result is obtained, and the blind detection result is target system control information and target user control information of each cell in the 8 paths of cells.
It should be noted that the PDCCH real-time blind detection process is a general existing processing method, and the internal process thereof is not described in detail. The method includes the steps that two types of target control information DCI are obtained through real-time blind detection, the first type is downlink control information DCI, and downlink traffic channel data PDSCH of a terminal (User Equipment) can be scheduled through the downlink control information DCI. The second type is uplink control information DCI, which may schedule uplink traffic channel data PUSCH of the terminal UE.
Further, after the target signal of each cell is processed in real time based on the digital logic chip to obtain the target control information, the method further includes:
transmitting target system control information and target user control information of each cell to the microprocessor chip;
and transmitting the system frame information and the subframe information where the target system control information of each cell is to the microprocessor chip.
Specifically, after the target system control information and the target user control information of each cell in the 8 paths of cells are obtained through the real-time blind detection processing of the FPGA chip, the target system control information and the target user control information of each cell in the 8 paths of cells are transmitted to the ARM chip through a First-in First-out (FIFO) memory. Meanwhile, the FPGA chip also needs to transmit the system frame information and the subframe information where the target system control information of each cell in the 8 channels of cells is located to the ARM chip through the first-in first-out memory.
Further, the non-real-time processing of the target signal of each cell based on the digital logic chip described in step 103 to obtain a non-real-time processing result includes:
and performing non-real-time processing on the service channel data in the target signal of each cell through the digital logic chip so as to synchronize the service channel data of each cell to the memory chip according to the cell system frame information synchronized by each cell.
Specifically, for non-real-time processing: the FPGA chip carries out non-real-time processing on service channel data (uplink service channel data PUSCH and downlink service channel data PDSCH) of each cell in the 8-channel cells so as to store the service channel data (uplink service channel data PUSCH and downlink service channel data PDSCH) of each cell in the 8-channel cells to the DDR chip according to cell system frame information after each cell is synchronized, and the method specifically comprises the following steps: the processing period of non-real-time processing is 2s, a period starting mark with the period of 2s is marked, and uplink service channel data PUSCH and downlink service channel data PDSCH of 8 channels of cells are stored in the plug-in DDR chip according to cell system frame information (starting system frame information, terminating system frame information and subframe information) after each cell is synchronized by taking 2s as a period.
The embodiment of the invention combines real-time processing and non-real-time processing, thereby balancing the processing capability and processing resources of passive positioning. Meanwhile, the digital logic chip and the microprocessor chip are combined for coordination processing, so that the expansibility of passive positioning is improved.
Further, the step 104 of locating the target terminal based on the microprocessor chip and the cell system frame information, the target control information and the non-real-time processing result of each cell includes:
based on the microprocessor chip and the cell system frame information, the target system control information and the target user control information of each cell, reading out the service channel data of the target user of each cell in the memory chip;
analyzing and decoding the service channel data of the target user of each cell based on the digital logic chip to obtain service decoding information of the target user of each cell;
and analyzing the service decoding information of the target user of each cell based on the microprocessor chip, and positioning the target terminal of the target user of each cell.
Specifically, the ARM chip analyzes the target system control information of each cell in the 8-way cell, and determines the system frame information and the subframe information where the target system control information of each cell in the 8-way cell is located. Further, the ARM chip determines the real system frame information of the target system control information of each cell in the 8-way cell by combining the initial system frame information of each cell in the 8-way cell according to the system frame information where the target system control information of each cell in the 8-way cell is located.
In an embodiment, in the process of controlling the read/write memory of the DDR chip, when the DDR chip is written every 2 second period, the cell C1 (cell numbers C1 to C8) needs to notify the ARM chip of the system frame number of the 2 second start time, and other cells need to do the same operation. The LTE sfn is a cyclic cycle of 0 to 1023 cycles, the 2 second starting sfn is C1_ St =100, and 2 seconds =200 sfn (1 sfn =10 ms) can be stored, so that the current sfn stored in 2 seconds is necessarily 100 to 299 sfn, i.e. the terminating sfn information of the cell C1 is 299. If it is detected that the system frame C1_ Sx =236 in which the target system control information C1_ DCI of the cell C1 is located, the actual system frame information of the target system control information C1_ DCI of the cell C1 is C1_ deta _ S = C1_ Sx-C1_ St =236-100=136.
Further, the ARM chip analyzes the target user control information of each cell in the 8 paths of cells to obtain target user uplink control information and target user downlink control information. Further, the ARM chip transmits the target user uplink control information and the target user downlink control information of each cell in the 8-channel cells, and the real system frame information and the subframe information of the target system control information of each cell in the 8-channel cells to the FPGA chip.
Furthermore, the FPGA chip reads uplink service channel data PUSCH corresponding to the target user uplink control information of each cell in the 8 channels of cells from the memory chip according to the real system frame information and subframe information of the target system control information of each cell in the 8 channels of cells.
Furthermore, the FPGA chip analyzes and decodes the uplink service channel data PUSCH of each cell in the 8-channel cells to obtain service decoding information of the uplink service channel data PUSCH of each cell and a target user in the 8-channel cells.
Further, the AFPGA chip reads downlink traffic channel data PDSCH corresponding to the target user downlink control information of each cell in the 8-way cell from the memory chip according to the real system frame information and subframe information of the target system control information of each cell in the 8-way cell.
Furthermore, the FPGA chip analyzes and decodes the PDSCH of the downlink traffic channel data of each cell in the 8-channel cells to obtain the traffic decoding information of the PDSCH of the downlink traffic channel data of each cell and a target user in the 8-channel cells.
Furthermore, the FPGA chip transmits the service decoding information of the PUSCH of the uplink service channel data and the service decoding information of the PDSCH of the downlink service channel data of each cell in the 8 channels of cells to the ARM chip.
Further, the ARM chip identifies service decoding information of uplink service channel data PUSCH of each cell in the 8-channel cells, and determines a target Network identifier RNTI (Radio Network Temporary identifier) of the suspected target. Further, the ARM chip analyzes the target network identifier (RNTI) of the suspected target according to the service decoding information of the downlink service channel data PDSCH of each cell in the 8 paths of cells, and locates the target terminal of the suspected target of each cell in the 8 paths of cells.
The embodiment of the invention combines the digital logic chip and the microprocessor chip to carry out coordination processing, thereby improving the expansibility of passive positioning.
Further, the following describes the target terminal positioning system provided by the present invention, and the target terminal positioning system and the target terminal positioning method may be referred to in correspondence.
As shown in fig. 4, fig. 4 is a schematic structural diagram of a target terminal positioning system provided by the present invention, and the target terminal positioning system includes:
a first processing module 401, configured to process the wireless data sampled by each cell based on a digital logic chip, to obtain a target signal of each cell;
a synchronization module 402, configured to synchronize each cell and determine cell system frame information of each cell;
a second processing module 403, configured to perform real-time processing on the target signal of each cell based on the digital logic chip to obtain target control information, and perform non-real-time processing on the target signal of each cell based on the digital logic chip to obtain a non-real-time processing result;
and a positioning module 404, configured to position a target terminal based on the microprocessor chip and the cell system frame information, the target control information, and the non-real-time processing result of each cell.
Further, the first processing module 201 is further configured to:
sampling wireless data of each cell based on a digital-to-analog converter;
performing time domain to frequency domain processing on the wireless data sampled by each cell based on the digital logic chip to obtain frequency domain data of each cell;
performing frequency offset compensation on the frequency domain data of each cell based on the digital logic chip to obtain frequency domain data after frequency offset compensation of each cell;
and performing inter-cell parallel-serial conversion on the frequency domain data after the frequency offset compensation of each cell based on the digital logic chip to obtain a target signal of each cell.
Further, the synchronization module 202 is further configured to:
carrying out coarse synchronization of a main synchronization signal and an auxiliary synchronization signal on each cell according to the cell code of each cell, carrying out fine synchronization on a broadcast signal in each cell according to the cell code of each cell, and determining cell system frame information of each cell;
wherein the coarse synchronization and the fine synchronization are performed periodically in a loop.
Further, the second processing module 203 is further configured to:
and carrying out real-time blind detection processing on the control channel data in the target signal of each cell through the digital logic chip to obtain target system control information and target user control information of each cell.
Further, the target terminal positioning system is further configured to:
transmitting target system control information and target user control information of each cell to the microprocessor chip;
and transmitting the system frame information and the subframe information where the target system control information of each cell is to the microprocessor chip.
Further, the second processing module 203 is further configured to:
and performing non-real-time processing on the service channel data in the target signal of each cell through the digital logic chip so as to synchronize the service channel data of each cell to the memory chip according to the cell system frame information synchronized by each cell.
Further, the positioning module 204 is further configured to:
based on the microprocessor chip and the cell system frame information, the target system control information and the target user control information of each cell, reading out the service channel data of the target user of each cell from the memory chip;
analyzing and decoding the service channel data of the target user of each cell based on the digital logic chip to obtain service decoding information of the target user of each cell;
and analyzing the service decoding information of the target user of each cell based on the microprocessor chip, and positioning the target terminal of the target user of each cell.
The specific embodiment of the target terminal positioning system provided by the invention is basically the same as the embodiments of the target terminal positioning method, and the details are not repeated herein.
Fig. 5 illustrates a physical structure diagram of an electronic device, and as shown in fig. 5, the electronic device may include: a processor (processor) 510, a communication Interface (Communications Interface) 520, a memory (memory) 530 and a communication bus 540, wherein the processor 510, the communication Interface 520 and the memory 530 communicate with each other via the communication bus 540. Processor 510 may invoke logic instructions in memory 530 to perform a target terminal location method comprising:
processing the wireless data sampled by each cell based on a digital logic chip to obtain a target signal of each cell;
synchronizing each cell and determining cell system frame information of each cell;
processing the target signal of each cell in real time based on the digital logic chip to obtain target control information, and processing the target signal of each cell in non-real time based on the digital logic chip to obtain a non-real time processing result;
and positioning a target terminal based on the microprocessor chip, the cell system frame information, the target control information and the non-real-time processing result of each cell.
Furthermore, the logic instructions in the memory 530 may be implemented in the form of software functional units and stored in a computer readable storage medium when the software functional units are sold or used as independent products. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
In another aspect, the present invention also provides a computer program product, the computer program product comprising a computer program stored on a non-transitory computer-readable storage medium, the computer program comprising program instructions, which when executed by a computer, enable the computer to perform the target terminal positioning method provided by the above methods, the method comprising:
processing the wireless data sampled by each cell based on a digital logic chip to obtain a target signal of each cell;
synchronizing each cell and determining cell system frame information of each cell;
processing the target signal of each cell in real time based on the digital logic chip to obtain target control information, and processing the target signal of each cell in non-real time based on the digital logic chip to obtain a non-real time processing result;
and positioning a target terminal based on the microprocessor chip, the cell system frame information, the target control information and the non-real-time processing result of each cell.
In yet another aspect, the present invention also provides a non-transitory computer readable storage medium, on which a computer program is stored, the computer program being implemented by a processor to perform the target terminal positioning method provided in the above aspects, the method comprising:
processing the wireless data sampled by each cell based on a digital logic chip to obtain a target signal of each cell;
synchronizing each cell and determining cell system frame information of each cell;
processing the target signal of each cell in real time based on the digital logic chip to obtain target control information, and processing the target signal of each cell in non-real time based on the digital logic chip to obtain a non-real time processing result;
and positioning a target terminal based on the microprocessor chip, the cell system frame information, the target control information and the non-real-time processing result of each cell.
The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (9)
1. A target terminal positioning method is characterized by comprising the following steps:
processing the wireless data sampled by each cell based on a digital logic chip to obtain a target signal of each cell;
synchronizing each cell and determining cell system frame information of each cell;
processing the target signal of each cell in real time based on the digital logic chip to obtain target control information, and processing the target signal of each cell in non-real time based on the digital logic chip to obtain a non-real time processing result;
positioning a target terminal based on the microprocessor chip and the cell system frame information, the target control information and the non-real-time processing result of each cell;
wherein, the positioning of the target terminal based on the microprocessor chip and the cell system frame information, the target control information and the non-real-time processing result of each cell comprises:
based on the microprocessor chip and the cell system frame information, the target system control information and the target user control information of each cell, reading out the service channel data of the target user of each cell from the memory chip;
analyzing and decoding the service channel data of the target user of each cell based on the digital logic chip to obtain service decoding information of the target user of each cell;
and analyzing the service decoding information of the target user of each cell based on the microprocessor chip, and positioning the target terminal of the target user of each cell.
2. The method of claim 1, wherein the processing the target signal of each cell in real time based on the digital logic chip to obtain target control information comprises:
and carrying out real-time blind detection processing on the control channel data in the target signal of each cell through the digital logic chip to obtain target system control information and target user control information of each cell.
3. The method of claim 2, wherein after the target signal of each cell is processed in real time based on the digital logic chip to obtain target control information, the method further comprises:
transmitting target system control information and target user control information of each cell to the microprocessor chip;
and transmitting the system frame information and the subframe information where the target system control information of each cell is to the microprocessor chip.
4. The method according to claim 1, wherein the performing non-real-time processing on the target signal of each cell based on the digital logic chip to obtain a non-real-time processing result comprises:
and performing non-real-time processing on the service channel data in the target signal of each cell through the digital logic chip so as to synchronize the service channel data of each cell to the memory chip according to the synchronized cell system frame information of each cell.
5. The method of claim 1, wherein the processing the wireless data sampled by each cell based on the digital logic chip to obtain the target signal of each cell comprises:
sampling wireless data of each cell based on a digital-to-analog converter;
performing time domain to frequency domain processing on the wireless data sampled by each cell based on the digital logic chip to obtain frequency domain data of each cell;
performing frequency offset compensation on the frequency domain data of each cell based on the digital logic chip to obtain frequency domain data after frequency offset compensation of each cell;
and performing parallel-serial conversion between cells on the frequency domain data after the frequency offset compensation of each cell based on the digital logic chip to obtain a target signal of each cell.
6. The method according to any of claims 1 to 5, wherein the synchronizing each cell and determining the cell system frame information of each cell comprises:
performing coarse synchronization of a main synchronization signal and an auxiliary synchronization signal on each cell according to the cell code of each cell, performing fine synchronization on a broadcast signal in each cell according to the cell code of each cell, and determining cell system frame information of each cell;
wherein the coarse synchronization and the fine synchronization are performed periodically in a loop.
7. A target terminal location system, comprising:
the first processing module is used for processing the wireless data sampled by each cell based on the digital logic chip to obtain a target signal of each cell;
the synchronization module is used for synchronizing each cell and determining cell system frame information of each cell;
the second processing module is used for processing the target signal of each cell in real time based on the digital logic chip to obtain target control information, and processing the target signal of each cell in non-real time based on the digital logic chip to obtain a non-real time processing result;
the positioning module is used for positioning a target terminal based on the microprocessor chip, and cell system frame information, target control information and non-real-time processing results of each cell;
the positioning module is further configured to:
based on the microprocessor chip and the cell system frame information, the target system control information and the target user control information of each cell, reading out the service channel data of the target user of each cell in the memory chip;
analyzing and decoding the service channel data of the target user of each cell based on the digital logic chip to obtain service decoding information of the target user of each cell;
and analyzing the service decoding information of the target user of each cell based on the microprocessor chip, and positioning the target terminal of the target user of each cell.
8. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the target terminal positioning method according to any one of claims 1 to 6 when executing the computer program.
9. A non-transitory computer readable storage medium comprising a computer program, wherein the computer program when executed by a processor implements the target terminal positioning method of any one of claims 1 to 6.
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