CN115378387A - Filter element, method of designing filter element, method of manufacturing filter element, and electronic apparatus - Google Patents
Filter element, method of designing filter element, method of manufacturing filter element, and electronic apparatus Download PDFInfo
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- CN115378387A CN115378387A CN202110536297.3A CN202110536297A CN115378387A CN 115378387 A CN115378387 A CN 115378387A CN 202110536297 A CN202110536297 A CN 202110536297A CN 115378387 A CN115378387 A CN 115378387A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H1/00—Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
- H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H1/00—Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
- H03H2001/0021—Constructional details
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Abstract
The invention discloses a filter element, a design method and a manufacturing method thereof, and an electronic device. The filter element comprises an upper wafer, a lower wafer and a substrate, wherein a metal ground plane is arranged below the lower wafer and is connected with the ground plane of the substrate; the lower wafer has a plurality of resonator elements thereon, wherein the plurality of resonator elements form a plurality of parallel filters. The technical scheme of the invention can reduce parasitic inductance, improve insertion loss and realize miniaturization.
Description
Technical Field
The present invention relates to the field of filter technology, and in particular, to a filter element, a design method and a manufacturing method thereof, and an electronic device.
Background
In a high power filter element (e.g., a base station filter), in order to improve power capacity, a plurality of dies (i.e., unpackaged semiconductor structures on which devices such as resonators are formed by a semiconductor processing process, also referred to as die) are generally connected in parallel, and then input/output impedance is matched to a specific impedance through a matching network. The dice are generally distributed on the substrate, and then connected in parallel on the substrate by bonding wires or bumps (bumps). In this technique, each die has a parasitic inductance to ground, which will degrade the out-of-band rejection of the filter; when a plurality of dice are distributed on the substrate, the input and the output of each die need to be connected through a specific connecting line, and the matching mode has larger limitation, so that the resistance loss and the matching loss are increased, and the insertion loss is deteriorated; in addition, the packaging path for packaging multiple die is complicated, and due to the requirement of the spacing between multiple die, the overall size of the chip is large, and the packaging cost and the manufacturing cost are both increased.
Disclosure of Invention
In view of the above, the present invention provides a filter element having reduced parasitic inductance, improved insertion loss, and reduced size, a method of designing the filter element, a method of manufacturing the filter element, and an electronic device.
The invention provides a filter element in a first aspect, which comprises an upper wafer, a lower wafer and a substrate, wherein a metal ground plane is arranged below the lower wafer and is connected with the ground plane of the substrate; the lower wafer has a plurality of resonator elements thereon, wherein the plurality of resonator elements form a plurality of parallel filters.
Optionally, a ground pad, an input pad, and an output pad are disposed above the upper wafer, the input ends of the plurality of parallel filters are connected to the input pad, and the output ends of the plurality of parallel filters are connected to the output pad.
Optionally, the ground pad, the input pad, and the output pad are connected to the substrate by a plurality of bonding wires.
Optionally, the number of the plurality of parallel filters is 2 to 4.
A second aspect of the present invention provides a method for designing a filter element, where the filter element includes an upper wafer, a lower wafer, and a substrate, the method including: and a metal ground plane is arranged below the lower wafer and is connected with the ground plane of the substrate, and a plurality of resonator elements are arranged above the lower wafer, wherein the plurality of resonator elements form a plurality of parallel filters so as to reduce parasitic inductance, improve insertion loss and realize miniaturization.
Optionally, the method further comprises: the upper portion of the upper wafer is provided with a grounding bonding pad, an input bonding pad and an output bonding pad, the input ends of the parallel filters are connected to the input bonding pad, and the output ends of the parallel filters are connected to the output bonding pad.
Optionally, the method further comprises: and arranging a plurality of ground through holes in the upper wafer and the lower wafer in parallel, wherein the ground inductance in the filter element is connected to the metal ground plane through the ground through hole in the lower wafer or connected to the ground pad through the ground through hole in the upper wafer.
Optionally, a top surface of the upper wafer is spaced from a bottom surface of the lower wafer by a distance of 50 to 300 microns, or alternatively, by 80 to 200 microns.
Optionally, the method further comprises: and connecting the grounding bonding pad, the input bonding pad and the output bonding pad with the substrate through a plurality of bonding wires.
Optionally, the number of the plurality of parallel filters is 2 to 4.
A third aspect of the present invention provides a method for manufacturing a filter element, the filter element including an upper wafer, a lower wafer, and a substrate, the method including: forming a metal ground plane below the lower wafer and a plurality of resonator elements above the lower wafer, wherein the metal ground plane is connected with the ground plane of the substrate, and the plurality of resonator elements constitute a plurality of parallel filters; forming a grounding bonding pad, an input bonding pad and an output bonding pad above the upper wafer, wherein the input ends of the plurality of parallel filters are connected to the input bonding pad, and the output ends of the plurality of parallel filters are connected to the output bonding pad; and connecting the grounding bonding pad, the input bonding pad and the output bonding pad with the substrate through a plurality of bonding wires.
Optionally, the number of the plurality of parallel filters is 2 to 4.
A fourth aspect of the invention provides an electronic device comprising any one of the filter elements of the invention.
According to the technical scheme of the invention, a plurality of die are combined in a circuit parallel connection mode, and the invention has the following advantages: (1) The parallel inductance value of the combined parasitic inductance is reduced, the parasitic inductance is improved, and the out-of-band rejection is also improved; (2) In the prior art, a plurality of discrete filters are respectively provided with an input inductor and an output inductor, and the combined die is connected at the input end and the output end through only one inductor, so that the matching mode of the invention reduces the resistance loss and the matching loss, and improves the insertion loss; (3) The packaging process can be simplified after the plurality of die are combined, the plurality of die do not need to be respectively attached to the substrate and then more bonding lead connections are carried out, scribing procedures can be reduced, scribing channel space is saved, miniaturization of devices is facilitated, the utilization rate of chips is improved, and production cost is reduced; (4) The method avoids the adoption of a plurality of discrete non-uniform die at different positions on the wafer (due to the non-uniformity of manufacturing, the performances of the plurality of die are not completely consistent), thereby avoiding the non-uniformity of the whole power distribution and transmission characteristics, and further avoiding the deterioration of indexes such as power capacity, transmission insertion loss echo and the like.
Drawings
For purposes of illustration and not limitation, the present invention will now be described in accordance with its preferred embodiments, particularly with reference to the accompanying drawings, wherein:
FIG. 1 is a prior art topological block diagram of a filter element;
FIG. 2 is a topological structure diagram of filter1 in FIG. 1;
fig. 3 is a schematic diagram of a prior art package of a filter element including two die;
FIG. 4 is a schematic cross-sectional view at AA' of FIG. 3;
fig. 5 is a schematic diagram of a package of a filter element incorporating two die according to an embodiment of the present invention;
FIG. 6 is a topology of two discrete die filter elements of the prior art;
FIG. 7 is a topology of two combined die filter elements according to an embodiment of the present invention;
FIG. 8 is a comparison of out-of-band rejection for filter elements of the prior art and embodiments of the present invention;
fig. 9 is a graph comparing the insertion loss of filter elements of the prior art and the embodiment of the present invention;
fig. 10 is a schematic diagram of a package of a filter element incorporating three die according to an embodiment of the present invention;
fig. 11 is a schematic diagram of a package of a filter element incorporating four die according to an embodiment of the present invention.
Detailed Description
Embodiments of the present invention are described in detail below by combining multiple discrete die from the prior art to improve device performance and simplify the manufacturing process.
Fig. 1 is a topology of a prior art filter element. In the prior art, a plurality of dice, for example, N dice, are connected in parallel, 1 filter is manufactured on each die, and then matching is performed to impedance of a specific value (for example, 50 ohms) through a matching network, where the dice are connected through input and output inductors, where N is greater than or equal to 2.
Fig. 2 is a topology structure diagram of the filter1 in fig. 1. All the ground inductances L1 to L4 are connected to ground via a common parasitic inductance L5, which parasitic inductance L5 is present on die or on the substrate or both. In the filter element according to the embodiment of the present invention, the number of resonators and ground inductances and the connection method thereof are not limited to the configuration shown in fig. 2.
Fig. 3 is a schematic diagram of a prior art package of a filter element including two die.
In the above figure, two die are respectively connected to the input and output ends of the substrate through the input and output inductors, the ground end is connected to the ground end of the substrate through the bonding wire, and the bonding wire exists between the two die, so that a certain distance is required. The input and output are connected through a long inductor, so that on one hand, the resistance loss is increased, and on the other hand, an extra matching network is needed to eliminate the effect of the inductor, so that the matching loss is additionally caused.
FIG. 4 is a schematic cross-sectional view at AA' of FIG. 3. As shown, a plurality of ground vias are disposed in parallel in the upper wafer and the lower wafer, so that the ground inductance can be reduced. The ground inductance in the filter element may be connected to the metal ground plane through a ground via in the lower wafer or to a ground pad through a ground via in the upper wafer.
The die thickness actually affects the equivalent inductance of the ground via. In the filter element according to the embodiment of the present invention, the distance between the top surface of the upper wafer and the bottom surface of the lower wafer (i.e., the thickness of die) may be 50 to 300 micrometers, or 80 to 200 micrometers.
Fig. 5 is a schematic diagram of a package of a filter element according to an embodiment of the invention. As shown in the figure, the two die in fig. 3 are merged to ensure that the two die are connected in parallel in the circuit topology, that is, the input end and the output end of the two die are respectively converged to two nodes. Then, through the arrangement and distribution of the bonding pads on the top of the upper wafer, the grounded area above the upper wafer is connected to form a grounded bonding pad, and the grounded bonding pad is connected with the integral metal ground plane below the lower wafer. The input and output pads of the upper wafer are connected to the substrates IN and OUT, respectively, by a plurality of bonding wires. As can be seen from fig. 5, on one hand, the present embodiment combines multiple dice, thereby avoiding the dicing process between multiple discrete dice and simplifying the manufacturing process; in addition, each die needs to be adhered to the substrate and then connected through a plurality of bonding wires, and only one die needs to be adhered to the substrate in the embodiment, and the connection of the bonding wires is simplified. In addition, the occupied area of the multiple stereo die is larger, and compared with the scheme of one die in the embodiment, at least the middle spacing (generally, the spacing is at least 50um wide) and the area provided with the middle bonding wire are increased, so that the chip size of the embodiment can be smaller.
Fig. 6 shows the topology of two discrete die filter elements of the prior art. Wherein the input-output inductance is also included in the above figure. Fig. 7 shows the topology of two combined die filter elements according to an embodiment of the present invention. As can be seen from fig. 6 and 7, on one hand, the parasitic inductance to ground L5 in fig. 7 is connected in parallel, and the parasitic to ground is halved, and on the other hand, the matching manner of input and output changes, fig. 7 shows that two dice are directly connected and then matched through one input and output inductance, and fig. 6 shows that each die is connected through an inductance and then converged to a node.
Fig. 8 is a graph comparing out-of-band rejection for filter elements of the prior art and embodiments of the present invention. Where the solid line is the merged die version of the embodiments of the present invention and the dashed line is the discrete die version of the prior art, it can be seen that there is a significant improvement in out-of-band rejection as the parasitic inductance is reduced.
Fig. 9 is a graph showing a comparison of insertion loss of filter elements according to the prior art and the embodiment of the present invention. Where the solid line is the scheme of merging die of the embodiment of the present invention and the dotted line is the scheme of discrete die of the prior art, it can be seen that when the matching mode is changed due to the merging die, the insertion loss is also improved.
In the filter element combining multiple die according to other embodiments of the present invention, the number of parallel filters included in the filter element may also be three, four, or more, and the inventive principle is the same. Fig. 10 is a schematic diagram of a package of a filter element incorporating three die according to an embodiment of the present invention;
fig. 11 is a schematic diagram of a package of a filter element incorporating four die according to an embodiment of the present invention. The dotted line is the boundary between the dice.
According to the design method of the filter element provided by the embodiment of the invention, the filter element comprises an upper wafer, a lower wafer and a substrate, and the design method comprises the following steps: a metal ground plane is arranged below the lower wafer and connected with the ground plane of the substrate, and a plurality of resonator elements are arranged above the lower wafer and form a plurality of parallel filters, so that parasitic inductance is reduced, insertion loss is improved, and miniaturization is realized. Wherein the number of the plurality of parallel filters is 2 to 4.
Optionally, the method further comprises: and a grounding bonding pad, an input bonding pad and an output bonding pad are arranged above the upper wafer, the input ends of the parallel filters are connected to the input bonding pad, and the output ends of the parallel filters are connected to the output bonding pad.
Optionally, the method further comprises: the ground pad, the input pad, and the output pad are connected to the substrate by a plurality of bonding wires.
According to a manufacturing method of a filter element according to an embodiment of the present invention, the filter element includes an upper wafer, a lower wafer, and a substrate, the manufacturing method includes: forming a metal ground plane below the lower wafer and forming a plurality of resonator elements above the lower wafer, wherein the metal ground plane is connected with the ground plane of the substrate, and the plurality of resonator elements form a plurality of parallel filters; forming a grounding bonding pad, an input bonding pad and an output bonding pad above the upper wafer, wherein the input ends of the plurality of parallel filters are connected to the input bonding pad, and the output ends of the plurality of parallel filters are connected to the output bonding pad; the ground pad, the input pad, and the output pad are connected to the substrate by a plurality of bonding wires. Wherein the number of the plurality of parallel filters is 2 to 4.
In the embodiment of the present invention, combining multiple dice in parallel circuit and rearranging the bonding pads above the upper wafer have at least the following advantages: (1) The parallel inductance value of the combined parasitic inductance is reduced, the parasitic inductance is improved, and the out-of-band rejection is also improved; (2) In the prior art, a plurality of discrete filters are respectively provided with an input inductor and an output inductor, and the combined die is connected at the input end and the output end through only one inductor, so that the matching mode of the invention reduces the resistance loss and the matching loss, and improves the insertion loss; (3) The packaging process can be simplified after the plurality of die are combined, the plurality of die do not need to be respectively attached to the substrate and then more bonding lead connections are carried out, scribing procedures can be reduced, scribing channel space is saved, miniaturization of devices is facilitated, the utilization rate of chips is improved, and production cost is reduced; (4) The method avoids the adoption of a plurality of discrete non-uniform die at different positions on the wafer (due to the non-uniformity of manufacturing, the performances of the plurality of die are not completely consistent), thereby avoiding the non-uniformity of the whole power distribution and transmission characteristics, and further avoiding the deterioration of indexes such as power capacity, transmission insertion loss echo and the like.
The above-described embodiments should not be construed as limiting the scope of the invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions can occur, depending on design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (13)
1. A filter element includes an upper wafer, a lower wafer and a substrate,
a metal ground plane is arranged below the lower wafer and connected with the ground plane of the substrate;
the lower wafer has a plurality of resonator elements thereon, wherein the plurality of resonator elements form a plurality of parallel filters.
2. The filter element of claim 1, wherein the upper wafer has a ground pad, an input pad, and an output pad thereon, wherein the input terminals of the plurality of parallel filters are connected to the input pad, and wherein the output terminals of the plurality of parallel filters are connected to the output pad.
3. The filter element of claim 2, wherein the ground pad, input pad, and output pad are connected to the substrate by a plurality of bonding wires.
4. The filter element of claim 1, wherein the plurality of parallel filters is 2 to 4 in number.
5. A method for designing a filter element, the filter element including an upper wafer, a lower wafer, and a substrate, the method comprising:
and a metal ground plane is arranged below the lower wafer and is connected with the ground plane of the substrate, and a plurality of resonator elements are arranged above the lower wafer and form a plurality of parallel filters so as to reduce parasitic inductance, improve insertion loss and realize miniaturization.
6. The method of designing a filter element according to claim 5, further comprising: the upper portion of the upper wafer is provided with a grounding bonding pad, an input bonding pad and an output bonding pad, the input ends of the parallel filters are connected to the input bonding pad, and the output ends of the parallel filters are connected to the output bonding pad.
7. The method of designing a filter element according to claim 6, further comprising: and arranging a plurality of ground through holes in the upper wafer and the lower wafer in parallel, wherein the ground inductance in the filter element is connected to the metal ground plane through the ground through hole in the lower wafer or connected to the ground pad through the ground through hole in the upper wafer.
8. The method of claim 5, wherein a distance between the top surface of the upper wafer and the bottom surface of the lower wafer is 50 to 300 micrometers, or 80 to 200 micrometers.
9. The method of designing a filter element according to claim 5, further comprising: and connecting the grounding bonding pad, the input bonding pad and the output bonding pad with the substrate through a plurality of bonding wires.
10. The method of claim 5, wherein the number of the plurality of parallel filters is 2 to 4.
11. A method of manufacturing a filter element including an upper wafer, a lower wafer, and a substrate, comprising:
forming a metal ground plane below the lower wafer and a plurality of resonator elements above the lower wafer, wherein the metal ground plane is connected with the ground plane of the substrate, and the plurality of resonator elements constitute a plurality of parallel filters;
forming a grounding bonding pad, an input bonding pad and an output bonding pad above the upper wafer, wherein the input ends of the plurality of parallel filters are connected to the input bonding pad, and the output ends of the plurality of parallel filters are connected to the output bonding pad;
and connecting the grounding bonding pad, the input bonding pad and the output bonding pad with the substrate through a plurality of bonding wires.
12. The method of manufacturing a filter element according to claim 11, wherein the number of the plurality of parallel filters is 2 to 4.
13. An electronic device, characterized in that it comprises a filter element according to any one of claims 1 to 4.
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CN202110536297.3A CN115378387A (en) | 2021-05-17 | 2021-05-17 | Filter element, method of designing filter element, method of manufacturing filter element, and electronic apparatus |
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CN202110536297.3A CN115378387A (en) | 2021-05-17 | 2021-05-17 | Filter element, method of designing filter element, method of manufacturing filter element, and electronic apparatus |
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