CN115376452B

CN115376452B - Array substrate, preparation method thereof and display device

Info

Publication number: CN115376452B
Application number: CN202211154011.6A
Authority: CN
Inventors: 袁鑫; 周秀峰; 康报虹
Original assignee: HKC Co Ltd
Current assignee: HKC Co Ltd
Priority date: 2022-09-21
Filing date: 2022-09-21
Publication date: 2023-09-26
Anticipated expiration: 2042-09-21
Also published as: CN115376452A

Abstract

The application relates to an array substrate, a preparation method thereof and a display device, wherein the array substrate comprises a substrate, a plurality of sub-pixels and a plurality of signal lines, the sub-pixels and the signal lines are arranged on the substrate and distributed in an array mode, the signal lines comprise data lines, power supply voltage lines, scanning lines and light-emitting switch signal lines, the data lines extend along a first direction, the scanning lines and the light-emitting switch signal lines extend along a second direction, the scanning lines extend along the first direction so as to limit corresponding sub-pixels, the first direction is intersected with the second direction, the signal lines further comprise initialization voltage lines extending along the first direction, the initialization voltage lines, the data lines and the power supply voltage lines are arranged in a stacked mode, and the initialization voltage lines or the data lines are arranged in a bridging mode at positions which are same with the scanning lines and the light-emitting switch signal lines and intersect. The array substrate can reduce the occupied space of the signal lines, improve the aperture ratio, or increase the line width of the signal lines and reduce the load of the signal lines under the condition of keeping the occupied space unchanged.

Description

Array substrate, preparation method thereof and display device

Technical Field

The application relates to the technical field of display, in particular to an array substrate, a preparation method thereof and a display device.

Background

In the pixel circuit, at least signal lines including a Scan line (Scan), a Data line (Data), a light-emitting switch signal line (Emit), a power supply voltage line (VDD), an initialization voltage line (Vint) and the like need to be provided for a single pixel, and these signal lines occupy a large amount of pixel wiring space, so that the requirement of higher aperture ratio and better display effect proposed by the market cannot be met.

Disclosure of Invention

The application aims to provide an array substrate, a preparation method thereof and a display device, which can reduce the occupied space of signal lines, improve the aperture ratio, or increase the line width of the signal lines and reduce the load of the signal lines under the condition of keeping the occupied space unchanged.

In a first aspect, an embodiment of the present application provides an array substrate, including a substrate, a plurality of sub-pixels located on the substrate and distributed in an array, and a plurality of signal lines, where the plurality of signal lines include a data line extending along a first direction, a power supply voltage line, and a scan line and a light-emitting switch signal line extending along a second direction, so as to define corresponding sub-pixels, the first direction intersects the second direction, the plurality of signal lines further include an initialization voltage line extending along the first direction, the initialization voltage line, the data line, and the power supply voltage line are stacked, and the initialization voltage line or the data line is disposed in a bridging manner at a position on the same layer as and intersecting the scan line and the light-emitting switch signal line.

In one possible implementation manner, the array substrate further comprises a modulation layer, a buffer layer, a first metal layer, an interlayer insulating layer, a second metal layer, a passivation layer and an electrode layer which are sequentially formed on the substrate; the initialization voltage line comprises a first part of signal lines and a second part of signal lines which are connected in a staggered manner along a first direction, wherein the orthographic projection of the second part of signal lines on the substrate is overlapped with the orthographic projection of the scanning lines and the light-emitting switch signal lines on the substrate, and the orthographic projection of the second part of signal lines, the data lines and the power voltage lines on the substrate are not overlapped with each other; wherein, the data line is positioned on the modulation layer; the first part of signal lines, the scanning lines and the light-emitting switch signal lines are positioned on the first metal layer; the power voltage line is positioned on the second metal layer; the second part of signal wires are positioned on the second metal layer and are electrically connected with the first part of signal wires through the via holes positioned on the interlayer insulating layer; alternatively, the second portion of the signal line is located in the electrode layer and is electrically connected to the first portion of the signal line through a via hole penetrating the film layer between the passivation layer and the interlayer insulating layer.

In one possible implementation manner, the array substrate further comprises a modulation layer, a buffer layer, a first metal layer, an interlayer insulating layer, a second metal layer, a passivation layer and an electrode layer which are sequentially formed on the substrate; the data line comprises a third part of signal lines and a fourth part of signal lines which are connected in a staggered manner along the first direction, and the orthographic projection of the fourth part of signal lines on the substrate is overlapped with the orthographic projection of the scanning lines and the light-emitting switch signal lines on the substrate, and is not overlapped with the orthographic projections of the initialization voltage line and the power supply voltage line on the substrate; wherein the initialization voltage line is positioned on the modulation layer; the third part of signal lines, the scanning lines and the light-emitting switch signal lines are positioned on the first metal layer; the power voltage line is positioned on the second metal layer; the fourth part of signal wires are positioned on the second metal layer and are electrically connected with the third part of signal wires through the via holes positioned on the interlayer insulating layer; alternatively, the fourth portion of the signal line is located in the electrode layer and is electrically connected to the third portion of the signal line through a via hole penetrating the film layer between the passivation layer and the interlayer insulating layer.

In one possible embodiment, the initialization voltage line, the data line, and the power supply voltage line are stacked on one side of the corresponding sub-pixel.

In one possible embodiment, the line width of the power supply voltage line is greater than the line width of the data line and the line width of the initialization voltage line.

In a second aspect, an embodiment of the present application provides a method for manufacturing an array substrate as described above, including: providing a substrate; forming a plurality of sub-pixels and a plurality of signal lines distributed in an array on a substrate, wherein the plurality of signal lines comprise data lines, power supply voltage lines, initialization voltage lines, scanning lines and light-emitting switch signal lines which extend along a first direction and a second direction, so as to limit corresponding sub-pixels, and the first direction and the second direction are intersected; wherein the initialization voltage line, the data line and the power voltage line are arranged in a stacked manner, and the initialization voltage line or the data line is arranged in a bridging manner at a position which is in the same layer as and intersects with the scan line and the light emitting switch signal line.

In one possible embodiment, forming a plurality of signal lines on a substrate base includes: depositing a modulation layer on a substrate base plate, and etching to form a data line; forming a buffer layer on the modulation layer; forming a patterned first metal layer on the buffer layer, and etching to form a first part of signal lines, scanning lines and light-emitting switch signal lines of the initialization voltage lines; forming a patterned interlayer insulating layer on the first metal layer, the interlayer insulating layer including a via hole corresponding to an end of the first portion of the signal line; forming a second metal layer on the interlayer insulating layer by deposition, etching to form second part of signal lines of a power supply voltage line and an initialization voltage line, wherein orthographic projection of the second part of signal lines on the substrate is overlapped with orthographic projections of the scanning line and the light-emitting switch signal line on the substrate, orthographic projections of the data line and the power supply voltage line on the substrate are not overlapped with each other, and the second part of signal lines are electrically connected with the first part of signal lines through the through holes; or depositing a second metal layer on the interlayer insulating layer, and etching to form a power supply voltage line; forming a patterned passivation layer on the second metal layer; and depositing an electrode layer on the passivation layer, etching to form a second part of signal line of the initialization voltage line, wherein the orthographic projection of the second part of signal line on the substrate is overlapped with the orthographic projection of the scanning line and the luminescent switch signal line on the substrate, and the orthographic projection of the second part of signal line and the orthographic projection of the data line and the power voltage line on the substrate are not overlapped, and the second part of signal line is electrically connected with the first part of signal line through a via hole penetrating through the passivation layer to a film layer between the interlayer insulating layers.

In one possible embodiment, forming a plurality of signal lines on a substrate base includes: depositing a modulation layer on a substrate base plate, and etching to form an initialization voltage line; forming a buffer layer on the modulation layer; forming a patterned first metal layer on the buffer layer, and etching to form a third part of signal lines, scanning lines and light-emitting switch signal lines of the data lines; forming a patterned interlayer insulating layer on the first metal layer, the interlayer insulating layer including a via hole corresponding to an end of the third portion of the signal line; forming a second metal layer on the interlayer insulating layer by deposition, etching to form a fourth part of signal lines of a power supply voltage line and a data line, wherein the orthographic projection of the fourth part of signal lines on the substrate is overlapped with the orthographic projection of the scanning line and the luminescent switch signal lines on the substrate, and is not overlapped with the orthographic projections of the initialization voltage line and the power supply voltage line on the substrate, and the fourth part of signal lines are electrically connected with the third part of signal lines through the through holes; or depositing a second metal layer on the interlayer insulating layer, and etching to form a power supply voltage line; forming a patterned passivation layer on the second metal layer; and depositing an electrode layer on the passivation layer, etching to form a fourth part of signal wires of the data wires, wherein the orthographic projection of the fourth part of signal wires on the substrate is overlapped with the orthographic projection of the scanning wires and the luminescent switch signal wires on the substrate, and the orthographic projections of the initialization voltage wires and the power voltage wires on the substrate are not overlapped with each other, and the fourth part of signal wires are electrically connected with the third part of signal wires through a via hole penetrating through the passivation layer to a film layer between the interlayer insulating layers.

In a second aspect, an embodiment of the present application provides a display apparatus, including: an array substrate as hereinbefore described.

According to the array substrate, the manufacturing method thereof and the display device provided by the embodiment of the application, the initialization voltage line, the data line and the power voltage line which extend along the first direction are arranged in a stacked manner, and the initialization voltage line or the data line is arranged in a bridging manner at the position which is in the same layer as the scanning line and the light-emitting switch signal line and is intersected with the scanning line and the light-emitting switch signal line, so that the occupied space of the signal line can be increased, the aperture ratio can be increased, or the line width of the signal line can be increased under the condition that the occupied space is kept unchanged, and the load of the signal line can be reduced.

Drawings

Features, advantages, and technical effects of exemplary embodiments of the present application will be described below with reference to the accompanying drawings. In the drawings, like parts are designated with like reference numerals. The drawings are not drawn to scale, but are merely for illustrating relative positional relationships, and the layer thicknesses of certain portions are exaggerated in order to facilitate understanding, and the layer thicknesses in the drawings do not represent the actual layer thickness relationships.

Fig. 1 is a schematic view showing a structure of an array substrate in the related art;

fig. 2 is a schematic structural diagram of an array substrate according to a first embodiment of the present application;

FIG. 3 shows a cross-section of FIG. 2 along the direction A-A;

FIG. 4 shows a cross-section of FIG. 2 along direction B-B;

fig. 5 is a schematic structural diagram of an array substrate according to a second embodiment of the present application;

FIG. 6 shows a cross-section of FIG. 5 along direction C-C;

fig. 7 is a schematic structural diagram of an array substrate according to a third embodiment of the present application;

FIG. 8 shows a cross-section of FIG. 7 along direction E-E;

FIG. 9 shows a cross-sectional view of FIG. 7 along direction F-F;

fig. 10 is a schematic structural diagram of an array substrate according to a fourth embodiment of the present application;

FIG. 11 shows a cross-sectional view of FIG. 10 along direction J-J;

fig. 12 is a schematic view showing the structure of another array substrate in the related art;

fig. 13 is a schematic structural diagram of an array substrate according to a fifth embodiment of the present application;

FIG. 14 shows a cross-sectional view of FIG. 13 along direction A-A;

FIG. 15 shows a cross-sectional view of FIG. 13 along direction B-B;

fig. 16 is a schematic structural diagram of an array substrate according to a sixth embodiment of the present application;

FIG. 17 shows a cross-sectional view of FIG. 16 along direction C-C;

fig. 18 is a schematic structural diagram of an array substrate according to a seventh embodiment of the present application;

FIG. 19 shows a cross-sectional view of FIG. 18 along direction E-E;

FIG. 20 shows a cross-sectional view of FIG. 18 along direction F-F;

fig. 21 is a schematic structural diagram of an array substrate according to an eighth embodiment of the present application;

Fig. 22 shows a cross-section of fig. 21 along direction J-J.

Reference numerals illustrate:

1. an array substrate; px, sub-pixels; x, a first direction; y, second direction;

10. a substrate base; 11. a modulation layer; 12. a buffer layer; 13. a first metal layer; 14. an interlayer insulating layer; 15. a second metal layer; 16. a passivation layer; 17. an electrode layer; H. a via hole;

D. a data line; d1, a third part of signal lines; d2, a fourth part of signal lines;

vdd, supply voltage line; s, scanning lines; an Emit, a light-emitting switch signal line;

vint, initializing voltage lines; vint1, first partial signal line; vint2, second partial signal line.

Detailed Description

Features and exemplary embodiments of various aspects of the application are described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the application. It will be apparent, however, to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the application by showing examples of the application. In the drawings and the following description, at least some well-known structures and techniques have not been shown in detail in order not to unnecessarily obscure the present application; also, the size of the region structures may be exaggerated for clarity. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

The application aims to provide an array substrate, a preparation method thereof and a display panel, which can reduce the occupied space of signal lines, improve the aperture ratio, or increase the line width of the signal lines and reduce the load of the signal lines under the condition of keeping the occupied space unchanged. The embodiments are described in detail below with reference to the accompanying drawings.

As shown in fig. 1, an array substrate in the related art includes a plurality of sub-pixels distributed in an array and various signal lines, wherein the data lines D and the power voltage lines Vdd are vertically arranged along a first direction X and are arranged on the same metal layer. The light-emitting switch signal line (Emit), the initialization voltage line (Vint) and the scanning line (Gate) are transversely arranged along the second direction Y and are arranged on the same metal layer, and each sub-pixel Px is located in a region formed by encircling the plurality of signal lines. Because the wiring has respective line width and line distance requirements, how to save wiring space and how to reduce the load of the signal lines becomes a difficult problem to be solved under the trend that the arrangement space of the signal lines is increasingly reduced.

First embodiment

Fig. 2 is a schematic structural diagram of an array substrate according to a first embodiment of the present application.

As shown in fig. 2, a first embodiment of the present application provides an array substrate 1, which includes a substrate 10, a plurality of sub-pixels Px disposed on the substrate 10 and distributed in an array, and a plurality of signal lines, wherein the plurality of signal lines include a data line D extending along a first direction X, a power voltage line Vdd, and a scan line S and a light-emitting switch signal line Emit extending along a second direction Y, so as to define corresponding sub-pixels Px, and the first direction X intersects the second direction Y. Alternatively, the substrate 10 is an insulating substrate such as a glass substrate.

The plurality of signal lines further include an initialization voltage line Vint extending along the first direction X, the initialization voltage line Vint, the data line D, and the power voltage line Vdd are stacked, and the initialization voltage line Vint is bridged at a position that is layered with and intersects the scan line S and the light emitting switch signal line Emit.

In this embodiment, the initialization voltage line Vint is changed from the original transverse arrangement along the second direction Y to the vertical arrangement along the first direction X, so that the wiring space of the signal line in the first direction X can be reduced; in addition, the initialization voltage line Vint, the data line D and the power voltage line Vdd are stacked, and the initialization voltage line Vint is bridged at a position which is in the same layer as and intersects the scanning line S and the light-emitting switch signal line Emit, so that the wiring space of the signal line in the second direction Y can be reduced, the wiring space of the signal line can be saved, and the pixel aperture ratio can be improved. Or under the condition of ensuring that the wiring space of the original signal wires is unchanged, the line width of each signal wire can be increased, and then the load of each signal wire is reduced.

In one example, the initialization voltage line Vint, the data line D, and the power supply voltage line Vdd, which are arranged in a stacked manner, are located at one side of the corresponding sub-pixel Px. Compared with the related art in which the data line D and the power supply voltage line Vdd extending in the first direction X are respectively located at both sides of the subpixel Px, the signal lines can be concentrated and stacked, and the wiring space of the signal line routing in the second direction is greatly reduced.

FIG. 3 shows a cross-section of FIG. 2 along the direction A-A; fig. 4 shows a cross-section of fig. 2 along direction B-B.

As shown in fig. 3 and 4, the array substrate 1 further includes a modulation layer 11, a buffer layer 12, a first metal layer 13, an interlayer insulating layer 14, a second metal layer 15, a passivation layer 16, and an electrode layer 17, which are sequentially formed on the substrate 10.

The initialization voltage line Vint includes a first portion of signal lines Vint1 and a second portion of signal lines Vint2 connected in a staggered manner along the first direction X, where the front projection of the second portion of signal lines Vint2 on the substrate 10 overlaps with the front projection of the scan line S and the light-emitting switch signal line Emit on the substrate 10, and does not overlap with the front projection of the data line D and the power voltage line Vdd on the substrate 10.

Wherein the data line D is located in the modulation layer 11; the first partial signal line Vint1, the scanning line S and the light-emitting switch signal line Emit are located in the first metal layer 13; the power supply voltage line Vdd is located at the second metal layer 15.

The second partial signal line Vint2 is located in the second metal layer 15 and is electrically connected to the first partial signal line Vint1 through the via hole H located in the interlayer insulating layer 14.

In one example, the first portion of the signal line Vint1 located in the first metal layer 13 is in an "L" type arrangement, one portion extends in the first direction X, and the other portion extends in the second direction Y; the end portion of the second partial signal line Vint2 located in the second metal layer 15 is aligned with the end portion of the first partial signal line Vint1 extending in the second direction Y and is electrically connected to each other through the via hole H located in the interlayer insulating layer 14, so that the initialization voltage line Vint is bridged at a position which is layered with and intersects the scan line S and the light emitting switch signal line Emit.

Alternatively, any one of the modulation layer 11, the first metal layer 13, the second metal layer 15, and the electrode layer 17 may be formed using any one metal such as molybdenum (Mo), titanium (Ti), niobium (Nb), tungsten (W), aluminum (Al), chromium (Cr), copper (Cu), and silver (Ag), or an alloy of at least two metals.

Alternatively, the interlayer insulating layer 14 may be made of, for example, silicon oxide (S _i O _X ) Or silicon nitride (S) _i N _X ) And (5) forming. The interlayer insulating layer 14 may be formed by laminating silicon oxide and silicon nitride.

In some embodiments, the line width of the power supply voltage line Vdd is greater than the line width of the data line D and the line width of the initialization voltage line Vint. Since the current flowing through the power supply voltage line Vdd is greater than the current flowing through the data line D or the initialization voltage line Vint, the line width of the power supply voltage line Vdd is greater than the line width of the data line D and the line width of the initialization voltage line Vint, and the load requirements of the corresponding signal lines are satisfied.

Second embodiment

Fig. 5 is a schematic structural diagram of an array substrate according to a second embodiment of the present application; fig. 6 shows a cross-section of fig. 5 along direction C-C.

As shown in fig. 5 and fig. 6, the array substrate 1 provided in the second embodiment of the present application is similar to the array substrate 1 provided in the first embodiment, and is different in that the initialization voltage line Vint is used for bridging the film layer where the second portion of the signal line Vint2 is located.

Specifically, the initialization voltage line Vint includes a first portion of signal lines Vint1 and a second portion of signal lines Vint2 that are connected to each other in the first direction X, and the front projection of the second portion of signal lines Vint2 on the substrate 10 overlaps with the front projection of the scan line S and the light-emitting switch signal line Emit on the substrate 10, and does not overlap with the front projections of the data line D and the power voltage line Vdd on the substrate 10.

The second partial signal line Vint2 is located in the electrode layer 17 and is electrically connected to the first partial signal line Vint1 through a via H penetrating the film layer between the passivation layer 16 and the interlayer insulating layer 14.

When the array substrate 1 is applied to an OLED display panel, the electrode layer 17 is an anode of a light emitting element. When the array substrate 1 is applied to a liquid crystal display panel, the electrode layer 17 is a pixel electrode.

In one example, the first portion of the signal line Vint1 located in the first metal layer 13 is in an "L" type arrangement, one portion extends in the first direction X, and the other portion extends in the second direction Y; the end portion of the second partial signal line Vint2 located in the electrode layer 17 is aligned with the end portion of the first partial signal line Vint1 extending in the second direction Y and is electrically connected to each other through a via hole H penetrating the film layer between the passivation layer 16 and the interlayer insulating layer 14, so that the initialization voltage line Vint is bridged at a position overlapping and intersecting the scan line S and the light emitting switch signal line Emit.

Third embodiment

Fig. 7 is a schematic structural diagram of an array substrate according to a third embodiment of the present application; FIG. 8 shows a cross-section of FIG. 7 along direction E-E; fig. 9 shows a cross-section of fig. 7 along direction F-F.

As shown in fig. 7 to 9, the array substrate 1 provided in the third embodiment of the present application is similar to the array substrate 1 provided in the first embodiment, and is different in that the initialization voltage line Vint and the data line D are interchanged in a film layer, and the data line D is bridged at a position which is in the same layer as and intersects with the scan line S and the light emitting switch signal line Emit.

Specifically, the array substrate 1 includes a modulation layer 11, a buffer layer 12, a first metal layer 13, an interlayer insulating layer 14, a second metal layer 15, a passivation layer 16, and an electrode layer 17, which are sequentially formed on a substrate 10.

The data line D includes a third portion signal line D1 and a fourth portion signal line D2 connected alternately in the first direction X, and the orthographic projection of the fourth portion signal line D2 on the substrate 10 overlaps with the orthographic projection of the scan line S, the light emitting switch signal line Emit on the substrate 10, and does not overlap with the orthographic projections of the initialization voltage line Vint and the power voltage line Vdd on the substrate 10.

Wherein the initialization voltage line Vint is located at the modulation layer 11; the third part of signal line D1, scan line S and light-emitting switch signal line Emit are located in the first metal layer 13; the power supply voltage line Vdd is located at the second metal layer 15.

The fourth partial signal line D2 is located in the second metal layer 15 and is electrically connected to the third partial signal line D1 through a via hole located in the interlayer insulating layer 14.

In one example, the third portion of the signal line D1 located in the first metal layer 13 is in an "L" type arrangement, one portion extending in the first direction X, and the other portion extending in the second direction Y; the end of the fourth partial signal line D2 located in the second metal layer 15 is aligned with the end of the third partial signal line D1 extending in the second direction Y and is electrically connected to each other through the via hole H located in the interlayer insulating layer 14, so that the data line D is bridged at a position intersecting the scan line S and the light emitting switch signal line Emit.

In addition, the film layer structure of the data line D is changed, and the film layer of the source/drain electrode of the TFT connected to the data line D is also changed. For example, the third portion signal line D1 is located in the first metal layer 13, and the source and drain electrodes of the tft may also be located in the first metal layer 13. The fourth part of the signal line D2 is only used for bridging and is not electrically connected with the source and drain electrodes of the TFT, so that the manufacturing difficulty of the array substrate 1 is reduced.

Fourth embodiment

Fig. 10 is a schematic structural diagram of an array substrate according to a fourth embodiment of the present application; fig. 11 shows a cross-section of fig. 10 along direction C-C.

As shown in fig. 10 and 11, the array substrate 1 provided in the fourth embodiment of the present application is similar to the array substrate 1 provided in the third embodiment, and is different in that the film layer where the fourth portion of the signal lines D2 used for bridging the data lines D are located is different.

The fourth partial signal line D2 is located in the electrode layer 17 and is electrically connected to the third partial signal line D1 through a via hole penetrating the film layer between the passivation layer 16 and the interlayer insulating layer 14.

In one example, the third portion of the signal line D1 located in the first metal layer 13 is in an "L" type arrangement, one portion extending in the first direction X, and the other portion extending in the second direction Y; the end of the fourth partial signal line D2 located in the electrode layer 17 is aligned with the end of the third partial signal line D1 extending in the second direction Y and is electrically connected to each other through the via hole H penetrating the film layer between the passivation layer 16 and the interlayer insulating layer 14, so that the data line D is bridged at a position overlapping and intersecting the scan line S and the light emitting switch signal line Emit.

Fig. 12 is a schematic view showing the structure of another array substrate in the related art.

As shown in fig. 12, another array substrate in the related art includes a plurality of sub-pixels distributed in an array and various signal lines, wherein the data lines D and the power voltage lines Vdd are vertically arranged along a first direction X and are arranged on the same metal layer. The light-emitting switch signal line (Emit), the initialization voltage line (Vint) and the scanning line (Gate) are transversely arranged along the second direction Y and are arranged on the same metal layer, and two adjacent sub-pixels Px are arranged in a mirror image mode and share the same power voltage line Vdd. Because the wiring has respective line width and line distance requirements, how to save wiring space and how to reduce the load of the signal lines becomes a difficult problem to be solved under the trend that the arrangement space of the signal lines is increasingly reduced.

Fifth embodiment

Fig. 13 is a schematic structural diagram of an array substrate according to a fifth embodiment of the present application; FIG. 14 shows a cross-sectional view of FIG. 13 along direction A-A; fig. 15 shows a cross-section of fig. 13 along direction B-B.

As shown in fig. 13 to 15, the array substrate 1 according to the fifth embodiment of the present application is similar to the array substrate 1 according to the first embodiment, except for the pixel circuit structure.

Specifically, in the first direction X, two adjacent subpixels Px are mirror-arranged and share the same power supply voltage line Vdd, and two data lines D and two initialization voltage lines Vint are arranged between two adjacent subpixels Px stacked with one power supply voltage line Vdd.

Further, the array substrate 1 further includes a modulation layer 11, a buffer layer 12, a first metal layer 13, an interlayer insulating layer 14, a second metal layer 15, a passivation layer 16, and an electrode layer 17 sequentially formed on the substrate 10.

The two data lines D and the two initialization voltage lines Vint are symmetrically arranged respectively, and compared with the first embodiment to the fourth embodiment, the occupation space of the plurality of signal lines of the array substrate provided by the fifth embodiment is smaller, so that the wiring space of the signal lines can be further saved, and the pixel aperture ratio can be further improved. Or under the condition of ensuring that the wiring space of the original signal wires is unchanged, the line width of each signal wire can be further increased, and the load of each signal wire is further reduced.

Sixth embodiment

Fig. 16 is a schematic structural diagram of an array substrate according to a sixth embodiment of the present application; fig. 17 shows a cross-section of fig. 16 along direction C-C.

As shown in fig. 16 to 17, the array substrate 1 provided in the sixth embodiment of the present application is similar to the array substrate 1 provided in the fifth embodiment, and is different in that the initialization voltage line Vint is different from the second portion of the signal line Vint2 for bridging.

Seventh embodiment

Fig. 18 is a schematic structural diagram of an array substrate according to a seventh embodiment of the present application; FIG. 19 shows a cross-sectional view of FIG. 18 along direction E-E; fig. 20 shows a cross-section of fig. 18 along direction F-F.

As shown in fig. 18 to 20, the array substrate 1 provided in the seventh embodiment of the present application is similar to the array substrate 1 provided in the fifth embodiment, and is different in that the initialization voltage line Vint and the data line D are interchanged in the film layer, and the data line D is bridged at the same layer and intersecting position with the scan line S and the light emitting switch signal line Emit.

In one example, the third portion of the signal line D1 located in the first metal layer 13 is in an "L" type arrangement, one portion extending in the first direction X, and the other portion extending in the second direction Y; the end of the fourth partial signal line D2 located in the second metal layer 15 is aligned with the end of the third partial signal line D1 extending in the second direction Y and is electrically connected to each other through the via hole H located in the interlayer insulating layer 14, so that the data line D is bridged at a position overlapping and intersecting the scan line S and the light emitting switch signal line Emit.

Eighth embodiment

Fig. 21 is a schematic structural diagram of an array substrate according to an eighth embodiment of the present application; fig. 22 shows a cross-section of fig. 21 along direction J-J.

As shown in fig. 21 to 22, the array substrate 1 provided in the eighth embodiment of the present application is similar to the array substrate 1 provided in the seventh embodiment, and is different in that the fourth portion of the signal lines D2 for bridging the data lines D are located in different layers.

In addition, the embodiment of the application also provides a preparation method of any one of the array substrates 1, which comprises the following steps:

step S1: providing a substrate base 10;

step S2: forming a plurality of subpixels Px and a plurality of signal lines distributed in an array on the substrate 10, the plurality of signal lines including a data line D extending in a first direction X, a power supply voltage line Vdd, an initialization voltage line Vint, and a scan line S and a light emitting switch signal line Emit extending in a second direction Y to define corresponding subpixels Px, the first direction X intersecting the second direction Y; the initialization voltage line Vint, the data line D, and the power voltage line Vdd are stacked, and the initialization voltage line Vint or the data line D is disposed in a bridging manner at a position which is in the same layer as and intersects the scan line S and the light emitting switch signal line Emit.

With the foregoing first and fifth embodiments, in step S2, forming a plurality of signal lines on the substrate base 10 includes the following steps S21 to S25.

Step S21: depositing a modulation layer 11 on the substrate base plate 10, and etching to form a data line D;

step S22: forming a buffer layer 12 on the modulation layer 11;

step S23: forming a patterned first metal layer 13 on the buffer layer 12, etching to form a first partial signal line Vint1 of an initialization voltage line Vint, a scan line S, and a light emitting switch signal line Emit;

Step S24: forming a patterned interlayer insulating layer 14 on the first metal layer 13, the interlayer insulating layer 14 including a via hole corresponding to an end of the first partial signal line Vint 1;

step S25: a second metal layer 15 is deposited on the interlayer insulating layer 14, a second part of the signal line Vint2 of the power supply voltage line Vdd and the initialization voltage line Vint is etched, the front projection of the second part of the signal line Vint2 on the substrate 10 overlaps with the front projection of the scan line S and the light emitting switch signal line Emit on the substrate 10, and does not overlap with the front projection of the data line D and the power supply voltage line Vdd on the substrate 10, and the second part of the signal line Vint2 is electrically connected with the first part of the signal line Vint1 through the via hole H.

In the foregoing second and sixth embodiments, in step S2, forming a plurality of signal lines on the substrate 10 includes steps S21 to S24 and steps S25 'to S27' as described above.

Wherein, step S25': depositing a second metal layer 15 on the interlayer insulating layer 14, and etching to form a power supply voltage line Vdd;

step S26': forming a patterned passivation layer 16 on the second metal layer 15;

step S27': an electrode layer 17 is deposited on the passivation layer 16, a second portion of the signal line Vint2 of the initialization voltage line Vint is etched, the orthographic projection of the second portion of the signal line Vint2 on the substrate 10 overlaps with the orthographic projection of the scan line S and the light emitting switch signal line Emit on the substrate 10, and does not overlap with the orthographic projection of the data line D and the power voltage line Vdd on the substrate 10, and the second portion of the signal line Vint2 is electrically connected to the first portion of the signal line Vint1 through a via H penetrating through a film layer between the passivation layer 16 and the interlayer insulating layer 14.

With the foregoing third and seventh embodiments, in step S2, forming a plurality of signal lines on the substrate base 10 includes the following steps S31 to S35.

Step S31: depositing a modulation layer 11 on a substrate base plate 10, and etching to form an initialization voltage line Vint;

step S32: forming a buffer layer 12 on the modulation layer 11;

step S33: forming a patterned first metal layer 13 on the buffer layer 12, etching to form a third portion of the signal lines D1, the scan lines S, and the light emitting switch signal lines Emit of the data lines D;

step S34: forming a patterned interlayer insulating layer 14 on the first metal layer 13, the interlayer insulating layer 14 including a via hole corresponding to an end of the third partial signal line D1;

step S35: a second metal layer 15 is deposited on the interlayer insulating layer 14, and a fourth portion of the signal line D2 of the power supply voltage line Vdd and the data line D is etched to form an overlap of the orthographic projection of the fourth portion of the signal line D2 on the substrate 10 with the orthographic projection of the scan line S and the light emitting switch signal line Emit on the substrate 10, and does not overlap with the orthographic projection of the initialization voltage line Vint and the power supply voltage line Vdd on the substrate 10, and the fourth portion of the signal line D2 is electrically connected to the third portion of the signal line D1 through the via hole.

In the fourth and eighth embodiments described above, in step S2, forming a plurality of signal lines on the substrate 10 includes steps S31 to S34 and steps S35 'to S37' as described above.

Wherein, step S35': depositing a second metal layer 15 on the interlayer insulating layer 14, and etching to form a power supply voltage line Vdd;

step S36': forming a patterned passivation layer 16 on the second metal layer 15;

step S37': the electrode layer 17 is deposited on the passivation layer 16, and the fourth portion of the signal line D2 of the data line D is etched to form, where the orthographic projection of the fourth portion of the signal line D2 on the substrate 10 overlaps with the orthographic projection of the scan line S and the light emitting switch signal line Emit on the substrate 10, and does not overlap with the orthographic projections of the initialization voltage line Vint and the power voltage line Vdd on the substrate 10, and the fourth portion of the signal line D2 is electrically connected to the third portion of the signal line D1 through a via hole penetrating through the passivation layer 16 to the film layer between the interlayer insulating layers 14.

It should be noted that, in the present application, the patterning process may include a photolithography process, or include a photolithography process and an etching step, and may also include other processes for forming a predetermined pattern, such as printing, ink-jet, and the like; the photolithography process refers to processes using photoresist, mask plate, exposure machine, etc. including film forming, exposure, development, etc., and corresponding patterning processes can be selected according to the structure formed in the present application.

In addition, an embodiment of the present application further provides a display apparatus, including: any of the array substrates 1 as described above. The display device may be implemented as any product or component having a display function, such as a liquid crystal display device, an Organic Light Emitting Diode (OLED) display panel, an electronic book, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator.

In one example, the display device is an OLED display panel, and further includes a pixel defining layer, a light emitting layer, and an encapsulation layer on the array substrate 1.

The pixel defining layer includes a plurality of pixel openings, and the light emitting layer includes a plurality of light emitting elements distributed in an array, each light emitting element corresponding to a pixel opening of the pixel defining layer. The light emitting element includes an anode in the electrode layer 17, a light emitting structure on the anode, and a cathode on the light emitting structure, with the pixel opening exposing the anode.

The encapsulation layer is located at the side of the light emitting layer facing away from the array substrate 1. The packaging layer can inhibit the cracking of the inorganic film, release the stress between inorganic matters, and improve the flexibility of the whole packaging layer 23, thereby realizing reliable flexible packaging.

In another example, the display device may also be a Micro/Mini-LED display, including a light emitting layer and a cover plate on the array substrate 1. Wherein the light emitting layer comprises a plurality of light emitting elements distributed in an array, and the light emitting elements can be any one of Micro light emitting diodes (Micro-LEDs) and submillimeter light emitting diodes (Mini-LEDs).

In another example, the display device may further be a liquid crystal display, including a liquid crystal display panel and a backlight module disposed on a backlight side of the liquid crystal display panel, where the backlight module is configured to provide a light source to the liquid crystal display panel. The liquid crystal display panel comprises an array substrate 1, a color film substrate and a liquid crystal layer positioned between the array substrate 1 and the color film substrate, which are oppositely arranged.

It should be readily understood that the terms "on … …", "above … …" and "above … …" in this disclosure should be interpreted in the broadest sense so that "on … …" means not only "directly on something" but also includes "on something" with intermediate features or layers therebetween, and "above … …" or "above … …" includes not only the meaning "on something" or "above" but also the meaning "above something" or "above" without intermediate features or layers therebetween (i.e., directly on something).

The term "substrate base" as used herein refers to a material to which subsequent layers of material are added. The substrate itself may be patterned. The material added atop the substrate base plate may be patterned or may remain unpatterned. In addition, the substrate base may comprise a wide range of materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate base plate may be made of a non-conductive material (e.g., glass, plastic, or sapphire wafer, etc.).

The term "layer" as used herein may refer to a portion of material that includes regions having a certain thickness. The layer may extend over the entire underlying or overlying structure, or may have a range that is less than the range of the underlying or overlying structure. Further, the layer may be a region of a continuous structure, either homogenous or non-homogenous, having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any pair of lateral planes at the top and bottom surfaces. The layers may extend laterally, vertically and/or along a tapered surface. The substrate base may be a layer, may include one or more layers therein, and/or may have one or more layers located thereon, and/or thereunder. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers (within which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.

Claims

1. An array substrate comprises a substrate, a plurality of sub-pixels and a plurality of signal lines, wherein the sub-pixels and the signal lines are arranged on the substrate in an array mode, the signal lines comprise data lines, power voltage lines, scanning lines and light-emitting switch signal lines, the data lines and the power voltage lines extend along a first direction, the scanning lines and the light-emitting switch signal lines extend along a second direction, the scanning lines and the light-emitting switch signal lines are used for limiting the corresponding sub-pixels, the first direction and the second direction are intersected,

the plurality of signal lines further include an initialization voltage line extending in the first direction, the initialization voltage line, the data line, and the power voltage line are stacked, and the initialization voltage line or the data line is disposed in a bridging manner at a position which is in the same layer as the scan line and the light-emitting switch signal line and intersects the scan line and the light-emitting switch signal line;

the semiconductor device further comprises a modulation layer, a buffer layer, a first metal layer, an interlayer insulating layer, a second metal layer, a passivation layer and an electrode layer which are sequentially formed on the substrate;

the initialization voltage line comprises a first part of signal lines and a second part of signal lines which are connected in a staggered manner along the first direction, wherein the orthographic projection of the second part of signal lines on the substrate is overlapped with the orthographic projection of the scanning lines and the light-emitting switch signal lines on the substrate, and the orthographic projection of the second part of signal lines on the substrate is not overlapped with the orthographic projection of the data lines and the power voltage lines on the substrate;

Wherein the data line is positioned on the modulation layer; the first part of signal lines, the scanning lines and the light-emitting switch signal lines are positioned on the first metal layer; the power voltage line is positioned on the second metal layer;

the second part of signal line is positioned on the second metal layer and is electrically connected with the first part of signal line through the via hole positioned on the interlayer insulating layer;

or the second part of signal line is positioned on the electrode layer and is electrically connected with the first part of signal line through a via hole penetrating through the passivation layer to the film layer between the interlayer insulating layers;

or, the data line includes a third part of signal lines and a fourth part of signal lines which are connected in a staggered manner along the first direction, and the orthographic projection of the fourth part of signal lines on the substrate overlaps with the orthographic projections of the scanning lines and the light-emitting switch signal lines on the substrate, and does not overlap with the orthographic projections of the initialization voltage line and the power supply voltage line on the substrate;

wherein the initialization voltage line is positioned on the modulation layer; the third part of signal lines, the scanning lines and the light-emitting switch signal lines are positioned on the first metal layer; the power voltage line is positioned on the second metal layer;

The fourth part of signal line is positioned on the second metal layer and is electrically connected with the third part of signal line through a via hole positioned on the interlayer insulating layer;

or the fourth part of signal line is positioned on the electrode layer and is electrically connected with the third part of signal line through a via hole penetrating through the passivation layer to the film layer between the interlayer insulating layers.

2. The array substrate of claim 1, wherein the initialization voltage line, the data line, and the power voltage line are stacked on one side of the corresponding sub-pixels.

3. The array substrate according to claim 1, wherein in the first direction, two adjacent sub-pixels are mirror-image arranged and share the same one of the power supply voltage lines, and two data lines and two initializing voltage lines are stacked with one of the power supply voltage lines between the two adjacent sub-pixels.

4. The array substrate of claim 1, wherein a line width of the power supply voltage line is greater than a line width of the data line and a line width of the initialization voltage line.

5. A method of manufacturing the array substrate according to any one of claims 1 to 4, comprising:

Providing a substrate;

forming a plurality of sub-pixels and a plurality of signal lines distributed in an array on the substrate, wherein the plurality of signal lines comprise data lines, power supply voltage lines, initialization voltage lines, scanning lines and light-emitting switch signal lines which extend along a first direction and a second direction, so as to limit the corresponding sub-pixels, and the first direction is intersected with the second direction; the initialization voltage line, the data line and the power voltage line are arranged in a stacked mode, and the initialization voltage line or the data line is arranged in a bridging mode at a position which is in the same layer as the scanning line and the light-emitting switch signal line and is intersected with the scanning line and the light-emitting switch signal line; wherein the forming a plurality of signal lines on the substrate includes:

depositing a modulation layer on a substrate base plate, and etching to form the data line;

forming a buffer layer on the modulation layer;

forming a patterned first metal layer on the buffer layer, and etching to form a first part of signal lines, the scanning lines and the light-emitting switch signal lines of the initialization voltage lines;

forming a patterned interlayer insulating layer on the first metal layer, the interlayer insulating layer including a via hole corresponding to an end of the first portion signal line;

Forming a second metal layer on the interlayer insulating layer in a depositing way, etching to form second part of signal lines of the power voltage line and the initialization voltage line, wherein the orthographic projection of the second part of signal lines on the substrate is overlapped with the orthographic projections of the scanning line and the light-emitting switch signal lines on the substrate, and the orthographic projections of the data lines and the power voltage line on the substrate are not overlapped with each other, and the second part of signal lines are electrically connected with the first part of signal lines through the through holes;

or depositing a second metal layer on the interlayer insulating layer, and etching to form the power voltage line;

forming a patterned passivation layer on the second metal layer;

forming an electrode layer on the passivation layer by deposition, and etching to form a second part of signal line of the initialization voltage line, wherein the orthographic projection of the second part of signal line on the substrate is overlapped with the orthographic projection of the scanning line and the luminescent switch signal line on the substrate, and is not overlapped with the orthographic projection of the data line and the power voltage line on the substrate, and the second part of signal line is electrically connected with the first part of signal line through a via hole penetrating through the passivation layer to a film layer between the interlayer insulating layers;

Alternatively, the forming the plurality of signal lines on the substrate includes:

depositing a modulation layer on a substrate base plate, and etching to form the initialization voltage line;

forming a buffer layer on the modulation layer;

forming a patterned first metal layer on the buffer layer, and etching to form a third part of signal lines, the scanning lines and the light-emitting switch signal lines of the data lines;

forming a patterned interlayer insulating layer on the first metal layer, the interlayer insulating layer including a via hole corresponding to an end of the third portion signal line;

forming a second metal layer on the interlayer insulating layer in a deposition mode, etching to form a fourth part of signal lines of the power voltage line and the data line, wherein orthographic projection of the fourth part of signal lines on the substrate is overlapped with orthographic projections of the scanning line and the light-emitting switch signal lines on the substrate, orthographic projections of the initialization voltage line and the power voltage line on the substrate are not overlapped with each other, and the fourth part of signal lines are electrically connected with the third part of signal lines through the through holes;

Forming a patterned passivation layer on the second metal layer;

and depositing an electrode layer on the passivation layer, etching to form a fourth part of signal line of the data line, wherein the orthographic projection of the fourth part of signal line on the substrate is overlapped with the orthographic projection of the scanning line and the luminescent switch signal line on the substrate, and is not overlapped with the orthographic projections of the initialization voltage line and the power voltage line on the substrate, and the fourth part of signal line is electrically connected with the third part of signal line through a via hole penetrating through the passivation layer to a film layer between the interlayer insulating layers.

6. A display device, comprising: the array substrate of any one of claims 1 to 4.