CN115373458B - LDO power supply with output voltage quick response - Google Patents
LDO power supply with output voltage quick response Download PDFInfo
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- CN115373458B CN115373458B CN202211299397.XA CN202211299397A CN115373458B CN 115373458 B CN115373458 B CN 115373458B CN 202211299397 A CN202211299397 A CN 202211299397A CN 115373458 B CN115373458 B CN 115373458B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention discloses an LDO power supply with fast response of output voltage, which relates to the technical field of integrated circuits and comprises an error amplifier, a buffer-stage circuit, an output and feedback module and a detection module, wherein the error amplifier compares reference voltage with a feedback signal to generate a control signal and outputs the control signal to the buffer-stage circuit; the buffer stage circuit drives the output and feedback module, and when receiving the detection signal of the detection module, the output voltage of the output and feedback module stops increasing; the output and feedback module outputs voltage and outputs a feedback signal to the error amplifier; and after the detection module detects that the instantaneous change of the output voltage exceeds a preset value, the detection module outputs a detection signal to the buffer stage circuit. The invention can adjust the adjusting time of the detection module through design parameters, and can always control the output voltage fluctuation within 50mV no matter how fast the load is switched or how frequent the load is switched within the load carrying capacity range of the LDO, thereby avoiding the problem that other chips are damaged by the voltage which is excessively output for a long time.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to an LDO power supply with output voltage quick response.
Background
With the continuous development and progress of chip technology, the advanced processes of 3nm, 5nm and the like gradually enter the stage of mass production, so that the integration level of various processor chips is increased under the condition of the same area, the processing speed is increased, and meanwhile, the requirement on the power supply voltage is higher and higher. With the reduction of the manufacturing process, the power supply voltage of the chip is also reduced proportionally, assuming that the standard power supply voltage is VCC, the safe power supply voltage range of the general chip is VCC ± VCC 10%, for example, when VCC =0.9V, the safe power supply voltage range is VCC ± VCC 10%, that is, 0.81v to 0.99v, when the power supply voltage exceeds 0.99V, the physical damage of the chip is easily caused, and the chip cannot be repaired, and the power supply voltage lower than 0.81V may cause the chip to work abnormally. In a scenario applied to a portable device, a power supply chip (power output port) generally uses an external capacitor (a large-capacitance capacitor is added on a PCB for voltage stabilization) to supply power to a low-power consumption (microampere-level static power consumption) low-dropout linear regulator LDO, so that the output voltage of the power supply chip is relatively stable, the output voltage of the LDO changes instantaneously under the condition of instantaneous change of a load, for example, when the load changes from 100mA to 0mA, the output voltage of the LDO increases several hundred millivolts (with the external capacitor) instantaneously, when the load changes from 0mA to 100mA, the output voltage of the LDO decreases several hundred millivolts instantaneously (if an LDO without the external capacitor is used, the transient voltage of the LDO even reaches the transient power voltage of the LDO), the time for the changed voltage to recover to the normal voltage under the low-power consumption condition is greatly increased, and the probability of chip burnout and the function error are greatly increased.
Disclosure of Invention
The invention aims to provide an LDO power supply with output voltage quick response, which is used for solving the problems that in the prior art, a power supply chip using an external capacitor has larger instantaneous change of the output voltage under the condition of instantaneous change of a load, the time for the changed voltage to return to a normal voltage is increased, the probability of chip burning-out is increased, and the function of the power supply chip is wrong.
The invention solves the problems through the following technical scheme:
the utility model provides an output voltage quick response's LDO power, includes error amplifier, buffer stage circuit, output and feedback module and detection module, wherein:
the error amplifier is used for comparing an input reference voltage with a feedback signal of the output and feedback module, generating a control signal and outputting the control signal to the buffer stage circuit;
the buffer stage circuit is used for driving the output and feedback module and adjusting the output signal to stop increasing the output voltage of the output and feedback module when receiving the detection signal output by the detection module;
the output and feedback module is used for driving a power tube of the buffer stage circuit to be turned on or turned off according to an output signal of the buffer stage circuit, adjusting output voltage and outputting a feedback signal to the error amplifier;
and the detection module is used for outputting a detection signal to the buffer stage circuit after detecting that the instantaneous change of the output voltage exceeds a preset value, and closing the buffer stage circuit after the instantaneous change of the output voltage is smaller than the preset value.
The invention comprises an error amplifier, a buffer stage circuit, an output and feedback module and a detection module, wherein the error amplifier generates a control signal by comparing a signal fed back by a receiving output end with a reference voltage and outputs the control signal to the buffer stage circuit; the buffer stage circuit has large driving capability and can quickly drive the power output and feedback module; the output and feedback module generates output voltage and a feedback signal; the detection circuit detects the change of the output voltage, the detection module responds only when the load connected with the output changes greatly instantly, a signal is output to the buffer circuit after the change is detected, the buffer circuit closes a power tube in the output module at the moment, the output voltage stops increasing at the moment, the detection module works before the system reaction, and the detection module is closed after the system reaction is adjusted to keep the output voltage unchanged (due to the limitation of the system bandwidth, the time of the instant change is far shorter than the time that the system can respond).
The error amplifier adopts a folding cascode operational amplifier, and specifically comprises an MOS tube M1, an MOS tube M2, an MOS tube M3, an MOS tube M4, an MOS tube M5, an MOS tube M6, an MOS tube M7, an MOS tube M8, an MOS tube M9, an MOS tube M10, an MOS tube M11 and an MOS tube M12, wherein the grid electrode of the MOS tube M1 is connected with a bias voltage VP1, the grid electrode of the MOS tube M2 is connected with a bias voltage VP2, the grid electrodes of the MOS tube M11 and the MOS tube M12 are connected with a bias voltage VN1, the grid electrodes of the MOS tube M9 and the MOS tube M10 are connected with a bias voltage VN2, the drain electrode of the MOS tube M1 is connected with the source electrode of the MOS tube M2, the source electrode of the MOS tube M1 is connected with a power supply voltage, the drain electrode VCC of the MOS tube M2 is connected with the source electrodes of the MOS tube M3 and the MOS tube M4, the grid electrode of the MOS tube M3 is used as a positive input end of the error amplifier, and the grid electrode of the MOS tube M4 is used as a negative input end of the error amplifier; the drain electrode of the MOS transistor M3 is connected with the source electrode of the MOS transistor M10 and the drain electrode of the MOS transistor M12, and the drain electrode of the MOS transistor M4 is connected with the source electrode of the MOS transistor M9 and the drain electrode of the MOS transistor M11; the source electrodes of the MOS tube M11 and the MOS tube M12 are grounded, the drain electrode of the MOS tube M9 is connected with the drain electrode of the MOS tube M7, the grid electrode of the MOS tube M5 and the grid electrode of the MOS tube M6, the grid electrode of the MOS tube M7 is connected with the grid electrode of the MOS tube M8 and the bias voltage VP2, the source electrode of the MOS tube M7 is connected with the drain electrode of the MOS tube M5, and the drain electrode of the MOS tube M8 is connected with the drain electrode of the MOS tube M10 and serves as the output end of the error amplifier; the source electrode of the MOS transistor M8 is connected with the drain electrode of the MOS transistor M6, and the source electrodes of the MOS transistor M5 and the MOS transistor M6 are connected with the source electrode of the MOS transistor M1.
The folded cascode operational amplifier is adopted, has single-stage high-gain characteristic, meets the requirement, and meets the requirement that the system is kept stable under any condition, and the phase margin of the whole system is kept above 45 degrees, so that when the folded cascode operational amplifier is applied to an SOC or other chips with higher requirements, the LDO output voltage has a damped oscillation state when the load change is large when the phase margin is lower than 45 degrees, and the system problem which is possibly caused is avoided.
The source electrode of the MOS transistor M10 is further connected with the first end of a capacitor C1, and the second end of the capacitor C1 is connected with the output voltage of the output and feedback module.
The compensation point is arranged between the MOS tube M10 and the MOS tube M12 by the Miller compensation technology, compared with the traditional method that the compensation point is arranged between the MOS tube M8 and the MOS tube M10, the method has 3 advantages: 1. the power supply rejection ratio is enhanced; 2. the Slew Rate (voltage conversion Rate, slew Rate for short) of the operational amplifier is greatly increased; 3. an additional compensation zero is added by using the MOS transistor M10.
The buffer circuit comprises an MOS tube M13, an MOS tube M14, an MOS tube M15, an MOS tube M16, an MOS tube M17 and an MOS tube M18, the grid electrodes of the MOS tube M13 and the MOS tube M16 are connected with a bias voltage VP1, the source electrodes of the MOS tube M13 and the MOS tube M16 are connected with a power supply voltage VCC, the drain electrode of the MOS tube M13 is connected with the source electrode of the MOS tube M14, the drain electrode of the MOS tube M16 is connected with the source electrode of the MOS tube M17, the grid electrodes of the MOS tube M14 and the MOS tube M17 are connected with the bias voltage VP1, the drain electrode of the MOS tube M14 is connected with the source electrode of the MOS tube M15 and the drain electrode of the MOS tube M18 and is connected with the output and feedback module as the output end of the buffer circuit, the grid electrode of the MOS tube M15 is connected with the input end of the buffer circuit and the output end of the error amplifier, the drain electrode of the MOS tube M15 is grounded, the source electrode of the MOS tube M18 is connected with the drain electrode of the MOS tube M17, and the grid electrode of the detection module is connected with the output end of the detection module.
The buffer stage circuit adopts a P-type MOS tube as a source follower of an input stage, the source follower is composed of an MOS tube M13, an MOS tube M14 and an MOS tube M15, the MOS tube M16, the MOS tube M17 and the MOS tube M18 only work when the load is switched, when the load is switched from 100mA to 0mA within a very short time (such as 100 ns), the output voltage is increased because the power tube cannot be controlled in time due to slow response time (the response time level is microsecond), so that a capacitor is added outside a chip in some system applications, the capacitor supplies power when the system is not reacted, and the cost is limited by many considerations, the capacitor is not used too large, so that some voltage is increased during switching even if the capacitor is used; in the scheme, when the module detects that the output voltage changes instantly, the control signal output by the detection module is rapidly changed from high level to low level to turn on the MOS transistor M18, and at this time, the output of the buffer stage circuit is instantly pulled high to approach the power supply voltage VCC, so that the power transistor in the output and feedback module approaches the off state, and at this time, the output voltage of the output and feedback module stops increasing continuously because no power transistor provides current.
Output and feedback module include MOS pipe M19, resistance R1 and resistance R2, MOS pipe M19's source electrode is connected supply voltage VCC, MOS pipe M19's drain electrode is connected resistance R1's first end is as output and feedback module's output and is connected detection module's input, resistance R1's second end is connected resistance R2's first end with error amplifier's negative input end, resistance R2's second end ground connection, MOS pipe M19's grid is connected buffer stage circuit's output. The MOS transistor M19 is a power transistor, and the resistor R1 and the resistor R2 form a resistor feedback module.
The detection module comprises an amplifier AMP, a resistor R3, a resistor R4, a resistor R5 and a resistor R6, wherein the first end of the resistor R3 is connected with the output end of the output and feedback module, the second end of the resistor R3 is connected with the first end of the resistor R4 and the first end of the resistor R6, the second end of the resistor R6 is connected with the positive input end of the amplifier AMP, the first end of the capacitor C2 and the first end of the capacitor C3, the second end of the resistor R4 is connected with the first end of the resistor R5 and the negative input end of the amplifier AMP, the second end of the capacitor C2 and the second end of the resistor R5 are grounded, the second end of the capacitor C3 is used as the output end of the detection module and is connected with the buffer circuit, the output end of the amplifier AMP is connected with the grids of the MOS tubes M21 and M22, the drain electrode of the MOS tube M21 is connected with the drain electrode of the MOS tube M22, the grid electrode of the MOS tube M23 and the grid electrode of the MOS tube M24 are connected with the power supply voltage VCC, and the drain electrode of the MOS tube M23 is connected with the second end of the capacitor C3.
The resistor R3, the resistor R4, and the resistor R5 sample the output voltage, the adjusting resistor R4 can set the detection precision, and can set the precision according to the corresponding application environment, for example, the set precision is 20mV, when the load is switched from a moment of 100mA (for example, 100ns time) to 0mA, the output voltage of the output and feedback module rises rapidly, due to the RC structure of the resistor R6 and the capacitor C2, the output state of the amplifier AMP changes when the voltage of the negative input terminal exceeds the voltage of the positive input terminal because the positive input terminal of the amplifier AMP changes slowly compared with the negative input terminal, the control signal output by the detection module is changed from a high level (power supply voltage VCC) to 0V, and when the positive input level between the resistor R6 and the capacitor C2 returns to the high level (power supply voltage VCC), the adjustment state ends. After the values of the capacitor C2 and the capacitor C3 are determined, the adjusting time of the detection module can be designed only by adjusting the value of the resistor R6, so that the detection module has the advantages of rapidness, accuracy, time controllability and the like.
Compared with the prior art, the invention has the following advantages and beneficial effects:
(1) According to the invention, the adjustment time of the detection module can be adjusted through design parameters, and the output voltage fluctuation can be always controlled within 50mV no matter how fast the load is switched or how frequent the load is switched within the load carrying capacity range of the LDO, so that the problem that other chips are damaged by the excessively output voltage for a long time is solved.
(2) The invention has wide applicability and quick and accurate detection capability; the detection bandwidth and the system bandwidth are crossed, so that the system has good response capability in the whole range; the energy consumption of the detection part is low.
Drawings
FIG. 1 is a functional block diagram of the present invention;
FIG. 2 is a circuit schematic of an error amplifier;
FIG. 3 is a schematic diagram of a circuit with Miller compensation added to the error amplifier;
FIG. 4 is a circuit schematic of a buffer stage circuit;
FIG. 5 is a circuit schematic of the output and feedback module;
FIG. 6 is a circuit schematic of the detection module;
FIG. 7 is a comparison of the present invention with the prior art;
FIG. 8 is a graph of simulation results of transient response for mode A of FIG. 7, wherein (a) is the output voltage waveform; (b) is a simulated load waveform; (c) a load current waveform for the real simulation;
FIG. 9 is a graph of transient response simulation results for mode B of FIG. 7; wherein, (a) is an output voltage waveform; (b) a simulated load waveform; (c) a load current waveform for the real simulation;
FIG. 10 is a graph of simulation results of the transient response of mode C of FIG. 7, wherein (a) is the output voltage waveform; (b) is a simulated load waveform; and (c) the real simulated load current waveform.
Detailed Description
The present invention will be described in further detail with reference to examples, but the embodiments of the present invention are not limited thereto.
Example 1:
with reference to fig. 1, an LDO power supply with fast response of output voltage includes an error amplifier, a buffer circuit, an output and feedback module, and a detection module, wherein:
the error amplifier is used for comparing an input reference voltage with a feedback signal of the output and feedback module, generating a control signal and outputting the control signal to the buffer stage circuit;
the buffer stage circuit is used for driving the output and feedback module, and adjusting the output signal to stop increasing the output voltage of the output and feedback module when receiving the detection signal output by the detection module;
the output and feedback module is used for driving a power tube of the buffer stage circuit to be turned on or turned off according to an output signal of the buffer stage circuit, adjusting output voltage and outputting a feedback signal to the error amplifier;
and the detection module is used for outputting a detection signal to the buffer stage circuit after detecting that the instantaneous change of the output voltage exceeds a preset value, and closing the buffer stage circuit after the instantaneous change of the output voltage is smaller than the preset value.
The invention comprises an error amplifier, a buffer stage circuit, an output and feedback module and a detection module, wherein the error amplifier generates a control signal by comparing a signal fed back by a receiving output end with a reference voltage and outputs the control signal to the buffer stage circuit; the buffer stage circuit has large driving capability and can quickly drive the power output and feedback module; the output and feedback module generates output voltage and a feedback signal; the detection circuit detects the change of the output voltage, the detection module responds only when the load connected with the output changes greatly instantly, the signal is output to the buffer circuit after the change is detected, the buffer circuit can close the power tube in the output module at the moment, the output voltage also stops increasing at the moment, the detection module works before the system reaction, and the detection module is closed after the system reaction is adjusted to keep the output voltage unchanged after the system reaction is waited (due to the limitation of the bandwidth of the system, the time of the instant change is far less than the time that the system can respond).
Example 2:
on the basis of embodiment 1, with reference to fig. 2, the error amplifier employs a folded cascode operational amplifier, and specifically includes a MOS transistor M1, a MOS transistor M2, a MOS transistor M3, a MOS transistor M4, a MOS transistor M5, a MOS transistor M6, a MOS transistor M7, a MOS transistor M8, a MOS transistor M9, a MOS transistor M10, a MOS transistor M11, and a MOS transistor M12, where a gate of the MOS transistor M1 is connected to a bias voltage VP1, a gate of the MOS transistor M2 is connected to a bias voltage VP2, gates of the MOS transistors M11 and M12 are connected to a bias voltage VN1, gates of the transistors M9 and M10 are connected to a bias voltage VN2, a drain of the MOS transistor M1 is connected to a source of the MOS transistor M2, a source of the MOS transistor M1 is connected to a power supply voltage VCC, a drain of the MOS transistor M2 is connected to a source of the transistors M3 and M4, a gate of the MOS transistor M3 is used as a positive input terminal of the error amplifier, and a negative terminal of the MOS transistor M4 is used as a negative input terminal of the error amplifier; the drain electrode of the MOS tube M3 is connected with the source electrode of the MOS tube M10 and the drain electrode of the MOS tube M12, and the drain electrode of the MOS tube M4 is connected with the source electrode of the MOS tube M9 and the drain electrode of the MOS tube M11; the source electrodes of the MOS tube M11 and the MOS tube M12 are grounded, the drain electrode of the MOS tube M9 is connected with the drain electrode of the MOS tube M7, the grid electrode of the MOS tube M5 and the grid electrode of the MOS tube M6, the grid electrode of the MOS tube M7 is connected with the grid electrode of the MOS tube M8 and the bias voltage VP2, the source electrode of the MOS tube M7 is connected with the drain electrode of the MOS tube M5, the drain electrode of the MOS tube M8 is connected with the drain electrode of the MOS tube M10 and serves as the output end of the error amplifier, and the output end of the error amplifier outputs a control signal VOUT; the source electrode of the MOS transistor M8 is connected with the drain electrode of the MOS transistor M6, and the source electrodes of the MOS transistor M5 and the MOS transistor M6 are connected with the source electrode of the MOS transistor M1.
The folded cascode operational amplifier is adopted, has single-stage high-gain characteristic, meets the requirement, and meets the requirement that the system is kept stable under any condition, and the phase margin of the whole system is kept above 45 degrees, so that when the folded cascode operational amplifier is applied to an SOC or other chips with higher requirements, the LDO output voltage has a damped oscillation state when the load change is large when the phase margin is lower than 45 degrees, and the system problem which is possibly caused is avoided.
Referring to fig. 3, the source of the MOS transistor M10 is further connected to the first end of the capacitor C1, and the second end of the capacitor C1 is connected to the output voltage of the output and feedback module.
The compensation point is arranged between the MOS tube M10 and the MOS tube M12 by the Miller compensation technology, compared with the traditional method that the compensation point is arranged between the MOS tube M8 and the MOS tube M10, the method has 3 advantages: 1. the power supply rejection ratio is enhanced; 2. the Slew Rate (voltage conversion Rate, slew Rate for short) of the operational amplifier is greatly increased; 3. an additional compensation zero is added by using the MOS transistor M10.
The Miller compensation capacitor, namely the capacitor C1, is connected with the output end of the output and feedback module at one end, and is connected with the source electrode of the MOS tube M10 at one end, the gain of the buffer stage circuit is assumed to be A1, the gain of the output and feedback module circuit is assumed to be A2, and the equivalent impedance of the MOS tube M6 and the MOS tube M8 is assumed to be R o1 X-point output resistor in FIG. 3The reactance is Rx, the output impedance at the point Y is Ry, and when the capacitor C1 is connected at the point Y, the pole frequency Sy at the point Y can be calculated as follows:
Sy=1/((R o1 /(1/gm 10 +R o1 )*A1*A2+1)*C1*Ry) (1)
1/gm in formula (1) 10 The impedance of the M10 tube looking into the source electrode is generally designed to be 1/gm 10 Has a value of 1/gm 10 <<Ro1, then equation (1) can be simplified as:
Sy=1/((A1*A2+1)*C1*Ry) (2)
if the capacitor C1 is connected to the point X, the pole frequency Sx of the point X is
Sx=1/((A1*A2+1)*C1*Rx) (3)
Comparing equations (2) and (3), it can be seen that the compensation points are mainly different from Rx and Ry at X and Y, and Rx and Ry are not very different, and they can be roughly considered to be equal, so that the compensation points are not much affected by the main pole frequency at X and Y, but have the advantage of being connected at Y:
1. the power supply rejection ratio is enhanced to a certain extent
A relatively rough analysis method can regard the MOS transistor M6, the MOS transistor M8, the MOS transistor M10, and the MOS transistor M12 as 4 resistors, and it is obvious that the influence of the fluctuation of the power supply on the Y point is smaller than the influence on the X point, that is, the power supply rejection ratio of the compensation point branch is enhanced to a certain extent;
2. greatly increasing the swing rate of the operational amplifier
Analyzing under an ideal state, when a load changes, the operational amplifier can adjust the power tube to achieve the effect of controlling the output voltage to be unchanged, in fig. 3, the voltage of the point X can be considered to be adjusted to control the power tube, and the voltage of the point Y remains unchanged under the ideal state, for example, when the voltage of the point X increases, the equivalent RC circuit of the point X is charged through the fixed currents of the MOS tube M6 and the MOS tube M8, assuming that the parasitic capacitance of the point X is Cx, the voltage of the point X rises from V1 to V2 during adjustment, and when the compensation point is at Y, the rising time of the voltage of the point X is:
T1=Rx*Cx*Ln[V2/(V2-V1)] (4)
if the compensation point is at point X, the rise time is:
T2=Rx*(Cx+C1)*Ln[V2/(V2-V1)] (5)
from the formulas (4) and (5), T2= T1 (1 + c 1/Cx) can be obtained, cx is generally very small, when Cx is 0.1pf and c1 is 4pF, T2=41 + T1, the compensation point is connected to the point X, the response time at the point X is greatly increased, and the response time at the point X is greatly reduced when the compensation point is arranged at the point Y;
3. an additional compensation zero point is added by using M10
In general, the compensation at the point X adds a resistor on the C1 loop for compensating the zero point to stabilize the system, and the compensation at the point Y adds 1/gm on the loop due to the action of the MOS transistor M10 10 A resistance of a magnitude just as useful as the zero resistance of the compensation.
Most important to the present invention is point 2 where the op-amp design can be of any form but the lower half of the dominant pole leg is preferably cascode connected to the compensation capacitor.
With reference to fig. 4, the buffer circuit includes a MOS transistor M13, a MOS transistor M14, a MOS transistor M15, a MOS transistor M16, a MOS transistor M17, and a MOS transistor M18, gates of the MOS transistor M13 and the MOS transistor M16 are connected to a bias voltage VP1, sources of the MOS transistor M13 and the MOS transistor M16 are connected to the supply voltage VCC, a drain of the MOS transistor M13 is connected to a source of the MOS transistor M14, a drain of the MOS transistor M16 is connected to a source of the MOS transistor M17, gates of the MOS transistor M14 and the MOS transistor M17 are connected to the bias voltage VP1, a drain of the MOS transistor M14 is connected to a source of the MOS transistor M15 and a drain of the MOS transistor M18 and serves as an output terminal of the buffer circuit, an output signal VOUT2 of an output terminal of the buffer circuit is connected to the output and feedback module, a gate of the MOS transistor M15 serves as an input terminal of the buffer circuit and is connected to an output terminal of the error amplifier VOUT, a drain of the MOS transistor M15 is connected to the drain of the MOS transistor M18, and a gate of the MOS transistor M18 is connected to a gate of the detection module.
The buffer stage circuit adopts a P-type MOS tube as a source follower of an input stage, the source follower is composed of an MOS tube M13, an MOS tube M14 and an MOS tube M15, the MOS tube M16, the MOS tube M17 and the MOS tube M18 only work when the load is switched, when the load is switched from 100mA to 0mA within a very short time (such as 100 ns), the output voltage is increased because the power tube cannot be controlled in time due to slow response time (the response time level is microsecond), so that a capacitor is added outside a chip in some system applications, the capacitor supplies power when the system is not reacted, and the cost is limited by many considerations, the capacitor is not used too large, so that some voltage is increased during switching even if the capacitor is used; in the scheme, when the module detects that the output voltage changes instantly, the detection signal VCM output by the detection module is rapidly changed from a high level to a low level to turn on the MOS transistor M18, and at this time, the output of the buffer circuit is pulled up instantly to approach the power supply voltage VCC, so that the power transistor in the output and feedback module approaches a closed state, and at this time, the output voltage of the output and feedback module stops increasing continuously because no power transistor provides current. As shown in fig. 4, the MOS transistor pair (M13, M14) and the MOS transistor pair (M16, M17) are all current sources with cascode structures, and ideally, the output impedance is considered to be infinite, and at this time, the gain A3 of the buffer stage circuit is equal to
A3=gm 15 /(gm 15 +gmb 15 ) (6)
In equation (6), gm 15 Transconductance of M15 tube, gmb 15 Denotes the body effect of M15, generally gmb 15 <<gm 15 Therefore, the gain of the source follower is generally regarded as 1, the large signal state is instantly changed by controlling the current sources (M16, M17), but the small signal is not interfered in an ideal state because the internal resistance of the current sources is infinite, and the adjustment of the system is not influenced.
Combine fig. 5 to show, output and feedback module includes MOS pipe M19, resistance R1 and resistance R2, MOS pipe M19's source connection supply voltage VCC, MOS pipe M19's drain connection resistance R1's first end provides output voltage VO as output and feedback module's output to the back stage, and connects detection module's input, resistance R1's second end is connected resistance R2's first end with error amplifier's negative input end, output feedback signal VFB to error amplifier's negative input promptly, resistance R2's second end ground connection, MOS pipe M19's grid is connected buffer circuit's output. The MOS transistor M19 is a power transistor, and the resistor R1 and the resistor R2 form a resistor feedback module.
Referring to fig. 6, the detection module includes an amplifier AMP, a resistor R3, a resistor R4, a resistor R5, and a resistor R6, a first end of the resistor R3 is used as an input end of the detection module to connect to the output end of the output and feedback module, a second end of the resistor R3 is connected to the first end of the resistor R4 and the first end of the resistor R6, a second end of the resistor R6 is connected to the positive input end of the amplifier AMP, the first end of the capacitor C2, and the first end of the capacitor C3, a second end of the resistor R4 is connected to the first end of the resistor R5 and the negative input end of the amplifier AMP, the second end of the capacitor C2 and the second end of the resistor R5 are grounded, the second end of the capacitor C3 is used as an output end (output detection signal VCM) of the detection module to connect to the buffer circuit, an output end of the amplifier AMP is connected to the gates of the MOS transistor M21 and the transistor M22, a drain of the MOS transistor M21 is connected to the drain of the transistor M22, a gate of the MOS transistor M23 is connected to the drain of the transistor M24 and the transistor VCC, and a drain of the transistor M23 are connected to the drain of the capacitor C3.
The resistor R3, the resistor R4, and the resistor R5 sample the output voltage VO, the adjustable resistor R4 can set the detection precision, and can set the precision according to a corresponding application environment, for example, the set precision is 20mV, when a load is switched from a moment of 100mA, such as 100ns of time, to 0mA, the output voltage of the output and feedback module rises rapidly, due to the RC structure of the resistor R6 and the capacitor C2, the output state of the amplifier AMP changes when the voltage of the negative input terminal exceeds the voltage of the positive input terminal due to the fact that the positive input terminal of the amplifier AMP changes slowly as compared with the negative input terminal, the control signal output by the detection module is changed from a high level (supply voltage VCC) to 0V, and when the positive input level between the resistor R6 and the capacitor C2 returns to a normal level, the state of the amplifier AMP returns to a high level (supply voltage VCC), and the adjustment state ends. After the values of the capacitor C2 and the capacitor C3 are determined, the adjusting time of the detection module can be designed only by adjusting the value of the resistor R6, so that the detection module has the advantages of rapidness, accuracy, time controllability and the like.
As shown in fig. 6, when the voltage at the point F is higher than the point G during normal operation, the amplifier AMP outputs a high level, that is, the detection signal VCM is at a high level at this time, after the output voltage VO of the output and feedback module rises instantaneously and the rising amplitude exceeds 20mV, the potential at the point F, G also rises instantaneously but the potential at this time is not changed due to the RC network at the point H, the potential at the point G exceeds the potential at the point H, the amplifier AMP detects that the output changes from the high level to the low level (ideally, when the point G just exceeds the voltage at the point H, the amplifier AMP detects and inverts after detection, in practice, the amplifier AMP reacts later by a period of time due to the limitations of the bandwidth and the slew rate of the amplifier AMP, the reaction time in the present invention is within 100 ns), the VCM also changes from the high level to the low level, the equivalent capacitance at the point H at this time changes to 2= C2+ C3, and the voltage at the point H changes instantaneously, the voltage at the point H before the change is set as U1, and after the change, the point U2 is set as U2:
U2=[C2*U1-C3*(VCC-U1)]/(C2+C3) (7)
VCC is a power supply voltage, then, the current charges the equivalent capacitor Ch2 through the resistor R3 and the resistor R6 until the voltage of the H point exceeds the voltage of the G point, the adjustment process of the detection module is completed, when the capacitor with a small capacitance value is used, C3 × VCC approaches to 0, and the formula (7) can be simplified as follows:
U2=[U1*(C2-C3)]/(C2+C3) (8)
as can be seen from the formula (8), the value of the voltage U2 can be set arbitrarily only by ensuring that the capacitance C2 is greater than or equal to the capacitance C3, and the capacitance C2 and the capacitance C3 are in a proportional relationship, so that the minimum unit capacitance can be used for design, and the chip area can be greatly saved; for simple analysis, the voltage at the point F is not changed, and the charging time Th at the point H is as follows by charging through the RC network of the resistor R6 and the equivalent capacitor Ch 2:
Th=R6*Ch2*Ln[Vf/(Vf-U2)] (9)
wherein Vf is the voltage at point F, ch2 and equation (7) are substituted into equation (9) to obtain:
Th=R6*(C2+C3)*Ln{Vf/{Vf-[C2*U1-C3*(VCC-U1)]/(C2+C3)}}(10)
the final result is shown in formula (10), and the adjustment time of the module can be designed by only adjusting the value of the resistor R6 after the values of the capacitors C2 and C3 are determined.
The detection module only plays a role in light load and heavy load switching, various added devices do not affect the stability, the detection module has good effects under various horners through verification, and no large deviation exists. The invention is suitable for wide-range output voltage, can meet various different output voltages, and has good compatibility and larger design margin.
Comparing the scheme with the prior art scheme, as shown in fig. 7, wherein the dotted line represents a chip, and the output voltage is connected outside the chip; the mode A represents a common LDO (low dropout regulator) without an external capacitor, the mode B represents a common LDO with an external capacitor, the mode C is the LDO power supply provided by the invention, and the transient simulation is carried out on the mode A-the mode C, and the result is as follows:
transient simulation results for mode A are shown in FIG. 8, where the LDO has an input voltage of 5V and an output of 0.9V, and point M39 (3.0 ms, 213.319mV) is shown in the figure; point M40 (3.80737ms, 895.594mV), point M39 and point M40 (dx: 807.361usdy; point M41 (6.80737ms, 895.594mV); point M42 (7.00013ms, 3.59648v), change value L3 between point M41 and point M42: (dx: 192.767us dy, 2.7009V s; point M45 (3.0 ms,1.0 uV); point M46 (3.00005 ms,100.0 mV), point M45, and point M46 (dx: 50ns dy; point M43 (4.88802ms, 99.5105mA); at point M44 (2.31097ms, 1.1098uA), it can be seen that the LDO load current in mode A rises from 1uA to 100mA within 50ns, the output voltage fluctuates 682mV instantaneously, the load current falls from 100mA to 1uA within 50ns, and the output voltage changes 2.7V instantaneously.
Transient simulation results for mode B are shown in FIG. 9, where the LDO has an input voltage of 5V and an output of 0.9V, combined with point M57 (3.00349ms, 696.314mV); point M58 (3.7434ms, 895.594mV), the change L4 between point M57 and point M58 (dx: 739.908us dy, 199.281mV s, 269.332V/s); point M59 (6.3434ms, 895.594mV); change value L5 of point M60 (7.00312ms, 1.03264v), point M59 and point M60: (dx: 659.716us dy 137.041mV s, 207.728V/s); point M55 (3.0 ms,1.0 uV); point M56 (3.00005ms, 100.0 mV), point M55 and point M56 variation value L6 (dx: 50.0ns dy 99.999mV s; point M53 (4.88802ms, 99.5105mA); at point M54 (2.31097ms, 1.06238ua), it can be seen that the LDO load current in mode B rises from 1uA to 100mA within 50ns, the output voltage fluctuates instantaneously by 199mV, the load current drops from 100mA to 1uA within 50ns, the output voltage changes instantaneously by 137mV, and the external capacitor greatly reduces the instantaneous change of the output voltage compared to mode a.
Transient simulation results of mode C are shown in FIG. 10, where the LDO with input voltage of 5V and output of 0.9V is combined with point M63 (3.00021ms, 877.901mV); point M64 (3.754369ms, 894.6372mV), point M63 and point M64 variation L7 (dx: 754.1595us dy; point M65 (5.944418ms, 894.6372mV); point M66 (7.000135ms, 910.2952mV), point M65 and point M66 change L8: (dx: 1.055717ms dy; point M67 (3.0 ms,1.0 uV); point M68 (3.00005ms, 100.0 mV), point M67 and point M68 change by a value L9 (dx: 50.14531ns dy, 99.999mV s; point M69 (4.133416ms, 99.40413mA); at point M70 (2.165982ms, 999.3996na), it can be seen that the LDO load current in mode C rises from 1uA to 100mA within 50ns, the output voltage fluctuates instantaneously by 16mV, the load current drops from 100mA to 1uA within 50ns, and the output voltage changes instantaneously by 15.6mV, so that the output voltage change of the invention controls the transient response within 20mV, and the process angle change can be kept within 50 mV; under the same condition, the response of the invention to the output voltage is greatly improved.
In a portable electronic device, due to the limitation of battery capacity, the static power consumption of various chips is made to be relatively low to save electric energy, the static power consumption of the LDO for supplying power is generally controlled within 100uA, when a load is instantly switched from heavy load to light load, the output voltage of the LDO can be instantly increased, an external capacitor is generally adopted for voltage stabilization to reduce the voltage transient problem during switching, even if the external capacitor of the LDO in the traditional structure still has voltage change of hundreds of millivolts, a buffer circuit is generally added in the front stage of a power tube of the LDO to further reduce the voltage, even if the transient voltage still exceeds 100mV, the transient power scheme of the invention with fast transient output voltage response can control the transient voltage within 50mV, and no matter how fast the load is switched in the load carrying capacity range of the LDO, the circuit can always control the voltage fluctuation of the output within 50mV, thereby avoiding the problem that the voltage with long-time overlarge output damages other chips, and also having the following advantages:
1. the applicability is wide;
2. the system itself is not affected;
3. the rapid and accurate detection capability is realized;
4. the detection bandwidth and the system bandwidth are crossed, so that the system has good response capability in the whole range;
5. the energy consumption of the detection part is low.
Although the present invention has been described herein with reference to the illustrated embodiments thereof, which are intended to be preferred embodiments of the present invention, it is to be understood that the invention is not limited thereto, and that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure.
Claims (4)
1. The utility model provides an output voltage quick response's LDO power, its characterized in that includes error amplifier, buffer stage circuit, output and feedback module and detection module, wherein:
the error amplifier is used for comparing an input reference voltage with a feedback signal of the output and feedback module, generating a control signal and outputting the control signal to the buffer stage circuit;
the buffer stage circuit is used for driving the output and feedback module and adjusting the output signal to stop increasing the output voltage of the output and feedback module when receiving the detection signal output by the detection module;
the output and feedback module is used for driving a power tube of the buffer stage circuit to be turned on or turned off according to an output signal of the buffer stage circuit, adjusting output voltage and outputting a feedback signal to the error amplifier;
the detection module is used for outputting a detection signal to the buffer stage circuit after detecting that the instantaneous change of the output voltage exceeds a preset value, and closing the buffer stage circuit after the instantaneous change of the output voltage is smaller than the preset value;
the error amplifier comprises an MOS tube M1, an MOS tube M2, an MOS tube M3, an MOS tube M4, an MOS tube M5, an MOS tube M6, an MOS tube M7, an MOS tube M8, an MOS tube M9, an MOS tube M10, an MOS tube M11 and an MOS tube M12, wherein a grid electrode of the MOS tube M1 is connected with a bias voltage VP1, a grid electrode of the MOS tube M2 is connected with the bias voltage VP2, grid electrodes of the MOS tube M11 and the MOS tube M12 are connected with the bias voltage VN1, grid electrodes of the MOS tube M9 and the MOS tube M10 are connected with the bias voltage VN2, a drain electrode of the MOS tube M1 is connected with a source electrode of the MOS tube M2, a source electrode of the MOS tube M1 is connected with a power supply voltage VCC, a drain electrode of the MOS tube M2 is connected with source electrodes of the MOS tube M3 and the MOS tube M4, a grid electrode of the MOS tube M3 is used as a positive input end of the error amplifier, and a grid electrode of the MOS tube M4 is used as a negative input end of the error amplifier; the drain electrode of the MOS tube M3 is connected with the source electrode of the MOS tube M10 and the drain electrode of the MOS tube M12, and the drain electrode of the MOS tube M4 is connected with the source electrode of the MOS tube M9 and the drain electrode of the MOS tube M11; the source electrodes of the MOS tube M11 and the MOS tube M12 are grounded, the drain electrode of the MOS tube M9 is connected with the drain electrode of the MOS tube M7, the grid electrode of the MOS tube M5 and the grid electrode of the MOS tube M6, the grid electrode of the MOS tube M7 is connected with the grid electrode of the MOS tube M8 and the bias voltage VP2, the source electrode of the MOS tube M7 is connected with the drain electrode of the MOS tube M5, and the drain electrode of the MOS tube M8 is connected with the drain electrode of the MOS tube M10 and serves as the output end of the error amplifier; the source electrode of the MOS tube M8 is connected with the drain electrode of the MOS tube M6, and the source electrodes of the MOS tube M5 and the MOS tube M6 are connected with the source electrode of the MOS tube M1;
the buffer circuit comprises an MOS tube M13, an MOS tube M14, an MOS tube M15, an MOS tube M16, an MOS tube M17 and an MOS tube M18, the grid electrodes of the MOS tube M13 and the MOS tube M16 are connected with a bias voltage VP1, the source electrodes of the MOS tube M13 and the MOS tube M16 are connected with a power supply voltage VCC, the drain electrode of the MOS tube M13 is connected with the source electrode of the MOS tube M14, the drain electrode of the MOS tube M16 is connected with the source electrode of the MOS tube M17, the grid electrodes of the MOS tube M14 and the MOS tube M17 are connected with the bias voltage VP1, the drain electrode of the MOS tube M14 is connected with the source electrode of the MOS tube M15 and the drain electrode of the MOS tube M18 and is connected with the output and feedback module as the output end of the buffer circuit, the grid electrode of the MOS tube M15 is connected with the input end of the buffer circuit and the output end of the error amplifier, the drain electrode of the MOS tube M15 is grounded, the source electrode of the MOS tube M18 is connected with the drain electrode of the MOS tube M17, and the grid electrode of the detection module is connected with the output end of the detection module.
2. The LDO power supply with fast response to output voltage of claim 1, wherein the source of the MOS transistor M10 is further connected to a first terminal of a capacitor C1, and a second terminal of the capacitor C1 is connected to the output voltage of the output and feedback module.
3. The LDO power supply with fast response to output voltage of claim 1, wherein the output and feedback module comprises a MOS transistor M19, a resistor R1 and a resistor R2, the source of the MOS transistor M19 is connected to the supply voltage VCC, the drain of the MOS transistor M19 is connected to the first end of the resistor R1 as the output end of the output and feedback module and to the input end of the detection module, the second end of the resistor R1 is connected to the first end of the resistor R2 and the negative input end of the error amplifier, the second end of the resistor R2 is grounded, and the gate of the MOS transistor M19 is connected to the output end of the buffer stage circuit.
4. The LDO power supply of claim 3, wherein the detection module comprises an amplifier AMP, a resistor R3, a resistor R4, a resistor R5, and a resistor R6, the first end of the resistor R3 is connected to the output terminal of the output and feedback module, the second end of the resistor R3 is connected to the first end of the resistor R4 and the first end of the resistor R6, the second end of the resistor R6 is connected to the positive input terminal of the amplifier AMP, the first end of the capacitor C2, and the first end of the capacitor C3, the second end of the resistor R4 is connected to the first end of the resistor R5 and the negative input terminal of the amplifier AMP, the second end of the capacitor C2 and the second end of the resistor R5 are grounded, the second end of the capacitor C3 is connected to the buffer stage circuit as the output terminal of the detection module, the output terminal of the amplifier AMP is connected to the gates of the MOS transistor M21 and the MOS transistor M22, the drain of the MOS transistor M22 is connected to the drain of the MOS transistor M23 and the gate of the MOS transistor M24, the source of the MOS transistor VCC is connected to the drain of the capacitor M23 and the drain of the MOS transistor M3, and the drain of the capacitor C23 are connected to the drain of the MOS transistor M24.
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