CN115359716B

CN115359716B - Driving circuit carrier, display panel and flat panel display

Info

Publication number: CN115359716B
Application number: CN202210461429.5A
Authority: CN
Inventors: 徐涛; 张秀玉; 顾宇; 高美玲; 赵静; 赵永丰
Original assignee: Kunshan Govisionox Optoelectronics Co Ltd
Current assignee: Kunshan Govisionox Optoelectronics Co Ltd
Priority date: 2016-10-31
Filing date: 2017-07-17
Publication date: 2024-01-26
Anticipated expiration: 2037-07-17
Also published as: CN108022516A; CN108022517A; CN108022515B; CN108022519A; CN106298862A; CN108022514A; CN115359716A; CN108022518A; CN114823609A; CN108022515A

Abstract

The invention provides a driving circuit carrier, a display panel and a flat panel display. The second pins in the display panel correspond to the first pins in the driving circuit carrier, so that bonding quality of the display panel or the driving circuit carrier after expansion can be greatly improved.

Description

Driving circuit carrier, display panel and flat panel display

Technical Field

The present invention relates to the field of display technologies, and in particular, to a driving circuit carrier, a display panel, and a flat panel display.

Background

The flat panel display (Flat Panel Display, FPD) itself is a flat panel without the electron beam tubes of the CRT (Cathode Ray Tube) display, and thus can be made very thin, which is a desirable display. Flat panel displays include Plasma Displays (PDPs), liquid Crystal Displays (LCDs), organic electronic displays (OLEDs), and the like.

Flat panel displays generally include a display panel and a driving circuit that needs to be electrically connected to the display panel to control the display of the display panel. In the prior art, the manner of electrically connecting the driving circuit and the display panel includes COF (Chip On Flex, or Chip On Film), COG (Chip On Glass) and other technologies. The COG technology generally makes a driving circuit on a driving chip, and the driving chip is directly connected with the display panel to realize the electrical connection between the driving circuit and the display panel; the COF technology generally makes a driving circuit on a flip chip film, and the flip chip film is directly connected to a display panel to electrically connect the driving circuit and the display panel.

In COG technology, a driving chip is used as a carrier for carrying connection between a driving circuit and a display panel, and electrical connection between the driving circuit and the display panel is realized by bonding pins (or called leads and output pads) on the driving chip and pins (or called leads and output pads) on the display panel; in COF technology, a flip chip film is used as a carrier for carrying the electrical connection between a driving circuit and a display panel, and the electrical connection between the driving circuit and the display panel is realized by bonding pins on the flip chip film and pins on the display panel. Therefore, the quality of bonding between the pins on the drive circuit carrier and the pins on the display panel described above will be critical.

Disclosure of Invention

The invention aims to provide a driving circuit carrier, a display panel and a flat panel display, so as to improve bonding quality between pins on the driving circuit carrier and pins on the display panel.

In order to solve the above technical problems, the present invention provides a driving circuit carrier, including: the device comprises a substrate and a plurality of first pins arranged on at least one surface of the substrate, wherein all the first pins are arranged along a first datum line; in all the first pins, an extension line of at least one first pin intersects with a second datum line, and the second datum line is perpendicular to the first datum line; each first pin includes opposing first and second ends, wherein a cross-sectional width of the first end is greater than a cross-sectional width of the second end.

Optionally, in the driving circuit carrier, a cross-sectional width of the first pin gradually decreases from the first end to the second end.

Optionally, in the driving circuit carrier, the first pin includes multiple segments, and shapes and/or cross-sectional widths of the segments are different.

Optionally, in the driving circuit carrier, the first pin includes two sections, a first section near the first end and a second section far away from the first end, where in the first section, a cross-sectional width of the first pin is kept unchanged and is the same as a cross-sectional width of the first end; in the second section, the cross-sectional width of the first pin gradually decreases from one end near the first end toward the second end.

Optionally, in the driving circuit carrier, the first pin includes two sections, a first section near the first end and a second section far away from the first end, wherein in the first section, a cross-sectional width of the first pin gradually decreases from the first end to an end near the second end; in the second section, the cross-sectional width of the first pin remains unchanged and is the same as the cross-sectional width of the second end.

Optionally, in the driving circuit carrier, the first pin includes three sections, a first section near the first end, a third section near the second end, and a second section between the first section and the third section, wherein in the first section, a cross-sectional width of the first pin gradually decreases from the first end to an end near the second end; in the second section, the cross-sectional width of the first pin remains unchanged; in the third section, the cross-sectional width of the first pin gradually decreases from one end near the first end toward the second end.

Optionally, in the driving circuit carrier, all the first pins form a plurality of first pin groups, and each first pin group includes at least one first pin; each first pin group intersects or is parallel to the second datum line; when one first pin group is intersected with the second datum line, extension lines of all first pins of the same first pin group are intersected with the second datum line and at the same point; when one first pin group is parallel to the second datum line, all first pins of the same first pin group are parallel to or coincide with the second datum line.

Optionally, in the driving circuit carrier, the driving circuit carrier is a flip chip film or a driving chip.

The invention also provides a display panel, which comprises a non-display area, wherein a plurality of second pins are arranged on the non-display area, and all the second pins are arranged along a third datum line; in all the second pins, the extension line of at least one second pin is intersected with a fourth datum line, the intersection points are different, and the fourth datum line is perpendicular to the third datum line; each second pin includes opposing first and second ends, wherein a cross-sectional width of the first end is greater than a cross-sectional width of the second end.

The present invention also provides a flat panel display including:

a drive circuit carrier as described above; and

A display panel as described above; wherein,

and a first pin in the driving circuit carrier is completely or partially attached to a second pin in the display panel, and the second datum line and the fourth datum line are overlapped.

In the driving circuit carrier, the display panel and the flat panel display provided by the invention, the property of the base material attached to the driving circuit carrier is the greatest through the design of the first pin of the driving circuit carrier, so that the tensile deformation of the base material is greatly compensated. The second pins in the display panel correspond to the first pins in the driving circuit carrier, so that bonding quality of the display panel or the driving circuit carrier after expansion can be greatly improved.

Drawings

Fig. 1 is a schematic structural diagram of a driving circuit carrier according to a first embodiment of the present invention;

fig. 2 is a schematic structural diagram of a display panel according to a first embodiment of the invention;

fig. 3 is a schematic structural diagram of a driving circuit carrier according to a second embodiment of the present invention;

fig. 4 is a schematic structural diagram of a display panel according to a second embodiment of the invention;

fig. 5 is a schematic structural diagram of a driving circuit carrier according to a third embodiment of the present invention;

fig. 6 is a schematic structural diagram of a display panel according to a third embodiment of the present invention;

fig. 7 is a schematic structural diagram of a driving circuit carrier according to a fourth embodiment of the present invention;

fig. 8 is a schematic structural diagram of a display panel according to a fourth embodiment of the present invention;

fig. 9 is a schematic structural diagram of a driving circuit carrier according to a fifth embodiment of the present invention;

fig. 10 is a schematic structural diagram of a display panel according to a fifth embodiment of the present invention;

fig. 11 is a schematic structural diagram of a driving circuit carrier according to a sixth embodiment of the present invention;

fig. 12 is a schematic structural diagram of a display panel according to a sixth embodiment of the present invention;

fig. 13 is a schematic structural view of a driving circuit carrier according to a seventh embodiment of the present invention;

fig. 14 is a schematic structural diagram of a display panel according to a seventh embodiment of the present invention;

fig. 15 is a schematic structural diagram of a driving circuit carrier according to an eighth embodiment of the present invention;

Fig. 16 is a schematic structural view of a display panel according to an eighth embodiment of the present invention;

fig. 17 is a schematic diagram of a driving circuit carrier according to a ninth embodiment of the present invention;

fig. 18 is a schematic structural view of a display panel according to a ninth embodiment of the present invention;

FIG. 19 is a schematic diagram of a driving circuit carrier according to a tenth embodiment of the present invention;

fig. 20 is another schematic structural view of a driving circuit carrier according to the tenth embodiment of the present invention;

FIG. 21 is a schematic diagram of a display panel according to a tenth embodiment of the present invention;

fig. 22 is another schematic structural view of a display panel according to a tenth embodiment of the present invention;

fig. 23 is a schematic structural view of a driving circuit carrier according to an eleventh embodiment of the present invention;

fig. 24 is a schematic structural view of a display panel according to an eleventh embodiment of the present invention;

FIG. 25 is a schematic diagram of a bonding apparatus according to an eleventh embodiment of the present invention;

wherein, 1-driving circuit carrier; 10-a substrate;

11. 11a, 11b, 11c, 11 d-first pins; 110-a first end; 111-second end;

12-a first alignment mark;

l1-a first datum line; l2-a second baseline;

a1, A2, A3, A4, A5, A6, A7, A8 and A9 are the first pin group;

d10, D11, D12, D13, D14, D15, D16, D17-intersection;

ang1, ang 2-angle;

2-a display panel; 20-non-display area; a 20' -display region;

21-a second pin; 210-a first end; 211-a second end;

22-a second alignment mark; 22a, 22b, 22 c-alignment structures;

l3-a third baseline; l4-fourth baseline;

b1, B2, B3, B4, B5, B6, B7, B8, B9-a first pin set;

d20, D21, D22, D23, D24, D25, D26, D27-intersection;

3-bonding the device; 30-a grabbing unit; 31-a compensation unit; 32-a mobile unit; 33-bonding unit.

Detailed Description

The driving circuit carrier, the display panel and the flat panel display according to the present invention will be described in further detail with reference to the accompanying drawings and embodiments. Advantages and features of the invention will become more apparent from the following description and from the claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.

The core idea of the invention is to provide a driving circuit carrier comprising: the device comprises a substrate and a plurality of first pins arranged on at least one surface of the substrate, wherein all the first pins are arranged along a first datum line; and in all the first pins, the extension line of at least one first pin is intersected with a second datum line, and the second datum line is perpendicular to the first datum line. I.e. in all the first pins, at least one of the first pins is inclined (i.e. non-perpendicular) with respect to the first reference line, whereby the spacing at different positions between an inclined first pin and its neighboring first pin varies, i.e. the spacing between an inclined first pin and its neighboring first pin varies from the end closest to the intersection point to the end distant from the intersection point, wherein the spacing is the distance between the midpoints of the neighboring two first pins in the direction of the first reference line. Therefore, the driving circuit carrier can better resist the expansion of the base material, namely, compared with the traditional driving circuit carrier, under the condition that the base material expands, the first pin of the driving circuit carrier can be well attached to the second pin of the display panel.

Further, each first pin includes a first end and a second end opposite to each other, wherein a cross-sectional width of the first end is greater than a cross-sectional width of the second end, so that when the driving circuit carrier moves in a direction of the second reference line to compensate for the offset in the direction of the first reference line, a bonding area between the first pin of the driving circuit carrier and the second pin of the display panel can be increased in the direction of the first reference line, thereby improving a bonding quality between the first pin of the driving circuit carrier and the second pin of the display panel and improving a quality of bonding of the driving circuit carrier on the display panel.

Further, a first alignment mark is arranged on the first pin located at the outermost side, so that the first pin of the driving circuit carrier and the second pin of the display panel can be attached more quickly and accurately by referring to the first alignment mark.

Correspondingly, the invention also provides a display panel, which comprises a non-display area, wherein a plurality of second pins are arranged on the non-display area, and all the second pins are arranged along a third datum line; and in all the second pins, the extension line of at least one second pin is intersected with a fourth datum line, and the fourth datum line is perpendicular to the third datum line.

In the invention, the second pins of the display panel correspond to the first pins of the driving circuit carrier, and specifically comprise that the inclination direction and the inclination angle of each second pin relative to the third datum line are the same as the inclination direction and the inclination angle of the corresponding first pin relative to the first datum line; the shape and the section width of each second pin are the same as those of the corresponding first pin; the spacing between two adjacent second pins is the same as the spacing between two corresponding adjacent first pins, and so on.

In the invention, the first ends of all the first pins arranged along the first datum line face the display panel, and the first ends of the second pins arranged along the third datum line face the driving circuit carrier, namely, before the driving circuit carrier is bonded on the display panel, the first ends of the first pins and the first ends of the second pins are opposite/close to each other; after the driving circuit carrier is bonded to the display panel, under the condition of complete bonding, the first end of the first pin is opposite to/close to the second end of the second pin, and the second section of the first pin is opposite to/close to the first end of the second pin.

In addition, the invention also provides a flat panel display and a manufacturing method thereof, by providing the driving circuit carrier; providing the display panel; aligning a first pin on the driving circuit carrier with a second pin on the display panel according to a first alignment mark on the driving circuit carrier and a second alignment mark on the display panel; and attaching the first pins and the second pins to enable the driving circuit carrier to be bonded on the display panel, so that a flat panel display is formed.

Further, the present invention also provides a binding device, where the binding device includes: the device comprises a grabbing unit, a compensation unit, a moving unit and a bonding unit, wherein the grabbing unit is used for the distance between two first alignment marks and the distance between two second alignment marks; the compensation unit is used for obtaining compensation amount according to the distance difference between the two first alignment marks and the distance between the two second alignment marks; the moving unit is used for moving the driving circuit carrier in the direction of a second datum line, and the moving distance is the magnitude of the compensation quantity, so that the first pin and the second pin are aligned; the bonding unit is used for attaching the first pins and the second pins, so that the driving circuit carrier is bonded on the display panel, and bonding between the driving circuit carrier and the display panel can be realized rapidly and reliably through the bonding equipment.

In addition, in the invention, the driving circuit carrier can be a flip chip film, a driving chip or other structures carrying driving circuits; the display panel may be a rigid display panel, a flexible display panel, or the like.

The driving circuit carrier, the display panel, the flat panel display, the bonding apparatus and the method according to the present invention will be further described with reference to the accompanying drawings, wherein, for clarity of illustration, only a few first pins/second pins are schematically shown, it should be understood that in actual products, the number of first pins/second pins on a product can be typically hundreds to thousands; furthermore, for clarity of illustration, there is often a discrepancy between the angles shown in the drawings and the angles characterized thereby, it being understood that the drawings are merely schematic.

[ embodiment one ]

Drive circuit carrier

Fig. 1 is a schematic structural diagram of a driving circuit carrier according to a first embodiment of the invention. As shown in fig. 1, in the embodiment of the present application, the driving circuit carrier 1 includes a substrate 10 and a plurality of first pins 11 disposed on at least one surface of the substrate 10, where all the first pins 11 are arranged L1 along a first reference line; of all the first leads 11, at least one extension line of the first lead 11 intersects with a second reference line L2, and the second reference line L2 is perpendicular to the first reference line L1.

In the embodiment of the present application, the first reference line L1 bisects each first lead 11 in the direction of the second reference line L2. In this embodiment, the number of the first pins 11 is an even number, and the second reference line L2 is located between the middle two first pins 11. Further, the second reference line L2 is located at a middle position of the base material 10.

With continued reference to fig. 1, in this embodiment, all the first pins 11 are arranged in an isosceles trapezoid, and further, an upper base (a shorter side) of the isosceles trapezoid faces the display panel, that is, after the driving circuit carrier 1 is bonded to the display panel, the upper base of the isosceles trapezoid is closer to the display area of the display panel. Here, the first end 110 of each first pin 11 is close to the display panel, and the second end 111 of each first pin 11 is far from the display panel.

In the embodiment of the present application, the cross-sectional width of each first pin 11 in the direction of the first reference line L1 is the same, that is, the cross-sectional width of each first pin 11 from the first end 110 to the second end 111 is the same. Further, each first lead 11 is rectangular or parallelogram in shape. Each first leg 11 comprises a pair of first sides and a pair of second sides, wherein each pair of first sides (or an extension of each pair of first sides) intersects the first reference line L1, and each pair of second sides is parallel to the first reference line L1, where a long side of a rectangle or a parallelogram intersects the first reference line L1, and a short side of the rectangle or the parallelogram is parallel to the first reference line L1.

With continued reference to fig. 1, in the embodiment of the present application, the number of the first pins 11 is eight, and four first pin groups are formed by eight first pins 11, where each first pin group includes two first pins 11, here, a first pin group A1, a first pin group A2, a first pin group A3, and a first pin group A4, respectively.

In this embodiment, all four first lead groups intersect with the second reference line L2. Further, all first pins 11 (here, two first pins 11) in the same first pin group intersect at the same point of the second reference line L2, and different first pin groups intersect at different points of the second reference line L2. That is, the two first leads 11 in the first lead group A1 all intersect with the intersection point D10 on the second reference line L2, the two first leads 11 in the first lead group A2 all intersect with the intersection point D11 on the second reference line L2, the two first leads 11 in the first lead group A3 all intersect with the intersection point D12 on the second reference line L2, and the two first leads 11 in the first lead group A4 all intersect with the intersection point D13 on the second reference line L2.

Further, all the first pins 11 of the same first pin group are symmetrically distributed on two sides of the second reference line L2. In this case, that is to say, two first pins 11 of the first pin group A1 are symmetrical about the second reference line L2, two first pins 11 of the first pin group A2 are symmetrical about the second reference line L2, two first pins 11 of the first pin group A3 are symmetrical about the second reference line L2, and two first pins 11 of the first pin group A4 are symmetrical about the second reference line L2. In other embodiments of the present application, all the first pins of the same first pin group may be distributed only on two sides of the second reference line L2 and not symmetrical.

In general, the material properties of the substrate 10 at the symmetrical positions are the same/similar, i.e. two symmetrical positions on the substrate 10 tend to expand simultaneously or do not expand simultaneously, so that it is preferable that all the first pins 11 of the same first pin group are symmetrically distributed on both sides of the second reference line L2. This allows the substrate 10 to be more favorably bonded to each other, and compensates for expansion/stretching deformation of the substrate 10.

Preferably, among all the first leads 11, an angle between an extension line of the first lead 11 farthest from and intersecting the second reference line L2 and the second reference line L2 is 5 ° to 15 °. Further, when one first lead group intersects with the second reference line L2, in the same first lead group, the distance from the intersection point to the distal end of the first lead 11 farthest from the second reference line L2 satisfies the formula:

R ₁ ＝360×W ₁ ×M ₁ /(π×θ ₁ )

wherein the distal end is the end of the first pin 11 away from the intersection point, R ₁ A distance from the intersection point to the distal end of the first lead 11 farthest from the second reference line L2; w (W) ₁ The cross-sectional width of the first lead 11 (here, the cross-sectional width of the first lead 11 may be taken through the first reference line L1, or an average value of the cross-sectional widths of the first lead 11 in the direction of the first reference line L1 may be taken); m is M ₁ For the number of first pins 11; pi is a constant; θ ₁ Is the angle between the extension line of the first pin 11 farthest from the second reference line L2 and the second reference line L2.

Display panel

Correspondingly, the present embodiment also provides a display panel, and in particular, please refer to fig. 2, which is a schematic structural diagram of a display panel according to a first embodiment of the present invention. As shown in fig. 2, the display panel 2 includes a non-display area 20, and a plurality of second pins 21 are disposed on the non-display area 20, and all the second pins 21 are arranged along a third reference line L3; of all the second leads 21, at least one extension line of the second lead 21 intersects with a fourth reference line L4, and the fourth reference line L4 is perpendicular to the third reference line L3. Here, the second pin 21 corresponds to the first pin 11.

Specifically, the third reference line L3 bisects each second leg 21 in the direction of the fourth reference line L4. In this embodiment, the number of the second pins 21 is an even number, and the fourth reference line L4 is located between the middle two second pins 21. Further, the fourth reference line L4 is located at a middle position of the non-display area 20.

With continued reference to fig. 2, in this embodiment, all the second pins 21 are arranged in an isosceles trapezoid, and further, the lower base (longer side) of the isosceles trapezoid faces the driving circuit carrier 1, that is, the upper base of the isosceles trapezoid is closer to the display area 20' of the display panel 2. Here, the first end 210 of each second pin 21 is far from the display area 20', and the second end 211 of each second pin 21 is near to the display area 20'.

In the embodiment of the present application, the cross-sectional width of each second pin 21 in the direction of the third reference line L3 is the same, that is, the cross-sectional width of each second pin 21 from the first end 210 to the second end 211 is the same. Further, each of the second pins 21 is rectangular or parallelogram in shape. Each second leg 21 comprises a pair of first sides and a pair of second sides, wherein each pair of first sides (or an extension of each pair of first sides) intersects the third reference line L3, and each pair of second sides is parallel to the third reference line L3, where a long side of a rectangle or a parallelogram intersects the third reference line L3, and a short side of the rectangle or the parallelogram is parallel to the third reference line L3.

With continued reference to fig. 2, in the embodiment of the present application, the number of the second pins 21 is eight, and four second pin groups are formed by the eight second pins 21, where each second pin group includes two second pins 21, and here, the second pin group B1, the second pin group B2, the second pin group B3, and the second pin group B4 respectively.

In this embodiment, all four second lead groups intersect with the fourth reference line L4. Further, all second pins 21 (here, two second pins 21) in the same second pin group intersect at the same point of the fourth reference line L4, and different second pin groups intersect at different points of the fourth reference line L4. That is, two second leads 21 in the second lead group B1 each intersect with an intersection point D20 on the fourth reference line L4, two second leads 21 in the second lead group B2 each intersect with an intersection point D21 on the fourth reference line L4, two second leads 21 in the second lead group B3 each intersect with an intersection point D22 on the fourth reference line L4, and two second leads 21 in the second lead group B4 each intersect with an intersection point D23 on the fourth reference line L4.

Further, all the second pins 21 of the same second pin group are symmetrically distributed on two sides of the fourth reference line L4. Here, that is, two second pins 21 in the second pin group B1 are symmetrical about the fourth reference line L4, two second pins 21 in the second pin group B2 are symmetrical about the fourth reference line L4, two second pins 21 in the second pin group B3 are symmetrical about the fourth reference line L4, and two second pins 21 in the second pin group B4 are symmetrical about the fourth reference line L4. In other embodiments of the present application, all the first pins of the same second pin group may be distributed only on two sides of the fourth reference line L4 and not symmetrical.

Preferably, among all the second leads 21, an angle between an extension line of the second lead 21 farthest from and intersecting the fourth reference line L4 and the fourth reference line L4 is 5 ° to 15 °. Further, when one second lead group intersects with the fourth reference line L4, in the same second lead group, the distance from the intersection point to the distal end of the second lead 21 farthest from the fourth reference line L4 satisfies the formula:

R ₂ ＝360×W ₂ ×M ₂ /(π×θ ₂ )

wherein the distal end is the end of the second pin 21 away from the intersection point, R ₂ A distance from the intersection point to the distal end of the second leg 21 farthest from the fourth reference line L4; w (W) ₂ The cross-sectional width of the second pin 21 (here, the cross-sectional width of the second pin 21 may be taken through the third reference line L3, or an average value of the cross-sectional widths of the second pin 21 in the direction of the third reference line L3 may be taken); m is M ₂ For the number of the second pins 21The method comprises the steps of carrying out a first treatment on the surface of the Pi is a constant; θ ₂ Is the angle between the extension line of the second pin 21 farthest from the fourth reference line L4 and the fourth reference line L4.

Flat panel display

Correspondingly, the embodiment also provides a flat panel display. Referring to fig. 1 and 2 in combination, in an embodiment of the present application, the flat panel display includes a driving circuit carrier 1 and a display panel 2, wherein,

The driving circuit carrier 1 includes a substrate 10, a plurality of first pins 11 disposed on at least one surface of the substrate 10, and all the first pins 11 are arranged L1 along a first reference line; of all the first pins 11, at least one extension line of the first pin 11 intersects with a second reference line L2, and the second reference line L2 is perpendicular to the first reference line L1;

the display panel 2 includes a non-display area 20, and a plurality of second pins 21 are disposed on the non-display area 20, and all the second pins 21 are arranged along a third reference line L3; of all the second pins 21, an extension line of at least one of the second pins 21 intersects with a fourth reference line L4, the fourth reference line L4 being perpendicular to the third reference line L3;

the first pins 11 in the driving circuit carrier 1 are completely or partially attached to the second pins 21 in the display panel 2, and the second reference line L2 and the fourth reference line L4 are overlapped.

[ example two ]

Drive circuit carrier

Fig. 3 is a schematic structural diagram of a driving circuit carrier according to a second embodiment of the invention. As shown in fig. 3, in the embodiment of the present application, the driving circuit carrier 1 includes a substrate 10 and a plurality of first pins 11 disposed on at least one surface of the substrate 10, where all the first pins 11 are arranged L1 along a first reference line; of all the first leads 11, at least one extension line of the first lead 11 intersects with a second reference line L2, and the second reference line L2 is perpendicular to the first reference line L1.

In the embodiment of the present application, the first end 110 of each first pin 11 is close to the display panel, and the second end 111 of each first pin 11 is far from the display panel. The cross-sectional width of each first pin 11 in the direction of the first reference line L1 is the same, i.e., the cross-sectional width of each first pin 11 from the first end 110 to the second end 111 is the same. Further, each first lead 11 is rectangular or parallelogram in shape. Each first leg 11 comprises a pair of first sides and a pair of second sides, wherein each pair of first sides (or an extension of each pair of first sides) intersects the first reference line L1, and each pair of second sides is parallel to the first reference line L1, where a long side of a rectangle or a parallelogram intersects the first reference line L1, and a short side of the rectangle or the parallelogram is parallel to the first reference line L1.

With continued reference to fig. 3, in the embodiment of the present application, the number of the first pins 11 is twelve, and the twelve first pins 11 form three first pin groups, where each first pin group includes four first pins 11, here, a first pin group A1, a first pin group A2, and a first pin group A3, respectively.

In this embodiment, the first lead group A1 and the first lead group A2 intersect the second reference line L2, and the first lead group A3 is parallel to the second reference line L2. Further, the first pin group A1 and the first pin group A2 intersect at different points of the second reference line L2. Specifically, the four first pins 11 in the first pin group A1 all intersect the intersection point D10 on the second reference line L2, the four first pins 11 in the first pin group A2 all intersect the intersection point D11 on the second reference line L2, and the four first pins 11 in the first pin group A3 all are parallel to the second reference line L2.

Wherein the first pin group A3 is located between the first pin group A1 and the first pin group A2. Further, all the first pins 11 in the first pin group A1 are located on the same side as the second reference line L2; all first pins 11 in the first pin group A2 are located on the same side of the second reference line L2, and all first pins 11 in the first pin group A2 and all first pins 11 in the first pin group A1 are located on two sides of the second reference line L2 respectively; four first pins 11 in the first pin group A3 are respectively located at two sides of the second reference line L2, that is, the second reference line L2 is located in the first pin group A3.

With continued reference to fig. 3, in the embodiment of the present application, the cross-sectional widths of the four first pins 11 in the first pin group A1 taken by the first reference line L1 are the same; the cross-sectional widths of the four first pins 11 in the first pin group A2 taken by the first reference line L1 are the same; the cross-sectional widths of the four first pins 11 in the first pin group A3 taken by the first reference line L1 are the same. Further, the cross-sectional width of each first lead 11 in the first lead group A3 taken by the first reference line L1 is smaller than the cross-sectional width of each first lead 11 in the first lead group A1 taken by the first reference line L1, and the cross-sectional width of each first lead 11 in the first lead group A1 taken by the first reference line L1 is smaller than the cross-sectional width of each first lead 11 in the first lead group A2 taken by the first reference line L1.

Here, by designing the cross-sectional width of the first pin 11 differently, the material and performance of different substrates 10 can be attached, and the expansion/stretching deformation of the substrate 10 at different positions can be optimally compensated.

Here, in the first pin group A1 or the second pin group A2, it is preferable that the distance from the intersection point D10 or the intersection point D11 to the distal end of the first pin 11 farthest from the second reference line L2 satisfies the formula:

R ₁ ＝360×W ₁ ×M ₁ /(π×θ ₁ )

Wherein the distal end is one end of the first pin 11 away from the intersection point D10 or the intersection point D11, R ₁ For the intersection point D10 or the intersection points D11 to DThe distance of the distal end of the first leg 11 furthest from the second reference line L2; w (W) ₁ Is the cross-sectional width of the first pin 11; m is M ₁ For the number of first pins 11; pi is a constant; θ ₁ Is the angle between the extension line of the first pin 11 farthest from the second reference line L2 and the second reference line L2. Preferably, θ ₁ The value of (2) is 5-15 degrees.

Display panel

Correspondingly, the present embodiment also provides a display panel, and in particular, please refer to fig. 4, which is a schematic structural diagram of a display panel according to a second embodiment of the present invention. As shown in fig. 4, the display panel 2 includes a non-display area 20, and a plurality of second pins 21 are disposed on the non-display area 20, and all the second pins 21 are arranged along a third reference line L3; of all the second leads 21, at least one extension line of the second lead 21 intersects with a fourth reference line L4, and the fourth reference line L4 is perpendicular to the third reference line L3. Here, the second pin 21 corresponds to the first pin 11, and the second pin 21 may refer to the first pin 11 and the first embodiment in the present embodiment, which will not be described in detail.

Flat panel display

Correspondingly, the embodiment also provides a flat panel display. Referring to fig. 3 and fig. 4 in combination, in the embodiment of the present application, the flat panel display includes a driving circuit carrier 1 and a display panel 2, a first pin 11 in the driving circuit carrier 1 is completely or partially attached to a second pin 21 in the display panel 2, and the second reference line L2 and the fourth reference line L4 are overlapped.

[ example III ]

Drive circuit carrier

Fig. 5 is a schematic structural diagram of a driving circuit carrier according to a third embodiment of the invention. As shown in fig. 5, in the embodiment of the present application, the driving circuit carrier 1 includes a substrate 10 and a plurality of first pins 11 disposed on at least one surface of the substrate 10, and all the first pins 11 are arranged L1 along a first reference line; of all the first leads 11, at least one extension line of the first lead 11 intersects with a second reference line L2, and the second reference line L2 is perpendicular to the first reference line L1.

With continued reference to fig. 5, in the embodiment of the present application, the number of the first pins 11 is twelve, and twelve first pins 11 form two first pin groups, namely a first pin group A1 and a first pin group A2, wherein the first pin group A1 includes eight first pins 11, and the first pin group A2 includes four first pins 11.

In this embodiment, the first lead set A1 intersects the second reference line L2, and the first lead set A2 is parallel to the second reference line L2. Specifically, eight first pins 11 in the first pin group A1 all intersect with an intersection point D10 on the second reference line L2, and four first pins 11 in the first pin group A2 all are parallel to the second reference line L2. Wherein the first pin group A2 is located in the first pin group A1. Further, the first pin group A1 and the first pin group A2 are symmetrical with respect to the second reference line L2.

In the first lead group A1, an included angle between an extension line of the first lead 11 close to the second reference line L2 and the second reference line L2 is smaller than an included angle between an extension line of the first lead 11 far from the second reference line L2 and the second reference line L2. Preferably, the included angle between the extension line of the first lead 11 and the second reference line L2 is gradually increased from the first lead 11 closest to the second reference line L2 to the first lead 11 farthest from the second reference line L2. Wherein, from the first pin 11 closest to the second reference line L2 to the first pin 11 farthest from the second reference line L2, the increase amplitude of the angle between the extension line of the first pin 11 and the second reference line L2 is the same or different. When the increasing amplitude of the angle between the extension line of the first lead 11 and the second reference line L2 is different from the first lead 11 closest to the second reference line L2 to the first lead 11 farthest from the second reference line L2, the increasing amplitude of the angle between the extension line of the first lead 11 and the second reference line L2 may be larger or smaller.

Here, the first lead group A1 is symmetrical with respect to the second reference line L2, and thus, the first leads 11 in the first lead group A1 on both sides of the second reference line L2 have the same angular relationship, and thus, only the first leads 11 in the first lead group A1 on one side of the second reference line L2 are further described in the present embodiment.

The first lead group A1 on the side of the second reference line L2 includes four first leads 11, and here, for convenience of description, from the first lead 11 closest to the second reference line L2 to the first lead 11 farthest from the second reference line L2 are respectively referred to as a first lead 11a, a first lead 11b, a first lead 11c, and a first lead 11d, and if the increase of the angle between the extension line of the first lead 11 and the second reference line L2 is the same from the first lead 11 closest to the second reference line L2 to the first lead 11 farthest from the second reference line L2, the angle between the first lead 11a and the second reference line L2 is ang1, the angle between the first lead 11b and the second reference line L2 is (ang 1+ang 2), the angle between the first lead 11c and the second reference line L2 is (ang 1+ang 2), and the angle between the first lead 11d and the second reference line L2 is (ang 1+ang 2).

In this embodiment, the second reference line L2 is located in the middle or near the middle of the substrate 10, and accordingly, the first pins 11 located at the edge positions (or two side positions) of the substrate 10 have a larger inclination with respect to the first reference line L1 than the first pins 11 located at the middle position of the substrate 10. In general, the edge position of the substrate 10 is relatively easy to stretch and deform (i.e., is easy to expand), and the middle position of the substrate 10 is not easy to stretch and deform or the deformation amount of the stretch and deformation is smaller than the deformation amount of the stretch and deformation at the two side positions of the substrate 10.

Accordingly, the substrate 10 can be attached to the substrate 10 at the maximum by gradually increasing the angle between the extension line of the first lead 11 and the second reference line L2 from the first lead 11 closest to the second reference line L2 to the first lead 11 farthest from the second reference line L2, thereby greatly compensating the tensile strain generated in the substrate 10.

In this embodiment of the present application, in the plurality of first pins 11, the intervals between two adjacent first pins 11 are equal, that is, the intervals between two adjacent first pins 11 in the first pin group A1 are equal, the intervals between two adjacent first pins 11 in the first pin group A2 are equal, and the intervals between two adjacent first pins 11 respectively belong to the first pin group A1 and the first pin group A2 are also equal. In other embodiments of the present application, the distance between two adjacent first pins 11 near the second reference line L2 may be smaller than the distance between two adjacent first pins 11 far from the second reference line L2, or the distance between two adjacent first pins 11 near the second reference line L2 may be larger than the distance between two adjacent first pins 11 far from the second reference line L2. Further, the spacing between two adjacent first pins 11 close to the second reference line L2 may be smaller than the spacing between two adjacent first pins 11 far from the second reference line L2 in all the first pins 11; it is also possible that in the first lead group A1, the pitch between two adjacent first leads 11 close to the second reference line L2 is smaller than the pitch between two adjacent first leads 11 far from the second reference line L2, and in the second lead group A2, the pitches between all (four) first leads 11 are equal. The distance between two adjacent first pins 11 refers to the distance between the midpoints of the two adjacent first pins 11 in the direction of the first reference line L1 (i.e., the midpoints of two line segments formed by overlapping portions of the two adjacent first pins 11 and the first reference line L1) along the first reference line L1.

With continued reference to fig. 5, in the embodiment of the present application, the cross-sectional widths of all the first pins 11 are equal, that is, the cross-sectional widths of eight first pins 11 in the first pin group A1 are equal, the cross-sectional widths of four first pins 11 in the second pin group A2 are equal, and the cross-sectional widths of the first pins 11 in the first pin group A1 are equal to the cross-sectional widths of the first pins 11 in the second pin group A2. In other embodiments of the present application, the width of the cross section of the first lead 11 near the second reference line L2 may be smaller than the width of the cross section of the first lead 11 far from the second reference line L2, or the width of the cross section of the first lead 11 near the second reference line L2 may be larger than the width of the cross section of the first lead 11 far from the second reference line L2. Further, the width of the cross section of the first lead 11 close to the second reference line L2 may be smaller than the width of the cross section of the first lead 11 far from the second reference line L2 among all the first leads 11; the first lead 11 near the second reference line L2 may have a smaller cross-sectional width than the first lead 11 far from the second reference line L2 in the first lead group A1, and all (four) first leads 11 may have the same cross-sectional width in the second lead group A2. Preferably, the cross-sectional width of the first lead 11 increases gradually from the first lead 11 closest to the second reference line L2 to the first lead 11 farthest from the second reference line L2. Here, the cross-sectional width of the first lead 11 may be taken by the first reference line L1, that is, the length of the portion where the first reference line L1 overlaps the first lead 11 is the cross-sectional width of the first lead 11.

Here, in the first lead group A1, it is preferable that the distance from the intersection point D10 to the distal end of the first lead 11 farthest from the second reference line L2 satisfies the formula:

R ₁ ＝360×W ₁ ×M ₁ /(π×θ ₁ )

wherein the distal end is the end of the first pin 11 away from the intersection point D10, R ₁ A distance from the intersection point D10 to the distal end of the first leg 11 farthest from the second reference line L2; w (W) ₁ Is the cross-sectional width of the first pin 11; m is M ₁ For the number of first pins 11; pi is a constant; θ ₁ Is the angle between the extension line of the first pin 11 farthest from the second reference line L2 and the second reference line L2. Preferably, θ ₁ The value of (2) is 5-15 degrees.

Display panel

Correspondingly, the present embodiment also provides a display panel, and in particular, please refer to fig. 6, which is a schematic structural diagram of a display panel according to a third embodiment of the present invention. As shown in fig. 6, the display panel 2 includes a non-display area 20, and a plurality of second pins 21 are disposed on the non-display area 20, and all the second pins 21 are arranged along a third reference line L3; of all the second leads 21, at least one extension line of the second lead 21 intersects with a fourth reference line L4, and the fourth reference line L4 is perpendicular to the third reference line L3. Here, the second pin 21 corresponds to the first pin 11, and the second pin 21 may refer to the first pin 11 and the first embodiment in the present embodiment, which will not be described in detail.

Flat panel display

Correspondingly, the embodiment also provides a flat panel display. Referring to fig. 5 and fig. 6 in combination, in the embodiment of the present application, the flat panel display includes a driving circuit carrier 1 and a display panel 2, a first pin 11 in the driving circuit carrier 1 is completely or partially attached to a second pin 21 in the display panel 2, and the second reference line L2 and the fourth reference line L4 are overlapped.

[ example IV ]

Drive circuit carrier

Fig. 7 is a schematic structural diagram of a driving circuit carrier according to a fourth embodiment of the invention. As shown in fig. 7, in the embodiment of the present application, the driving circuit carrier 1 includes a substrate 10 and a plurality of first pins 11 disposed on at least one surface of the substrate 10, and all the first pins 11 are arranged L1 along a first reference line; of all the first leads 11, at least one extension line of the first lead 11 intersects with a second reference line L2, and the second reference line L2 is perpendicular to the first reference line L1.

With continued reference to fig. 7, in the embodiment of the present application, the number of the first pins 11 is twenty-eight, and twenty-eight first pins 11 form four first pin groups, which are a first pin group A1, a first pin group A2, a first pin group A3, and a first pin group A4, respectively, where the first pin group A1 includes eight first pins 11, the first pin group A2 includes eight first pins 11, the first pin group A3 includes eight first pins 11, and the first pin group A4 includes four first pins 11.

In this embodiment, the first lead group A1, the first lead group A2, and the first lead group A3 all intersect with the second reference line L2 and intersect with the same intersection point D10; the first pin group A4 is parallel to the second reference line L2. Further, the first pin group A2 is located in the first pin group A3, the first pin group A1 is located in the first pin group A2, the first pin group A4 is located in the first pin group A1, and the first pin group A1, the first pin group A2, the first pin group A3 and the first pin group A4 are symmetrical with respect to the second reference line L2.

Wherein, in each first lead group (i.e. in the first lead group A1, in the first lead group A2, and in the first lead group A3), an angle between an extension line of the first lead 11 close to the second reference line L2 and the second reference line L2 is smaller than an angle between an extension line of the first lead 11 far from the second reference line L2 and the second reference line L2. Preferably, the included angle between the extension line of the first lead 11 and the second reference line L2 is gradually increased from the first lead 11 closest to the second reference line L2 to the first lead 11 farthest from the second reference line L2. Wherein, from the first pin 11 closest to the second reference line L2 to the first pin 11 farthest from the second reference line L2, the increase amplitude of the angle between the extension line of the first pin 11 and the second reference line L2 is the same or different. When the increasing amplitude of the angle between the extension line of the first lead 11 and the second reference line L2 is different from the first lead 11 closest to the second reference line L2 to the first lead 11 farthest from the second reference line L2, the increasing amplitude of the angle between the extension line of the first lead 11 and the second reference line L2 may be larger or smaller.

Further, between the first lead group and the first lead group, the increase of the angle between the extension line of the first lead 11 and the second reference line L2 is preferably greater from the first lead group closest to the second reference line L2 to the first lead group farthest from the second reference line L2.

Further, in all the first pins 11, at least two first pins 11 have different cross-sectional widths taken by the first reference line L1. By designing the cross-sectional widths of the plurality of first pins 11 differently, the properties of the substrate 10 can be better adhered. In this embodiment of the present application, the cross-sectional widths of the plurality of first pins 11 of the same first pin group taken by the first reference line L1 are the same, and between the first pin group and the first pin group, the cross-sectional width of the first pin 11 taken by the first reference line L1 becomes larger from the first pin group closest to the second reference line L2 to the first pin group farthest from the second reference line L2; in the same first lead group, the pitches of two adjacent first leads 11 at the first reference line L1 are the same, and the pitches of two adjacent first leads 11 at the first reference line L1 are increased from the first lead group closest to the second reference line L2 to the first lead group farthest from the second reference line L2 between the first lead group and the first lead group.

Here, the first lead group A1, the first lead group A2 and the first lead group A3 are symmetrical with respect to the second reference line L2, and thus the first lead groups A1, A2 and 11 on both sides of the second reference line L2 have the same angular relationship, and thus only the first lead groups A1, A2 and 11 on one side of the second reference line L2 are further described in this embodiment.

For example, in the first pin group A1 on one side, four first pins 11 are included, and here, for convenience of description, from the closest to the second reference line L2 to the farthest from the second reference line L2, they are respectively referred to as a first pin 11a-A1, a first pin 11b-A1, a first pin 11c-A1, and a first pin 11d-A1, preferably, an angle between the first pin 11a-A1 and the second reference line L2 is ang1, an angle between the first pin 11b-A1 and the second reference line L2 is (ang1+ang2), an angle between the first pin 11c-A1 and the second reference line L2 is (ang1+2ang2), and an angle between the first pin 11d-A1 and the second reference line L2 is (ang1+3ang2). The distance between the first pin 11a-A1 and the first pin 11b-A1 is d1, the distance between the first pin 11b-A1 and the first pin 11c-A1 is d1, and the distance between the first pin 11c-A1 and the first pin 11d-A1 is d1. The first pins 11a-A1, the first pins 11b-A1, the first pins 11c-A1 and the first pins 11d-A1 have cross-sectional widths d2.

In the first pin group A2 on one side, four first pins 11 are included, and for convenience of description, from the nearest second reference line L2 to the farthest second reference line L2, the first pins 11a-A2, the first pins 11b-A2, the first pins 11c-A2, and the first pins 11d-A2 are respectively referred to as a first pin 11a-A2, a first pin 11c-A2, and a first pin 11d-A2, wherein an angle between the first pin 11a-A2 and the second reference line L2 is (ang1+3ang2+ang3), an angle between the first pin 11b-A2 and the second reference line L2 is (ang1+3ang2+2ang3), and an angle between the first pin 11c-A2 and the second reference line L2 is (ang1+3ang2+3ang3), and an angle between the first pin 11d-A2 and the second pin L2 is (ang1+3ang2+ang3). Preferably, angle ang3 is greater than angle ang2. The distance between the first pin 11a-A2 and the first pin 11b-A2 is d3, the distance between the first pin 11b-A2 and the first pin 11c-A2 is d3, and the distance between the first pin 11c-A2 and the first pin 11d-A2 is d3. Wherein the distance d3 may be greater than the distance d1 or equal to the distance d1. The first pins 11a-A2, the first pins 11b-A2, the first pins 11c-A2 and the first pins 11d-A2 have cross-sectional widths d4. Preferably, the cross-sectional width d4 is greater than the cross-sectional width d2.

In the first pin group A3 on one side, four first pins 11 are included, and for convenience of description, from the nearest second reference line L2 to the farthest second reference line L2, the first pins 11a-A3, the first pins 11b-A3, the first pins 11c-A3, and the first pins 11d-A3 are respectively referred to as a first pin 11a-A3, a first pin 11c-A3, and a first pin 11d-A3, wherein an angle between the first pin 11a-A3 and the second reference line L2 is (ang1+3ang2+4ang3+ang4), an angle between the first pin 11b-A3 and the second reference line L2 is (ang1+3ang2+4ang3+2ang4), and an angle between the first pin 11c-A3 and the second reference line L2 is (ang1+3ang2+4ang3+3ang4), and an angle between the first pin 11d-A3 and the second reference line L2 is (ang1+3ang2+4ang2). Preferably, angle ang4 is greater than angle ang3. The distance between the first pin 11a-A3 and the first pin 11b-A3 is d5, the distance between the first pin 11b-A3 and the first pin 11c-A3 is d5, and the distance between the first pin 11c-A3 and the first pin 11d-A3 is d5. Wherein the distance d5 may be greater than the distance d3 or equal to the distance d3. The first pins 11a-A3, the first pins 11b-A3, the first pins 11c-A3 and the first pins 11d-A3 have cross-sectional widths d6. Preferably, the cross-sectional width d6 is greater than the cross-sectional width d4.

Here, in each first lead group, it is preferable that the distance from the intersection point D10 to the distal end of the first lead 11 farthest from the second reference line L2 satisfies the formula:

R ₁ ＝360×W ₁ ×M ₁ /(π×θ ₁ )

Display panel

Correspondingly, the present embodiment also provides a display panel, and in particular, please refer to fig. 8, which is a schematic structural diagram of a display panel according to a fourth embodiment of the present invention. As shown in fig. 8, the display panel 2 includes a non-display area 20, and a plurality of second pins 21 are disposed on the non-display area 20, and all the second pins 21 are arranged along a third reference line L3; of all the second leads 21, at least one extension line of the second lead 21 intersects with a fourth reference line L4, and the fourth reference line L4 is perpendicular to the third reference line L3. Here, the second pin 21 corresponds to the first pin 11, and the second pin 21 may refer to the first pin 11 and the first embodiment in the present embodiment, which will not be described in detail.

Flat panel display

Correspondingly, the embodiment also provides a flat panel display. Referring to fig. 7 and 8 in combination, in the embodiment of the present application, the flat panel display includes a driving circuit carrier 1 and a display panel 2, a first pin 11 in the driving circuit carrier 1 is completely or partially attached to a second pin 21 in the display panel 2, and the second reference line L2 and the fourth reference line L4 are overlapped.

[ example five ]

Drive circuit carrier

Fig. 9 is a schematic diagram of a driving circuit carrier according to a fifth embodiment of the invention. As shown in fig. 9, in the embodiment of the present application, the driving circuit carrier 1 includes a substrate 10 and a plurality of first pins 11 disposed on at least one surface of the substrate 10, and all the first pins 11 are arranged L1 along a first reference line; of all the first leads 11, at least one extension line of the first lead 11 intersects with a second reference line L2, and the second reference line L2 is perpendicular to the first reference line L1.

In this embodiment, all the first pins 11 are arranged in a right-angle trapezoid shape. Further, the first reference line L1 bisects each first lead 11 in the direction of the second reference line L2.

The number of the first pins 11 is eight, and the eight first pins 11 form two first pin groups, namely a first pin group A1 and a first pin group A2, wherein the first pin group A1 comprises four first pins 11, and the first pin group A2 comprises four first pins 11. In this embodiment, the first lead group A1 intersects with the second reference line L2, and the first lead group A2 is parallel to the second reference line L2, where the first lead group A2 is located on one side of the first lead group A1.

The second reference line L2 may be located in the first lead group A1, or the second reference line L2 may be located in the first lead group A2, or the second reference line L2 may be located between the first lead group A1 and the first lead group A2, or the second reference line L2 may be located at one side of all the first leads 11. In this embodiment, the second reference line L2 is located in the first pin group A2.

With continued reference to fig. 9, in the first lead group A1, an included angle between an extension line of the first lead 11 close to the second reference line L2 and the second reference line L2 is smaller than an included angle between an extension line of the first lead 11 far from the second reference line L2 and the second reference line L2. Preferably, the included angle between the extension line of the first lead 11 and the second reference line L2 is gradually increased from the first lead 11 closest to the second reference line L2 to the first lead 11 farthest from the second reference line L2. Wherein, from the first pin 11 closest to the second reference line L2 to the first pin 11 farthest from the second reference line L2, the increase amplitude of the angle between the extension line of the first pin 11 and the second reference line L2 is the same or different. When the increasing amplitude of the angle between the extension line of the first lead 11 and the second reference line L2 is different from the first lead 11 closest to the second reference line L2 to the first lead 11 farthest from the second reference line L2, the increasing amplitude of the angle between the extension line of the first lead 11 and the second reference line L2 may be larger or smaller.

With continued reference to fig. 9, in the embodiment of the present application, the cross-sectional widths of all the first pins 11 are equal, that is, the cross-sectional widths of the four first pins 11 in the first pin group A1 are equal, the cross-sectional widths of the four first pins 11 in the second pin group A2 are equal, and the cross-sectional widths of the first pins 11 in the first pin group A1 are equal to the cross-sectional widths of the first pins 11 in the second pin group A2. In other embodiments of the present application, the width of the cross section of the first lead 11 near the second reference line L2 may be smaller than the width of the cross section of the first lead 11 far from the second reference line L2, or the width of the cross section of the first lead 11 near the second reference line L2 may be larger than the width of the cross section of the first lead 11 far from the second reference line L2. Further, the width of the cross section of the first lead 11 close to the second reference line L2 may be smaller than the width of the cross section of the first lead 11 far from the second reference line L2 among all the first leads 11; the first lead 11 near the second reference line L2 may have a smaller cross-sectional width than the first lead 11 far from the second reference line L2 in the first lead group A1, and all (four) first leads 11 may have the same cross-sectional width in the second lead group A2. Preferably, the cross-sectional width of the first lead 11 increases gradually from the first lead 11 closest to the second reference line L2 to the first lead 11 farthest from the second reference line L2. Here, the cross-sectional width of the first lead 11 may be taken by the first reference line L1, that is, the length of the portion where the first reference line L1 overlaps the first lead 11 is the cross-sectional width of the first lead 11.

R ₁ ＝360×W ₁ ×M ₁ /(π×θ ₁ )

wherein the distal end is the end of the first pin 11 away from the intersection point D10, R ₁ A distance from the intersection point D10 to the distal end of the first leg 11 farthest from the second reference line L2; w (W) ₁ Is the cross-sectional width of the first pin 11; m is M ₁ For the number of the first pins 11An amount of; pi is a constant; θ ₁ Is the angle between the extension line of the first pin 11 farthest from the second reference line L2 and the second reference line L2. Preferably, θ ₁ The value of (2) is 5-15 degrees.

Display panel

Correspondingly, the present embodiment also provides a display panel, and in particular, please refer to fig. 10, which is a schematic structural diagram of a display panel according to a fifth embodiment of the present invention. As shown in fig. 10, the display panel 2 includes a non-display area 20, and a plurality of second pins 21 are disposed on the non-display area 20, and all the second pins 21 are arranged along a third reference line L3; of all the second leads 21, at least one extension line of the second lead 21 intersects with a fourth reference line L4, and the fourth reference line L4 is perpendicular to the third reference line L3. Here, the second pin 21 corresponds to the first pin 11, and the second pin 21 may refer to the first pin 11 and the first embodiment in the present embodiment, which will not be described in detail.

Flat panel display

Correspondingly, the embodiment also provides a flat panel display. Referring to fig. 9 and 10 in combination, in the embodiment of the present application, the flat panel display includes a driving circuit carrier 1 and a display panel 2, where a first pin 11 in the driving circuit carrier 1 is completely or partially attached to a second pin 21 in the display panel 2, and the second reference line L2 and the fourth reference line L4 are overlapped.

[ example six ]

Fig. 11 is a schematic diagram of a driving circuit carrier according to a sixth embodiment of the invention. As shown in fig. 11, in the embodiment of the present application, the driving circuit carrier 1 includes a substrate 10 and a plurality of first pins 11 disposed on at least one surface of the substrate 10, where all the first pins 11 are arranged L1 along a first reference line; of all the first leads 11, at least one extension line of the first lead 11 intersects with a second reference line L2, and the second reference line L2 is perpendicular to the first reference line L1.

The number of the first pins 11 is sixteen, and sixteen first pins 11 form four first pin groups, namely a first pin group A1, a first pin group A2, a first pin group A3 and a first pin group A4, and each first pin group includes four first pins 11. In this embodiment, the first lead group A1, the first lead group A2, and the first lead group A3 all intersect the second reference line L2, and the first lead group A4 is parallel to the second reference line L2. Along the direction of the first reference line L1, the first lead group A4, the first lead group A1, the first lead group A2 and the first lead group A3 are sequentially arranged.

In the embodiment of the present application, the second reference line L2 is located in the first pin group A4. That is, among the three first lead groups intersecting the second reference line L2, the first lead group A1 is closest to the second reference line L2, the first lead group A2 is the second time, and the first lead group A3 is the farthest from the second reference line L2.

With continued reference to fig. 11, in each of the first lead groups (i.e., in the first lead group A1, in the first lead group A2, and in the first lead group A3), an angle between an extension line of the first lead 11 near the second reference line L2 and the second reference line L2 is smaller than an angle between an extension line of the first lead 11 far from the second reference line L2 and the second reference line L2. Preferably, the included angle between the extension line of the first lead 11 and the second reference line L2 is gradually increased from the first lead 11 closest to the second reference line L2 to the first lead 11 farthest from the second reference line L2. Wherein, from the first pin 11 closest to the second reference line L2 to the first pin 11 farthest from the second reference line L2, the increase amplitude of the angle between the extension line of the first pin 11 and the second reference line L2 is the same or different. When the increasing amplitude of the angle between the extension line of the first lead 11 and the second reference line L2 is different from the first lead 11 closest to the second reference line L2 to the first lead 11 farthest from the second reference line L2, the increasing amplitude of the angle between the extension line of the first lead 11 and the second reference line L2 may be larger or smaller.

Further, between the first lead group and the first lead group, the increase of the angle between the extension line of the first lead 11 and the second reference line L2 is preferably greater from the first lead group closest to the second reference line L2 to the first lead group farthest from the second reference line L2 (i.e., from the first lead group A1 to the first lead group A3).

Further, the cross-sectional widths of the plurality of first pins 11 of the same first pin group taken by the first reference line L1 are the same. Namely, in the first pin group A1, the cross-sectional widths of the four first pins 11 are the same; in the first pin group A2, the cross-sectional widths of the four first pins 11 are the same; in the first pin group A3, the cross-sectional widths of the four first pins 11 are the same; in the first pin group A4, the cross-sectional widths of the four first pins 11 are the same.

Between the first lead group and the first lead group, a cross-sectional width of the first lead 11 taken by the first reference line L1 becomes larger from the first lead group closest to the second reference line L2 to the first lead group farthest from the second reference line L2. Specifically, the first pins 11 in the first pin group A1 have the smallest cross-sectional width from the first pin group A1 to the first pin group A3, the first pins 11 in the first pin group A2 have the central cross-sectional width, and the first pins 11 in the first pin group A3 have the largest cross-sectional width. Further, the cross-sectional width of the first pins 11 in the first pin group A4 may be smaller than the cross-sectional width of the first pins 11 in the first pin group A1.

In the same first pin group, the pitches of two adjacent first pins 11 at the first reference line L1 are the same. Namely, in the first pin group A1, the pitches of two adjacent first pins 11 at the first reference line L1 are the same; in the first pin group A2, the pitches of two adjacent first pins 11 at the first reference line L1 are the same; in the first pin group A3, the pitches of two adjacent first pins 11 at the first reference line L1 are the same; in the first lead group A4, the pitches of two adjacent first leads 11 at the first reference line L1 are the same.

Between the first lead group and the first lead group, the pitch between the adjacent two first leads 11 at the first reference line L1 becomes larger from the first lead group closest to the second reference line L2 to the first lead group farthest from the second reference line L2. Specifically, from the first pin group A1 to the first pin group A3, the distance between two adjacent first pins 11 in the first pin group A1 at the first reference line L1 is the smallest; the spacing of two adjacent first pins 11 in the first pin group A2 at the first reference line L1 is multiple; the pitch between two adjacent first pins 11 in the first pin group A3 is the largest at the first reference line L1. Further, the pitch of two adjacent first pins 11 in the first pin group A4 at the first reference line L1 may be smaller than the pitch of two adjacent first pins 11 in the first pin group A1 at the first reference line L1.

The plurality of first pins 11 are arranged along the first reference line L1 and are in a right trapezoid shape, so that the first pin group A4 can be used as a reference in the process of bonding the driving circuit carrier 1 on the display panel, and bonding operation can be conveniently performed; further, by gradually increasing the angle between the first lead 11 and the second reference line L2 from the closest to the second reference line L2 to the farthest from the second reference line L2, the distance between the adjacent first leads 11 remains unchanged or gradually increases, and the cross-sectional width of the first lead 11 gradually increases, so that the properties of the base material 10 can be well attached, and the tensile deformation generated by the base material 10 can be compensated.

Display panel

Correspondingly, the present embodiment also provides a display panel, and in particular, please refer to fig. 12, which is a schematic structural diagram of a display panel according to a sixth embodiment of the present invention. As shown in fig. 12, the display panel 2 includes a non-display area 20, and a plurality of second pins 21 are disposed on the non-display area 20, and all the second pins 21 are arranged along a third reference line L3; of all the second leads 21, at least one extension line of the second lead 21 intersects with a fourth reference line L4, and the fourth reference line L4 is perpendicular to the third reference line L3. Here, the second pin 21 corresponds to the first pin 11, and the second pin 21 may refer to the first pin 11 and the first embodiment in the present embodiment, which will not be described in detail.

Flat panel display

Correspondingly, the embodiment also provides a flat panel display. Referring to fig. 11 and 12 in combination, in the embodiment of the present application, the flat panel display includes a driving circuit carrier 1 and a display panel 2, where a first pin 11 in the driving circuit carrier 1 is completely or partially attached to a second pin 21 in the display panel 2, and the second reference line L2 and the fourth reference line L4 are overlapped.

[ embodiment seven ]

Drive circuit carrier

Fig. 13 is a schematic structural diagram of a driving circuit carrier according to a seventh embodiment of the invention. As shown in fig. 13, in the embodiment of the present application, the driving circuit carrier 1 includes a substrate 10 and a plurality of first pins 11 disposed on at least one surface of the substrate 10, and all the first pins 11 are arranged L1 along a first reference line; of all the first leads 11, at least one extension line of the first lead 11 intersects with a second reference line L2, and the second reference line L2 is perpendicular to the first reference line L1.

In the embodiment of the present application, the first reference line L1 bisects each first lead 11 in the direction of the second reference line L2. Preferably, the second reference line L2 is located between two adjacent first pins 11, for example, the number of the first pins 11 is an even number, and the second reference line L2 is located between two middle first pins 11. In other embodiments of the present application, the second reference line L2 may also be located on one side of the plurality of first pins 11, that is, all the first pins 11 are located on the same side of the second reference line L2.

With continued reference to fig. 13, in the embodiment of the present application, the number of the first pins 11 is eight, and eight first pins 11 form eight first pin groups, where each first pin group includes one first pin 11, and here, the first pin group A1, the first pin group A2, the first pin group A3, the first pin group A4, the first pin group A5, the first pin group A6, the first pin group A7, and the first pin group A8 are respectively. Further, along the direction of the first reference line L1, the first pin group A8, the first pin group A6, the first pin group A4, the first pin group A2, the first pin group A1, the first pin group A3, the first pin group A5, and the first pin group A7 are sequentially arranged.

In this embodiment, all eight first lead groups intersect the second reference line L2. Further, different first lead groups intersect at different points of the second reference line L2. That is, in the embodiment of the present application, each first pin 11 intersects a different point on the second reference line L2. Specifically, the first lead 11 in the first lead group A1 intersects the intersection point D10 on the second reference line L2, the first lead 11 in the first lead group A2 intersects the intersection point D11 on the second reference line L2, the first lead 11 in the first lead group A3 intersects the intersection point D12 on the second reference line L2, the first lead 11 in the first lead group A4 intersects the intersection point D13 on the second reference line L2, the first lead 11 in the first lead group A5 intersects the intersection point D14 on the second reference line L2, the first lead 11 in the first lead group A6 intersects the intersection point D15 on the second reference line L2, the first lead 11 in the first lead group A7 intersects the intersection point D16 on the second reference line L2, and the first lead 11 in the first lead group A8 intersects the intersection point D17 on the second reference line L2.

In the embodiment of the present application, the intersection point of the extension line of the first lead 11 near the second reference line L2 and the second reference line L2 is near a plurality of the first leads 11 (herein, a plurality of the first leads 11 may be regarded as a whole). In other embodiments of the present application, the intersection point of the extension line of the first lead 11 far from the second reference line L2 and the second reference line L2 may be close to a plurality of the first leads 11, or a cross exists between the extension lines of a plurality of the first leads 11.

Further, the included angle between the extension line of the first lead 11 near the second reference line L2 and the second reference line L2 is smaller than the included angle between the extension line of the first lead 11 far from the second reference line L2 and the second reference line L2, or the included angle between the extension line of the first lead 11 near the second reference line L2 and the second reference line L2 is larger than the included angle between the extension line of the first lead 11 far from the second reference line L2 and the second reference line L2, or the included angle between the extension line of the first lead 11 near the second reference line L2 and the second reference line L2 is equal to the included angle between the extension line of the first lead 11 far from the second reference line L2 and the second reference line L2. Preferably, the included angle between the extension line of the first lead 11 and the second reference line L2 is gradually increased from the first lead 11 closest to the second reference line L2 to the first lead 11 farthest from the second reference line L2. Wherein, from the first pin 11 closest to the second reference line L2 to the first pin 11 farthest from the second reference line L2, the increase amplitude of the angle between the extension line of the first pin 11 and the second reference line L2 is the same or different. When the increasing amplitude of the angle between the extension line of the first lead 11 and the second reference line L2 is different from the first lead 11 closest to the second reference line L2 to the first lead 11 farthest from the second reference line L2, the increasing amplitude of the angle between the extension line of the first lead 11 and the second reference line L2 may be larger or smaller.

In this embodiment, eight first pins 11 are evenly distributed on two sides of the second reference line L2. Wherein, the included angle between the extension line of the first pin 11 close to the second reference line L2 and the second reference line L2 may be smaller than the included angle between the extension line of the first pin 11 far from the second reference line L2 and the second reference line L2; on the other side, an included angle between an extension line of the first pin 11 close to the second reference line L2 and the second reference line L2 is equal to an included angle between an extension line of the first pin 11 far from the second reference line L2 and the second reference line L2. It may be satisfied that an included angle between an extension line of the first pin 11 close to the second reference line L2 and the second reference line L2 is smaller than an included angle between an extension line of the first pin 11 far from the second reference line L2 and the second reference line L2. The present application is not limited in this regard. Further choices may be made according to the nature of the substrate 10.

Display panel

Correspondingly, the present embodiment also provides a display panel, and in particular, please refer to fig. 14, which is a schematic structural diagram of a display panel according to a seventh embodiment of the present invention. As shown in fig. 14, the display panel 2 includes a non-display area 20, and a plurality of second pins 21 are disposed on the non-display area 20, and all the second pins 21 are arranged along a third reference line L3; of all the second leads 21, at least one extension line of the second lead 21 intersects with a fourth reference line L4, and the fourth reference line L4 is perpendicular to the third reference line L3. Here, the second pin 21 corresponds to the first pin 11, and the second pin 21 may refer to the first pin 11 and the first embodiment in the present embodiment, which will not be described in detail.

Flat panel display

Correspondingly, the embodiment also provides a flat panel display. Referring to fig. 13 and 14 in combination, in the embodiment of the present application, the flat panel display includes a driving circuit carrier 1 and a display panel 2, where a first pin 11 in the driving circuit carrier 1 is completely or partially attached to a second pin 21 in the display panel 2, and the second reference line L2 and the fourth reference line L4 are overlapped.

[ example eight ]

Drive circuit carrier

Fig. 15 is a schematic diagram of a driving circuit carrier according to an eighth embodiment of the invention. As shown in fig. 15, in the embodiment of the present application, the driving circuit carrier 1 includes a substrate 10 and a plurality of first pins 11 disposed on at least one surface of the substrate 10, and all the first pins 11 are arranged L1 along a first reference line; of all the first leads 11, at least one extension line of the first lead 11 intersects with a second reference line L2, and the second reference line L2 is perpendicular to the first reference line L1.

With continued reference to fig. 15, in the embodiment of the present application, the number of the first pins 11 is twelve, and the twelve first pins 11 form nine first pin groups, which are a first pin group A1, a first pin group A2, a first pin group A3, a first pin group A4, a first pin group A5, a first pin group A6, a first pin group A7, a first pin group A8, and a first pin group A9. The first pin group A1, the first pin group A2, the first pin group A3, the first pin group A4, the first pin group A5, the first pin group A6, the first pin group A7 and the first pin group A8 all include a first pin 11, and the first pin group A9 includes four first pins 11. Along the direction of the first reference line L1, the first lead group A8, the first lead group A6, the first lead group A4, the first lead group A2, the first lead group A9, the first lead group A1, the first lead group A3, the first lead group A5 and the first lead group A7 are sequentially arranged.

In this embodiment, the first lead group A1, the first lead group A2, the first lead group A3, the first lead group A4, the first lead group A5, the first lead group A6, the first lead group A7 and the first lead group A8 are all intersected with the second reference line L2, and the first lead group A9 is parallel with the second reference line L2. Further, different first lead groups intersecting the second reference line L2 intersect different points of the second reference line L2. That is, in the embodiment of the present application, the first pins 11 intersecting the second reference line L2 intersect at different points on the second reference line L2. Specifically, the first lead 11 in the first lead group A1 intersects the intersection point D10 on the second reference line L2, the first lead 11 in the first lead group A2 intersects the intersection point D11 on the second reference line L2, the first lead 11 in the first lead group A3 intersects the intersection point D12 on the second reference line L2, the first lead 11 in the first lead group A4 intersects the intersection point D13 on the second reference line L2, the first lead 11 in the first lead group A5 intersects the intersection point D14 on the second reference line L2, the first lead 11 in the first lead group A6 intersects the intersection point D15 on the second reference line L2, the first lead 11 in the first lead group A7 intersects the intersection point D16 on the second reference line L2, and the first lead 11 in the first lead group A8 intersects the intersection point D17 on the second reference line L2.

In this embodiment, eight first pins 11 intersecting with the second reference line L2 are evenly distributed on two sides of the second reference line L2. Wherein, the included angle between the extension line of the first pin 11 close to the second reference line L2 and the second reference line L2 may be smaller than the included angle between the extension line of the first pin 11 far from the second reference line L2 and the second reference line L2; on the other side, an included angle between an extension line of the first pin 11 close to the second reference line L2 and the second reference line L2 is equal to an included angle between an extension line of the first pin 11 far from the second reference line L2 and the second reference line L2. It may be satisfied that an included angle between an extension line of the first pin 11 close to the second reference line L2 and the second reference line L2 is smaller than an included angle between an extension line of the first pin 11 far from the second reference line L2 and the second reference line L2. The present application is not limited in this regard. Further choices may be made according to the nature of the substrate 10.

Display panel

Correspondingly, the present embodiment also provides a display panel, and in particular, please refer to fig. 16, which is a schematic structural diagram of a display panel according to an eighth embodiment of the present invention. As shown in fig. 16, the display panel 2 includes a non-display area 20, and a plurality of second pins 21 are disposed on the non-display area 20, and all the second pins 21 are arranged along a third reference line L3; of all the second leads 21, at least one extension line of the second lead 21 intersects with a fourth reference line L4, and the fourth reference line L4 is perpendicular to the third reference line L3. Here, the second pin 21 corresponds to the first pin 11, and the second pin 21 may refer to the first pin 11 and the first embodiment in the present embodiment, which will not be described in detail.

Flat panel display

Correspondingly, the embodiment also provides a flat panel display. Referring to fig. 15 and 16 in combination, in the embodiment of the present application, the flat panel display includes a driving circuit carrier 1 and a display panel 2, where a first pin 11 in the driving circuit carrier 1 is completely or partially attached to a second pin 21 in the display panel 2, and the second reference line L2 and the fourth reference line L4 are overlapped.

[ example nine ]

Drive circuit carrier

Fig. 17 is a schematic structural diagram of a driving circuit carrier according to a ninth embodiment of the invention. As shown in fig. 17, in the embodiment of the present application, the driving circuit carrier 1 includes a substrate 10 and a plurality of first pins 11 disposed on at least one surface of the substrate 10, and all the first pins 11 are arranged L1 along a first reference line; of all the first leads 11, at least one extension line of the first lead 11 intersects with a second reference line L2, and the second reference line L2 is perpendicular to the first reference line L1.

In the embodiment of the present application, the first reference line L1 bisects each first lead 11 in the direction of the second reference line L2. With continued reference to fig. 17, in the embodiment of the present application, the number of the first pins 11 is eight, and the five first pin groups are formed by eight first pins 11, which are a first pin group A1, a first pin group A2, a first pin group A3, a first pin group A4, and a first pin group A5. The first pin group A1, the first pin group A2, the first pin group A3 and the first pin group A4 each include one first pin 11, and the first pin group A5 includes four first pins 11. Along the direction of the first reference line L1, the first lead group A5, the first lead group A1, the first lead group A2, the first lead group A3 and the first lead group A4 are sequentially arranged. In the embodiment of the present application, the second reference line L2 is located in the first pin group A5.

In this embodiment, the first lead group A1, the first lead group A2, the first lead group A3, and the first lead group A4 all intersect the second reference line L2, and the first lead group A5 is parallel to the second reference line L2. Further, different first lead groups intersecting the second reference line L2 intersect different points of the second reference line L2. That is, in the embodiment of the present application, the first pins 11 intersecting the second reference line L2 intersect at different points on the second reference line L2. Specifically, the first lead 11 in the first lead group A1 intersects the intersection point D10 on the second reference line L2, the first lead 11 in the first lead group A2 intersects the intersection point D11 on the second reference line L2, the first lead 11 in the first lead group A3 intersects the intersection point D12 on the second reference line L2, and the first lead 11 in the first lead group A4 intersects the intersection point D13 on the second reference line L2.

Display panel

Correspondingly, the present embodiment also provides a display panel, and in particular, please refer to fig. 18, which is a schematic structural diagram of a display panel according to a ninth embodiment of the present invention. As shown in fig. 18, the display panel 2 includes a non-display area 20, and a plurality of second pins 21 are disposed on the non-display area 20, and all the second pins 21 are arranged along a third reference line L3; of all the second leads 21, at least one extension line of the second lead 21 intersects with a fourth reference line L4, and the fourth reference line L4 is perpendicular to the third reference line L3. Here, the second pin 21 corresponds to the first pin 11, and the second pin 21 may refer to the first pin 11 and the first embodiment in the present embodiment, which will not be described in detail.

Flat panel display

Correspondingly, the embodiment also provides a flat panel display. Referring to fig. 17 and fig. 18 in combination, in the embodiment of the present application, the flat panel display includes a driving circuit carrier 1 and a display panel 2, where a first pin 11 in the driving circuit carrier 1 is completely or partially attached to a second pin 21 in the display panel 2, and the second reference line L2 and the fourth reference line L4 are overlapped.

[ example ten ]

Drive circuit carrier

Fig. 19 is a schematic structural diagram of a driving circuit carrier according to a tenth embodiment of the invention. As shown in fig. 19, in the embodiment of the present application, the driving circuit carrier 1 includes a substrate 10 and a plurality of first pins 11 disposed on at least one surface of the substrate 10, and all the first pins 11 are arranged L1 along a first reference line; of all the first leads 11, at least one extension line of the first lead 11 intersects with a second reference line L2, and the second reference line L2 is perpendicular to the first reference line L1. In the embodiment of the present application, the first reference line L1 bisects each first lead 11 in the direction of the second reference line L2.

Further, each first pin 11 comprises a first end 110 and a second end 111 opposite to each other, wherein the cross-sectional width of the first end 110 is larger than the cross-sectional width of the second end 111. Here, the first end 110 of each first pin 11 is close to the display panel, and the second end 111 of each first pin 11 is far from the display panel. Through the one end cross-section width of first pin 11 is greater than the other end, will drive circuit carrier 1 nation is on the display panel, when carrying out skew compensation, can make the contact surface width increase of the pin on the drive circuit carrier 1 with the pin on the display panel to improve the nation and decide the effect.

With continued reference to fig. 19, in the embodiment of the present application, the cross-sectional width of the first pin 11 gradually decreases from the first end 110 to the second end 111. That is, of the sectional widths of the first pins 11, the sectional width of the first end 110 is the largest and the sectional width of the second end 111 is the smallest.

In other embodiments of the present application, the cross-sectional width of the first pin 11 may have other different arrangements, as long as the cross-sectional width of the first end 110 is larger than the cross-sectional width of the second end 111. In particular, the first pin 11 may comprise a plurality of segments, each segment having a different shape and/or cross-sectional width.

For example, as shown in fig. 20, the cross-sectional width of the first pin 11 from the first end 110 to the second end 111 is maintained constant and then gradually decreases. That is, in fig. 20, the first pin 11 includes two sections, a first section near the first end 110 and a second section far from the first end 110, wherein in the first section, the cross-sectional width of the first pin 11 is kept unchanged and is the same as the cross-sectional width of the first end 110, i.e., the shape of the first section is rectangular or parallelogram; in the second section, the cross-sectional width of the first pin 11 gradually decreases from the end near the first end 110 to the second end 111, i.e., in the second section, the cross-sectional width near the end of the first end 110 is the largest and the cross-sectional width of the second end 111 is the smallest.

For another example, the first pin 11 may have a cross-sectional width that gradually decreases from the first end 110 to the second end 111, then remains the same, and then gradually decreases. That is, the first pin 11 includes three sections, a first section near the first end 110, a third section near the second end 111, and a second section between the first section and the third section, wherein in the first section, a cross-sectional width of the first pin 11 gradually decreases, that is, a cross-sectional width of the first pin 11 gradually decreases from the first end 110 toward an end far from the first end 110, that is, in the first section, a cross-sectional width of the first end 110 is the largest and a cross-sectional width of an end far from the first end 110 is the smallest; in the second section, the cross-sectional width of the first pin 11 remains unchanged, and is the same as the minimum cross-sectional width in the first section and the maximum cross-sectional width in the third section, i.e. the shape of the second section is rectangular or parallelogram; in the third section, the cross-sectional width of the first pin 11 gradually decreases from the end near the first end 110 to the second end 111, i.e., in the third section, the cross-sectional width near the end of the first end 110 is the largest, and the cross-sectional width of the second end 111 is the smallest.

Also, for example, the cross-sectional width of the first pin 11 from the first end 110 to the second end 111 is kept constant, and then is reduced and then is kept constant. That is, the first pin 11 includes two sections, a first section near the first end 110 and a second section far from the first end 110, wherein in the first section, the cross-sectional width of the first pin 11 remains unchanged and is the same as the cross-sectional width of the first end 110, i.e., the first section is rectangular or parallelogram; in the second section, the cross-sectional width of the first pin 11 remains the same as the cross-sectional width of the second end 111, i.e. the second section is rectangular or parallelogram in shape, wherein the cross-sectional width of the second end 111 is smaller than the cross-sectional width of the first end 110.

Display panel

Correspondingly, the present embodiment also provides a display panel, and in particular, please refer to fig. 21 or fig. 22, which is a schematic structural diagram of a display panel according to a tenth embodiment of the present invention. As shown in fig. 21 or 22, the display panel 2 includes a non-display area 20, and a plurality of second pins 21 are disposed on the non-display area 20, and all the second pins 21 are arranged along a third reference line L3; of all the second leads 21, at least one extension line of the second lead 21 intersects with a fourth reference line L4, and the fourth reference line L4 is perpendicular to the third reference line L3. Here, the second pin 21 corresponds to the first pin 11, and the second pin 21 may refer to the first pin 11 and the first embodiment in the present embodiment, which will not be described in detail.

Flat panel display

Correspondingly, the embodiment also provides a flat panel display. 19-22, in this embodiment, the flat panel display includes a driving circuit carrier 1 and a display panel 2, where a first pin 11 in the driving circuit carrier 1 is completely or partially attached to a second pin 21 in the display panel 2, and the second reference line L2 and the fourth reference line L4 are overlapped.

[ example eleven ]

Fig. 23 is a schematic diagram of a driving circuit carrier according to an eleventh embodiment of the invention. As shown in fig. 23, in the embodiment of the present application, the driving circuit carrier 1 includes a substrate 10 and a plurality of first pins 11 disposed on at least one surface of the substrate 10, and all the first pins 11 are arranged L1 along a first reference line; of all the first leads 11, at least one extension line of the first lead 11 intersects with a second reference line L2, and the second reference line L2 is perpendicular to the first reference line L1. In the embodiment of the present application, the first reference line L1 bisects each first lead 11 in the direction of the second reference line L2.

In this embodiment, a first alignment mark 12 is disposed on the first pin 11 located at the outermost side. When the driving circuit carrier 1 is bonded to the display panel, the first alignment mark 12 can be used for conveniently aligning, so that the bonding efficiency is improved.

Preferably, the first alignment marks 12 are disposed on the two first pins 11 located at the outermost sides. Thus, when the driving circuit carrier 1 is bonded to the display panel, the alignment can be performed by the first alignment marks 12 on the plurality of first pins 11, so that the bonding efficiency can be further improved.

In this embodiment, each of the first pins 11 includes a pair of first sides intersecting the first reference line L1 and a pair of second sides parallel to the first reference line L1. Preferably, each first alignment mark 12 is disposed on a first side edge of the first lead 11 on the outermost side, and is located on one first side edge on the outer side. Further, the first alignment mark 12 is located on the first reference line L1.

Further, the shape of the first alignment mark 12 may be a regular shape such as a rectangle, a trapezoid, a triangle, a sector, or a circle, or may be an irregular shape, which is not limited in this application.

Display panel

Correspondingly, the present embodiment also provides a display panel, and in particular, please refer to fig. 24, which is a schematic structural diagram of a display panel according to a fourth embodiment of the present invention. As shown in fig. 24, the display panel 2 includes a non-display area 20, and a plurality of second pins 21 are disposed on the non-display area 20, and all the second pins 21 are arranged along a third reference line L3; of all the second leads 21, at least one extension line of the second lead 21 intersects with a fourth reference line L4, and the fourth reference line L4 is perpendicular to the third reference line L3. In the embodiment of the present application, the third reference line L3 bisects each second lead 21 in the direction of the fourth reference line L4.

In this embodiment, a second alignment mark 22 is disposed on the second pin 21 located at the outermost side. When the driving circuit carrier 1 is bonded to the display panel 2, the second alignment mark 22 can be used for conveniently aligning, so that the bonding efficiency is improved.

Preferably, the second alignment marks 22 are disposed on the two second pins 21 located at the outermost side. Thus, when the driving circuit carrier is bonded to the display panel 2, the alignment can be performed by the second alignment marks 22 on the plurality of second pins 21, and the bonding efficiency can be further improved.

In this embodiment, the second pin 21 includes a pair of first sides and a pair of second sides, where the pair of first sides intersect the fourth reference line L4, and the pair of second sides are parallel to the fourth reference line L4. Preferably, the second alignment mark 22 is disposed on a first side of the second lead 21 on the outermost side, and is located on one first side of the outer side.

Preferably, each second alignment mark 22 includes a plurality of alignment structures, wherein the shapes and sizes of the alignment structures may be the same or different. Further, the shape of the alignment structures may be regular, such as rectangular, trapezoidal, triangular, or circular, or irregular, which is not limited in this application.

With continued reference to fig. 24, in the embodiment of the present application, each second alignment mark 22 includes three alignment structures, which are referred to herein as an alignment structure 22a, an alignment structure 22b, and an alignment structure 22c. Of the three alignment structures, the alignment structure 22b is located on the third reference line L3. The alignment structures 22a and 22c are located on both sides of the third reference line L3, that is, on both sides of the alignment structure 22b, respectively, and the distances between the alignment structures 22a and 22c and the third reference line L3 are equal. Wherein, the distance between the alignment structure 22a and the alignment structure 22c and the third reference line L3 refers to the distance between the alignment structure 22a and the alignment structure 22c and the third reference line L3 in the direction of the fourth reference line L4.

Preferably, the distance between the alignment structure 22a and the third reference line L3 satisfies the following formula, and the distance between the alignment structure 22c and the third reference line L3 also satisfies the following formula:

H＝h-s/w

wherein H represents the distance of the alignment structures 22a and 22c from the third reference line L3; h represents the height of the second pins 21 (herein, the plurality of second pins 21 as a whole, the height direction of the plurality of second pins 21 is perpendicular to the third reference line L3); s is a constant (obtained from the minimum area required for the bonding material, which is typically ACF material); w represents the cross-sectional width of the second pin 21 (may be taken through the third reference line L3, and may be an average value of the cross-sectional width of the second pin 21).

In other embodiments of the present application, the second alignment mark 22 may include only one or two alignment structures, and when the second alignment mark 22 includes one alignment structure, it is preferable that the one alignment structure is located on the third reference line L3; when the second alignment mark 22 includes two alignment structures, the two alignment structures are preferably located at two sides of the third reference line L3 and have the same distance from the third reference line L3. In addition, the second alignment mark 22 may further include a plurality of alignment structures, such as five, six, etc. When the second alignment mark 22 includes more alignment structures, alignment can be more conveniently performed when the driving circuit carrier is bonded to the display panel 2, thereby improving bonding efficiency.

In addition, by including a plurality of alignment structures in the second alignment mark 22, the amount of offset compensation can be precisely controlled when offset compensation is performed, and the occurrence of problems such as overcompensation can be avoided.

Flat panel display

Correspondingly, the embodiment also provides a flat panel display. Referring to fig. 23 and 24 in combination, in the embodiment of the present application, the flat panel display includes a driving circuit carrier 1 and a display panel 2, where a first pin 11 in the driving circuit carrier 1 is completely or partially attached to a second pin 21 in the display panel 2, and the second reference line L2 and the fourth reference line L4 are overlapped.

Method for manufacturing flat panel display

Correspondingly, the embodiment also provides a manufacturing method of the flat panel display, which comprises the following steps:

providing said drive circuit carrier 1;

providing said display panel 2;

aligning the first pins 11 on the driving circuit carrier 1 and the second pins 21 on the display panel 2 according to the first alignment marks 12 on the driving circuit carrier 1 and the second alignment marks 22 on the display panel 2;

the first pins 11 and the second pins 21 are attached, so that the driving circuit carrier 1 is bonded on the display panel 2.

Further, aligning the first pins 11 on the driving circuit carrier 1 with the second pins 21 on the display panel 2 according to the first alignment marks 12 on the driving circuit carrier 1 and the second alignment marks 22 on the display panel 2 includes:

acquiring the distance between the two first alignment marks 12 and the distance between the two second alignment marks 22;

obtaining a compensation amount according to a distance difference between the distances between the two first alignment marks 12 and the distances between the two second alignment marks 22;

the driving circuit carrier 1 is moved in the direction of the second reference line L2 by the amount of the compensation amount so that the first pin 11 and the second pin 21 are aligned.

Wherein the compensation amount is obtained by the following formula:

Y＝X/tanθ

wherein Y represents the compensation amount; x represents a distance difference; θ is an included angle between the extension line of the first pin at the outermost side and the second reference line.

In this embodiment, the compensation amount Y is less than or equal to the distance H between the alignment structure 22a (or the alignment structure 22 c) and the third reference line. The compensation amount Y may be 0, and the distance moved in the direction of the second reference line L2 is also 0.

Bonding device

Correspondingly, the present embodiment further provides a bonding device 3, where the bonding device 3 includes: a gripping unit 30, a compensating unit 31, a moving unit 32 and a bonding unit 33, wherein,

the grabbing 30 unit is used for enabling a distance between the two first alignment marks and a distance between the two second alignment marks;

the compensation unit 31 is configured to obtain a compensation amount according to a distance difference between the distances between the two first alignment marks and the distance between the two second alignment marks;

the moving unit 32 is configured to move the driving circuit carrier in the direction of the second reference line by a distance of the compensation amount so that the first pin and the second pin are aligned;

The bonding unit 33 is configured to attach the first pin and the second pin, so that the driving circuit carrier is bonded on the display panel.

In this application, eleven embodiments are schematically shown, and a person skilled in the art may make many more variants according to the eleven embodiments described above, for example, embodiment ten may be combined with embodiment five, i.e. in embodiment ten, the plurality of first pins 11 may be arranged in the manner of embodiment five, for example, embodiment ten may also be combined with embodiment one, for example, embodiment eleven may be combined with embodiment five, for example, embodiment eleven may be combined with embodiment seven, etc.

The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims

1. A drive circuit carrier, comprising:

a substrate; and

the first pins are arranged on at least one surface of the substrate and are arranged along a first datum line;

wherein the first leads decrease in cross-sectional width along the first reference line from the middle to both sides along the first reference line, the first leads are divided into a plurality of first lead groups along the first reference line, each of the first lead groups includes at least two first leads, and the first leads in each of the first lead groups are adjacent to each other,

There are at least two of the first lead groups located on both sides of a second reference line perpendicular to the first reference line, and wherein an extension line of the first lead intersects the second reference line,

at least one first pin group is arranged, wherein an extension line of the first pin is parallel to the second reference line, the first pin group comprising the first pin with the extension line intersecting the second reference line is positioned at two sides of the first pin group comprising the first pin with the extension line parallel to the second reference line, and

for all the first pins, the larger the distance from the second datum line is, the smaller the distance between two adjacent first pins along the first datum line is.

2. The drive circuit carrier of claim 1, wherein,

the second reference line passes through the first pin group including the first pins whose extension lines are parallel to the second reference line.

3. The drive circuit carrier according to claim 1 or 2, wherein extension lines of all the first pins having extension lines intersecting with the second reference line are identical to an intersection point of the second reference line.

4. The drive circuit carrier according to claim 1 or 2, wherein, for the first pin group including the first pin whose extension line intersects the second reference line,

the intersection points of the first pins and the second reference line in the same first pin group are the same, and the intersection points of the first pins and the second reference line in different first pin groups are different.

5. The drive circuit carrier of claim 1 or 2, wherein the drive circuit carrier is a flip-chip film or a drive chip.

6. A display panel is characterized by comprising a non-display area, wherein a plurality of second pins are arranged on the non-display area, all the second pins are arranged along a third datum line, the second pins are reduced in section width along the third datum line from the middle to two sides, the second pins are divided into a plurality of second pin groups along the third datum line, each second pin group comprises at least two second pins, and the second pins in each second pin group are adjacent to each other,

there are at least two of the second lead groups located on both sides of a fourth reference line perpendicular to the third reference line, and wherein an extension line of the second lead intersects with the fourth reference line,

At least one second pin group is arranged, wherein an extension line of the second pin is parallel to the fourth reference line, the second pin group comprising the second pin with the extension line intersecting the fourth reference line is positioned at two sides of the second pin group comprising the second pin with the extension line parallel to the fourth reference line, and

for all the second pins, the larger the distance from the fourth datum line is, the smaller the distance between two adjacent second pins along the third datum line is.

7. A flat panel display, comprising:

the drive circuit carrier according to any one of claims 1 to 5; and

the display panel of claim 6;

and the first pin in the driving circuit carrier is completely or partially attached to the second pin in the display panel.