CN115347769B - Charge pump circuit and memory - Google Patents
Charge pump circuit and memory Download PDFInfo
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- CN115347769B CN115347769B CN202110525835.9A CN202110525835A CN115347769B CN 115347769 B CN115347769 B CN 115347769B CN 202110525835 A CN202110525835 A CN 202110525835A CN 115347769 B CN115347769 B CN 115347769B
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- 230000001629 suppression Effects 0.000 claims abstract description 40
- 238000005070 sampling Methods 0.000 claims description 14
- 230000001105 regulatory effect Effects 0.000 claims description 5
- 230000003247 decreasing effect Effects 0.000 abstract description 10
- 230000000694 effects Effects 0.000 description 15
- 230000007423 decrease Effects 0.000 description 11
- 238000000034 method Methods 0.000 description 7
- 230000001276 controlling effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/14—Arrangements for reducing ripples from dc input or output
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/36—Means for starting or stopping converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
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- Engineering & Computer Science (AREA)
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- Dc-Dc Converters (AREA)
Abstract
The invention provides a charge pump circuit and a memory. The ripple suppression circuit comprises a voltage division circuit and N comparators. The voltage dividing circuit is provided with an input end node, an output end node and N voltage dividing nodes. The first input end of each comparator is connected with a corresponding voltage division node; the input node serves as a first comparison input, and the second inputs of the N comparators are interconnected to form a second comparison input. By providing a ripple suppression circuit; at least one comparison input end of the first comparison input end and the second comparison input end is connected with at least one voltage end of the input voltage end and the output voltage end; the clock generation control circuit is controlled to enable all or part of the N charge pump units according to comparison signals output by different comparators, and the output voltage is enabled to have lower ripple voltage by increasing or decreasing the number of enabled charge pump units.
Description
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a charge pump circuit and a memory.
Background
In order to meet the requirements of full voltage range operation, a charge pump circuit is typically used to provide a stable voltage source for a word line voltage, a bit line voltage, or a memory cell. The charge pump circuit of the prior art is generally composed of an oscillator, a charge pump and a voltage stabilizing circuit. The voltage stabilizing circuit continuously turns on or off the charge pump when maintaining the voltage stable, and ripple is inevitably generated when outputting the voltage. With the progress of the memory chip technology, the input voltage is continuously reduced, the load of the output voltage is continuously increased, and the output voltage ripple is further increased. The larger output voltage ripple can negatively affect the sensitivity and stability of writing and reading of the memory. The prior art generally adds a filter capacitor to the voltage output to reduce the ripple voltage, but it significantly reduces the settling time of the charge pump and consumes chip area.
Disclosure of Invention
The invention provides a charge pump circuit and a memory, which enable output voltage to have lower ripple voltage.
In a first aspect, the present invention provides a charge pump circuit comprising N charge pump cells, a ripple suppression circuit, and a clock generation control circuit. Wherein N is an integer greater than 1. Each charge pump unit is provided with an input end, an output end and an enabling end; the input ends of the N charge pump units are interconnected to form an input voltage end connected with the input voltage, and the output ends of the N charge pump units are interconnected to form an output voltage end of the charge pump circuit. The ripple suppression circuit includes a voltage division circuit and N comparators. The voltage dividing circuit is provided with an input end node and an output end node, the output end node is grounded, and N voltage dividing nodes are sequentially arranged between the input end node and the output end node. Each comparator is provided with a first input end, a second input end and an output end; n comparators are in one-to-one correspondence with N voltage dividing nodes, and a first input end of each comparator is connected with the corresponding voltage dividing node; the input node serves as a first comparison input, and the second inputs of the N comparators are interconnected to form a second comparison input. The clock generation control circuit is connected with the output ends of the N comparators so as to receive comparison signals output by each comparator; the N comparators are in one-to-one correspondence with the N charge pump units, and the clock generation control circuit is also connected with the enabling ends of the N charge pump units so as to generate control signals for enabling the corresponding charge pump units according to the comparison signals output by each comparator. At least one comparison input end of the first comparison input end and the second comparison input end is connected with at least one voltage end of the input voltage end and the output voltage end; one comparison input terminal is connected with one voltage terminal only, and one voltage terminal is connected with one comparison input terminal only; the comparison input terminal, which is not connected to any voltage terminal, is connected to the reference voltage terminal.
In the above scheme, the ripple suppression circuit is provided, and at least one of the first comparison input end and the second comparison input end is connected with at least one of the input voltage end and the output voltage end; the clock generation control circuit is enabled to control all or part of the N charge pump units according to comparison signals output by different comparators, so that the output voltage output by the output voltage terminal has lower ripple voltage by increasing or decreasing the number of enabled charge pump units, and the effect of low ripple of the output voltage is achieved. And low ripple output without consuming chip area.
In a specific embodiment, the charge pump circuit further includes a voltage adjustment circuit connected to the output voltage terminal, where the voltage adjustment circuit is configured to detect whether the output voltage value output by the output voltage terminal reaches a target voltage value; the voltage regulating circuit is also connected with the ripple suppression circuit and the clock generation control circuit to control the ripple suppression circuit and the clock generation control circuit to be turned on or turned off.
In a specific embodiment, the first comparison input is connected to a first reference voltage terminal and the second comparison input is connected to an output voltage terminal. The number of the charge enabling units is convenient to adaptively adjust based on the output voltage, and the effect of low ripple of the output voltage is achieved.
In a specific embodiment, the first comparison input is connected to the input voltage terminal and the second comparison input is connected to the second reference voltage terminal. The number of the charge enabling units is convenient to adaptively adjust based on the input voltage, and the effect of low ripple of the output voltage is achieved.
In a specific embodiment, the first comparison input is connected to the input voltage terminal and the second comparison input is connected to the output voltage terminal. The self-adaptive charge control circuit is convenient for self-adaptively adjusting the number of charge enabling units based on the input voltage and the output voltage, and achieves the effect of low ripple of the output voltage.
In a specific embodiment, the first comparison input is connected to the output voltage terminal and the second comparison input is connected to the input voltage terminal. The self-adaptive charge control circuit is convenient for self-adaptively adjusting the number of charge enabling units based on the input voltage and the output voltage, and achieves the effect of low ripple of the output voltage.
In a specific embodiment, a first single-pole double-throw switch is provided at the first comparison input, the stationary end of the first single-pole double-throw switch is connected to the first comparison input, and the movable end of the first single-pole double-throw switch is switchable between an input voltage end and a first reference voltage end. The second comparison input end is provided with a second single-pole double-throw switch, the fixed end of the second single-pole double-throw switch is connected with the second comparison input end, and the movable end of the second single-pole double-throw switch can be switched between an output voltage end and a second reference voltage end. When the device is convenient for specific application, ripple suppression on different voltage ends is realized through switching of the two single-pole double-throw switches, the number of charge enabling units is convenient to adaptively adjust based on input voltage and output voltage, and the effect of low ripple of the output voltage is achieved.
In a specific embodiment, the ripple suppression circuit further comprises an output load sampling circuit connected with the output voltage terminal, wherein the output load sampling circuit samples the load current of the output voltage terminal according to the ratio mirror image, and converts the load current into a node voltage terminal through a set resistor. The node voltage end is used for being connected with the second comparison input end. Based on the load current of the output voltage end, the number of the charge pump units is adaptively adjusted and enabled, ripple voltage generated at the output voltage end due to load current change of the output voltage end is reduced, and the effect of low ripple of the output voltage is achieved.
In a specific embodiment, the ripple suppression circuit further includes a start-up circuit, the start-up circuit including: a switching unit and a control unit. The first end of the switch unit is connected with the output voltage end, and the second section of the switch unit is connected with the node voltage end. The control unit is connected with the voltage regulating circuit to receive the pump voltage signal output by the voltage regulating circuit; and the control end of the switch unit is connected with the control unit to control the connection or disconnection of the first end and the second end according to the pump voltage signal. So as to reduce the ripple voltage in the starting stage and realize quick and stable and low ripple output.
In a second aspect, the invention also provides a memory comprising any of the charge pump circuits described above. The ripple suppression circuit is arranged, and at least one comparison input end of the first comparison input end and the second comparison input end is connected with at least one voltage end of the input voltage end and the output voltage end; the clock generation control circuit is enabled to control all or part of the N charge pump units according to comparison signals output by different comparators, so that the output voltage output by the output voltage terminal has lower ripple voltage by increasing or decreasing the number of enabled charge pump units.
Drawings
Fig. 1 is a block diagram of a charge pump circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a ripple suppression circuit according to an embodiment of the present invention.
Reference numerals:
10-Charge Pump Unit 20-ripple suppression Circuit 21-bleeder Circuit
22-comparator 23-output load sampling circuit 231-set resistor
24-start-up circuit 241-switch unit 242-control unit
30-clock generation control circuit 40-voltage regulating circuit
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In order to facilitate understanding of the charge pump circuit provided by the embodiment of the present invention, an application scenario of the charge pump circuit provided by the embodiment of the present invention is first described below, and the charge pump circuit is applied to a memory for providing a stable voltage source for a word line, a bit line or a memory cell in the memory. The charge pump circuit is described in detail below with reference to the accompanying drawings.
Referring to fig. 1 and 2, a charge pump circuit according to an embodiment of the present invention includes N charge pump units 10, a ripple suppression circuit 20, and a clock generation control circuit 30. Wherein N is an integer greater than 1. Each charge pump cell 10 has an input, an output, and an enable; the input terminals of the N charge pump units 10 are interconnected to form an input voltage terminal (Vin, hereinafter referred to as Vin in fig. 1 and 2) connected to an input voltage, and the output terminals of the N charge pump units 10 are interconnected to form an output voltage terminal (Vout, hereinafter referred to as Vout in fig. 1 and 2) of the charge pump circuit. The ripple suppression circuit 20 includes a voltage division circuit 21, and N comparators 22. The voltage dividing circuit 21 is provided with an input end node and an output end node, the output end node is grounded, and N voltage dividing nodes are sequentially arranged between the input end node and the output end node. Each comparator 22 has a first input, a second input, and an output; the N comparators 22 are in one-to-one correspondence with the N voltage dividing nodes, and a first input end of each comparator 22 is connected with the corresponding voltage dividing node; the input node serves as a first comparison input and the second inputs of the N comparators 22 are interconnected to form a second comparison input. The clock generation control circuit 30 is connected to the output terminals of the N comparators 22 to receive the comparison signal output by each comparator 22; the N comparators 22 are in one-to-one correspondence with the N charge pump units 10, and the clock generation control circuit 30 is further connected to the enable terminals of the N charge pump units 10, so as to generate a control signal for enabling the corresponding charge pump unit 10 according to the comparison signal output by each comparator 22. At least one comparison input end of the first comparison input end and the second comparison input end is connected with at least one voltage end of the input voltage end and the output voltage end; one comparison input terminal is connected with one voltage terminal only, and one voltage terminal is connected with one comparison input terminal only; the comparison input terminal, which is not connected to any voltage terminal, is connected to the reference voltage terminal.
In the above-described scheme, the ripple suppression circuit 20 is provided, and at least one of the first comparison input terminal and the second comparison input terminal is connected to at least one of the input voltage terminal and the output voltage terminal; the clock generation control circuit 30 is enabled to control all or part of the charge pump units 10 in the N charge pump units 10 according to the comparison signals output by the different comparators 22, so that the number of enabled charge pump units 10 is increased or decreased, the driving capability is adaptively adjusted, the output voltage output by the output voltage terminal has lower ripple voltage, the output voltage ripple of the charge pump circuit is reduced, the effect of low ripple of the output voltage is achieved, a stable voltage source is provided for the memory circuit, and the interference of the power supply ripple on programming and reading of the memory is suppressed. And low ripple output without consuming chip area. The above structure will be described in detail with reference to the accompanying drawings.
The charge pump circuit as shown in fig. 1 includes N charge pump units 10, a ripple suppression circuit 20, and a clock generation control circuit 30. The above structures are described separately below.
When the charge pump unit 10 is provided, the number N of the charge pump units 10 is an integer greater than 1. Specifically, N may be an integer of not less than 2, 3, 4, 5, 8, 12, 16, 20, etc. Referring to fig. 1, each charge pump unit 10 has an input, an output, and an enable. The input terminals of the N charge pump cells 10 are interconnected to form an input voltage terminal connected to an input voltage, and the output terminals of the N charge pump cells 10 are interconnected to form an output voltage terminal of the charge pump circuit. The enable terminal of each charge pump unit 10 is connected to the clock generation control circuit 30, so that the clock generation control circuit 30 transmits an enable signal to each charge pump unit 10, thereby placing the charge pump unit 10 in an enabled state as enabling the charge pump unit 10.
When the ripple suppression circuit 20 is provided, referring to fig. 2, the ripple suppression circuit 20 includes a voltage division circuit 21, and N comparators 22. The voltage dividing circuit 21 is provided with an input end node and an output end node, the output end node is grounded, and N voltage dividing nodes are sequentially arranged between the input end node and the output end node. Specifically, as shown in fig. 2, n+1 voltage dividing resistors are connected in series with each other, namely, R10, R11, R12, …, and R1N, to form a voltage dividing circuit 21 connected in series. The output end of R1N is connected with the ground and serves as an output end node. Wherein the input of R10 serves as the input node. N+1 voltage dividing resistors are shared between the input end node and the output end node to form N voltage dividing nodes. When n+1 voltage dividing resistors are arranged, the resistance value of each voltage dividing resistor can be equal, and the voltage divided between any two adjacent voltage dividing nodes is the same.
As shown in fig. 2, each of the N comparators 22 has a first input, a second input, and an output. The negative terminal of each comparator 22 shown in fig. 2 is a first input terminal and the positive terminal is a second input terminal. It should be appreciated that each comparator 22 may also have a positive terminal as a first input and a negative terminal as a second input. The N comparators 22 are in one-to-one correspondence with the N voltage dividing nodes, and the first input end of each comparator 22 is connected to the corresponding voltage dividing node. The input node serves as a first comparison input and the second inputs of the N comparators 22 are interconnected to form a second comparison input.
The first comparison input end and the second comparison input end are used for being connected with an input voltage end, an output voltage end or a reference voltage end. Specifically, at least one comparison input end of the first comparison input end and the second comparison input end is connected with at least one voltage end of the input voltage end and the output voltage end; one comparison input terminal is connected with one voltage terminal only, and one voltage terminal is connected with one comparison input terminal only; the comparison input terminal, which is not connected to any voltage terminal, is connected to the reference voltage terminal. That is, at least one of the two comparison inputs is connected to one voltage terminal, which may be an input voltage terminal or an output voltage terminal. However, when connected, each comparison input terminal can only be connected with one voltage terminal, and one comparison input terminal and two voltage simultaneous terminals cannot be connected; each voltage terminal can only be connected with one comparison input terminal, and one voltage terminal cannot be connected with two comparison input terminals at the same time.
Specifically, the first comparison input end and the first reference voltage end (such as Vref1 in fig. 2, the same applies below) may be connected, and the second comparison input end and the output voltage end are connected, so as to facilitate self-adaptive adjustment of the number of charge enabling units based on the output voltage, and achieve the effect of low ripple of the output voltage. The first comparison input end and the input voltage end can be connected, the second comparison input end and the second reference voltage end (such as Vref2 in fig. 2, the following is the same), the number of charge enabling units can be adjusted in a self-adaptive mode based on the input voltage, and the effect of low ripple of the output voltage is achieved. The first comparison input end is connected with the input voltage end, the second comparison input end is connected with the output voltage end, the number of charge enabling units can be adjusted in a self-adaptive mode based on the input voltage and the output voltage, and the effect of low ripple of the output voltage is achieved. Or the first comparison input end is connected with the output voltage end, and the second comparison input end is connected with the input voltage end, so that the number of charge enabling units can be adjusted in a self-adaptive mode based on the input voltage and the output voltage, and the effect of low ripple of the output voltage is achieved.
Of course, referring to fig. 2, a first single-pole double-throw switch may be further disposed at the first comparison input end, where the stationary end of the first single-pole double-throw switch is connected to the first comparison input end, and the movable end of the first single-pole double-throw switch is capable of switching between the input voltage end and the first reference voltage end. The second comparison input end is provided with a second single-pole double-throw switch, the fixed end of the second single-pole double-throw switch is connected with the second comparison input end, and the movable end of the second single-pole double-throw switch can be switched between an output voltage end and a second reference voltage end. When the device is convenient for specific application, ripple suppression on different voltage ends is realized through switching of the two single-pole double-throw switches, the number of charge enabling units is convenient to adaptively adjust based on input voltage and output voltage, and the effect of low ripple of the output voltage is achieved. When two single-pole double-throw switches are arranged, an MOS tube can be used as the structure of the single-pole double-throw switch.
By the connection method shown above, the first comparison input terminal and the second comparison input terminal are connected with the input voltage terminal, the output voltage terminal or the reference voltage terminal, so that the voltage value output by at least one of the two comparison input terminals will have fluctuation with time, and is input to the voltage dividing circuit 21 and the N comparators 22, so that M comparators 22 in the N comparators 22 are one comparison signal, and the other N-M comparators 22 are the other comparison signal. For example, one comparison signal is "0" and the other comparison signal is "1". When the voltage value output from the comparison input terminal fluctuates with time, the number of M is also changed, and different comparison signals are input to the clock generation control circuit 30, so that the clock generation control circuit 30 controls the M charge pump units 10 in the N charge pump units 10 to be enabled according to the comparison signals input by the N comparators 22. That is, the ripple suppression circuit 20 generates the control signal of the clock generation control circuit 30 by the voltage value change of the first comparison input terminal and the second comparison input terminal.
When the clock generation control circuit 30 is provided, as shown in fig. 1, the clock generation control circuit 30 is connected to the output terminals of the N comparators 22 to receive the comparison signal output from each of the comparators 22. The N comparators 22 are in one-to-one correspondence with the N charge pump units 10, and the clock generation control circuit 30 is further connected to the enable terminals of the N charge pump units 10, so as to generate a control signal for enabling the corresponding charge pump unit 10 according to the comparison signal output by each comparator 22. That is, the comparison signals output from the N comparators 22 in the ripple suppression circuit 20 and the charge pump clock signal constitute the output signals of the clock generation controller circuit, and control whether the N charge pump units 10 are enabled or not correspondingly. That is, the clock generation control circuit 30 controls the operation of the N charge pump units 10 based on the control signal generated by the ripple suppression circuit 20. By providing the ripple suppression circuit 20, at least one of the first comparison input terminal and the second comparison input terminal is connected to at least one of the input voltage terminal and the output voltage terminal; the clock generation control circuit 30 is enabled to control all or part of the charge pump units 10 in the N charge pump units 10 according to the comparison signals output by the different comparators 22, so that the number of enabled charge pump units 10 is increased or decreased, the driving capability is adaptively adjusted, the output voltage output by the output voltage terminal has lower ripple voltage, the output voltage ripple of the charge pump circuit is reduced, the effect of low ripple of the output voltage is achieved, a stable voltage source is provided for the memory circuit, and the interference of the power supply ripple on programming and reading of the memory is suppressed. And low ripple output without consuming chip area. The above structure will be described in detail with reference to the accompanying drawings.
The charge pump circuit as shown in fig. 1 may further include a voltage adjustment circuit 40 connected to the output voltage terminal, the voltage adjustment circuit 40 being configured to detect whether the output voltage value output by the output voltage terminal reaches the target voltage value; and the voltage adjusting circuit 40 is also connected with the ripple suppression circuit 20 and the clock generation control circuit 30 to control the ripple suppression circuit 20 and the clock generation control circuit 30 to be turned on or off. The voltage adjustment circuit 40 is used for detecting the output voltage of the charge pump circuit and controlling the operating states of the clock generation control circuit 30 and the ripple suppression circuit 20. When the voltage adjustment circuit 40 detects that the output voltage of the charge pump circuit does not reach the target voltage value, the ripple suppression circuit 20 and the clock generation control circuit 30 are controlled to operate. When the voltage adjustment circuit 40 detects that the output voltage of the charge pump circuit reaches the target voltage value, the ripple suppression circuit 20 and the clock generation control circuit 30 are controlled to stop operating. That is, the clock generation control circuit 30 controls the operation of the N charge pump units 10 based on the control signal generated by the ripple suppression circuit 20 and the enable signal generated by the voltage adjustment circuit 40.
As the ripple suppression circuit 20 shown in fig. 2, the ripple suppression circuit 20 may further include an output load sampling circuit 23 connected to the output voltage terminal, where the output load sampling circuit 23 samples the load current of the output voltage terminal in a ratio mirror image, and converts the load current into the node voltage terminal (Vsa in fig. 2, the same applies below) through a set resistor 231. The node voltage end is used for being connected with the second comparison input end. Based on the load current of the output voltage terminal, 10 charge pump units are adaptively adjusted and enabled, ripple voltage generated at the output voltage terminal due to load current change of the output voltage terminal is reduced, and the effect of low ripple of the output voltage is achieved. The output load sampling circuit 23 in this embodiment is any type of load sampling circuit known in the art capable of mirroring the load current at the output voltage terminal by a ratio. As shown in fig. 2, the set resistor 231R0 may be sized according to the estimated steady voltage and the target voltage value.
Referring to fig. 2, the ripple suppression circuit 20 may further include a start-up circuit 24, the start-up circuit 24 including: a switching unit 241 and a control unit 242. Wherein, the first end of the switch unit 241 is connected to the output voltage end, and the second end of the switch unit 241 is connected to the node voltage end. The control unit 242 is connected to the voltage adjusting circuit 40 to receive the pump voltage signal (e.g. pumpen in fig. 2, the following description) output by the voltage adjusting circuit 40; and a control terminal of the switching unit 241 is connected to the control unit 242 to control the connection or disconnection of the first terminal and the second terminal according to the pump voltage signal. So as to reduce the ripple voltage in the starting stage and realize quick and stable and low ripple output. Referring to fig. 2, the switching unit 241 may be a PMOS transistor, and the P1MOS transistor in fig. 2 represents the switching unit 241 herein.
The manner of adjustment of the start-up and stabilization phases is illustrated below in connection with the structures shown in fig. 1 and 2.
The start-up phase is first introduced. The output voltage outputted from the output voltage terminal of the charge pump circuit does not reach the stable voltage, the pump voltage signal outputted from the voltage adjusting circuit 40 to the control unit 242 does not change in level, the control terminal of the switching unit 241 is closed, the node voltage terminal Vsa is connected to the second comparison input terminal, and the output voltage is inputted from the second comparison input terminal. The value of the output voltage is small at the beginning, and there is a case where N comparators 22 output the same comparison signal, so that the clock generation control unit 242 controls all of the N charge pump units 10 to be enabled, and N enabled charge pump units 10 occur, so that the output voltage rises rapidly, so as to provide a larger load current.
As the output voltage increases, the output voltage reaches a stable voltage, at this time, the pump voltage signal output from the voltage adjusting circuit 40 turns over in level, so that the switching unit 241 is turned off, and the second comparison input terminal is connected to the output voltage terminal through the output load sampling circuit 23. At this time, the load current at the output voltage terminal is multiplied by the node voltage Vsa of the set resistor 231R0, so that the node voltage Vsa at the second comparison input terminal changes with the load current. When the load current decreases, the node voltage Vsa input by the second comparison terminal decreases, and the number of M comparators 22 generating the enable signal in the N comparators 22 also decreases synchronously, thereby decreasing the number of the enabled charge pump units 10, and further enabling the output voltage to have a lower ripple voltage.
After the output voltage enters a stable phase, the output voltage of the charge pump circuit reaches a stable voltage. When the first comparison input terminal and the input voltage terminal are connected, the number of the charge pump unit 10 can be adjusted according to the change of the input voltage, thereby reducing the ripple voltage. The specific adjustment process is as follows: when the input voltage increases, the voltage input by the first comparison input terminal increases, so that the voltage at the first end of each comparator 22 increases, the number M of comparators 22 outputting the enabling signals for controlling the charge pump unit 10 in the comparators 22 decreases, and when the output voltage and the load current are the same, the lower number M of enabling the charge pump unit 10 can reduce the influence of the increase of the input voltage on the ripple voltage in the output voltage. Conversely, when the input voltage decreases, the voltage at the first end of each comparator 22 decreases, so that the number M of comparators 22 outputting the enable signal for controlling the charge pump unit 10 in the comparators 22 increases, thereby enabling more enable charge pump units 10 to have a number M, and ensuring the stability of the output voltage and the load current.
When the second comparison input terminal is connected to the output voltage terminal through the output load sampling circuit 23, the node voltage Vsa increases when the load current increases, the voltage input to the second comparison input terminal increases, the voltage of the second terminal of each comparator 22 increases, the number of comparators 22M that are output in the comparator 22 to control the charge pump unit 10 to enable increases, thereby increasing the number of enabled charge pump units 10, and more current can be supplied to the load without changing the output voltage. After the load current is stabilized, the number M of the enabled charge pump units is stabilized at the same time, so that the number M of the enabled charge pump units is prevented from being increased, and higher ripple voltage is brought. Conversely, when the load current decreases, the node voltage Vsa decreases, the voltage input to the second comparison input terminal decreases, the voltage at the second terminal of each comparator 22 decreases, and the number of comparators 22M that are output from the comparator 22 to control the charge pump unit 10 to enable decreases, thereby decreasing the number of enabled charge pump units 10 and further decreasing the ripple voltage.
In addition, when the first comparison input end is connected with the input voltage and the second comparison input end is connected with the second reference voltage, the working process mainly automatically controls the number of the enabled charge pump units 10 according to the fluctuation of the input voltage, and the working process is the working process when the first comparison input end is connected with the input voltage end in the stable stage.
When the first comparison input terminal is connected to the first reference voltage terminal and the second comparison input terminal is connected to the output voltage terminal through the output load sampling circuit 23, the number of enabled charge pump units 10 is automatically controlled based on the load current variation of the output voltage terminal only, and the operation process is the operation process when the second comparison input terminal is connected to the output load sampling circuit 23 in the aforementioned stable stage.
By providing the ripple suppression circuit 20, at least one of the first comparison input terminal and the second comparison input terminal is connected to at least one of the input voltage terminal and the output voltage terminal; the clock generation control circuit 30 is controlled to enable all or part of the N charge pump units 10 according to the comparison signals output by the different comparators 22, so that the output voltage output by the output voltage terminal has a lower ripple voltage by increasing or decreasing the number of enabled charge pump units 10.
In addition, the embodiment of the invention also provides a memory, which comprises any one of the charge pump circuits. By providing the ripple suppression circuit 20, at least one of the first comparison input terminal and the second comparison input terminal is connected to at least one of the input voltage terminal and the output voltage terminal; the clock generation control circuit 30 is controlled to enable all or part of the N charge pump units 10 according to the comparison signals output by the different comparators 22, so that the output voltage output by the output voltage terminal has a lower ripple voltage by increasing or decreasing the number of enabled charge pump units 10.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.
Claims (10)
1. A charge pump circuit, comprising:
n charge pump units; wherein N is an integer greater than 1; each charge pump unit is provided with an input end, an output end and an enabling end; the input ends of the N charge pump units are interconnected to form an input voltage end connected with an input voltage, and the output ends of the N charge pump units are interconnected to form an output voltage end of the charge pump circuit;
the ripple suppression circuit comprises a voltage division circuit and N comparators; the voltage dividing circuit is provided with an input end node and an output end node, the output end node is grounded, and N voltage dividing nodes are sequentially arranged between the input end node and the output end node; each comparator is provided with a first input end, a second input end and an output end; the N comparators are in one-to-one correspondence with the N voltage dividing nodes, and the first input end of each comparator is connected with the corresponding voltage dividing node; the input end node is used as a first comparison input end, and second input ends of the N comparators are interconnected to form a second comparison input end;
the clock generation control circuit is connected with the output ends of the N comparators so as to receive comparison signals output by each comparator; the N comparators are in one-to-one correspondence with the N charge pump units, and the clock generation control circuit is also connected with the enabling ends of the N charge pump units so as to generate control signals for enabling the corresponding charge pump units according to comparison signals output by each comparator;
at least one comparison input end of the first comparison input end and the second comparison input end is connected with at least one voltage end of the input voltage end and the output voltage end; one comparison input terminal is connected with one voltage terminal only, and one voltage terminal is connected with one comparison input terminal only; the comparison input terminal not connected to any voltage terminal is connected to the reference voltage terminal.
2. The charge pump circuit of claim 1, further comprising:
the voltage adjusting circuit is connected with the output voltage end and is used for detecting whether the output voltage value output by the output voltage end reaches a target voltage value or not;
and the voltage regulating circuit is also connected with the ripple suppression circuit and the clock generation control circuit to control the ripple suppression circuit and the clock generation control circuit to be turned on or turned off.
3. The charge pump circuit of claim 2, wherein the first comparison input is connected to a first reference voltage terminal and the second comparison input is connected to the output voltage terminal.
4. The charge pump circuit of claim 2, wherein the first comparison input is connected to the input voltage terminal and the second comparison input is connected to a second reference voltage terminal.
5. The charge pump circuit of claim 2, wherein the first comparison input is connected to the input voltage terminal and the second comparison input is connected to the output voltage terminal.
6. The charge pump circuit of claim 2, wherein the first comparison input is connected to the output voltage terminal and the second comparison input is connected to the input voltage terminal.
7. The charge pump circuit of claim 2, wherein a first single pole double throw switch is provided at the first comparison input; the fixed end of the first single-pole double-throw switch is connected with the first comparison input end, and the movable end of the first single-pole double-throw switch can be switched between the input voltage end and a first reference voltage end;
a second single-pole double-throw switch is arranged at the second comparison input end; the fixed end of the second single-pole double-throw switch is connected with the second comparison input end, and the movable end of the second single-pole double-throw switch can be switched between the output voltage end and a second reference voltage end.
8. The charge pump circuit of claim 2, wherein the ripple suppression circuit further comprises:
the output load sampling circuit is connected with the output voltage end; the output load sampling circuit is used for sampling the load current of the output voltage end according to the ratio mirror image and converting the load current into a node voltage end through a set resistor; the node voltage end is used for being connected with the second comparison input end.
9. The charge pump circuit of claim 8, wherein the ripple suppression circuit further comprises a start-up circuit; the start-up circuit includes:
the first end of the switch unit is connected with the output voltage end, and the second end of the switch unit is connected with the node voltage end;
the control unit is connected with the voltage adjusting circuit and used for receiving the pump voltage signal output by the voltage adjusting circuit; and the control end of the switch unit is connected with the control unit so as to control the connection or disconnection of the first end and the second end according to the pump voltage signal.
10. A memory comprising a charge pump circuit as claimed in any one of claims 1 to 9.
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| CN202110525835.9A CN115347769B (en) | 2021-05-14 | 2021-05-14 | Charge pump circuit and memory |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110525835.9A CN115347769B (en) | 2021-05-14 | 2021-05-14 | Charge pump circuit and memory |
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| CN115347769A CN115347769A (en) | 2022-11-15 |
| CN115347769B true CN115347769B (en) | 2024-03-22 |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6724241B1 (en) * | 2002-10-25 | 2004-04-20 | Atmel Corporation | Variable charge pump circuit with dynamic load |
| DE102005054207A1 (en) * | 2005-11-14 | 2007-05-16 | Infineon Technologies Ag | Charge pump circuit for use in e.g. dynamic random access memory, has evaluation circuit comparing voltage values with reference value, where time characteristics of voltage signal are changed in control loop depending on comparison result |
| CN105515370A (en) * | 2016-01-27 | 2016-04-20 | 上海华虹宏力半导体制造有限公司 | Charge pump circuit and memory |
| CN107453599A (en) * | 2017-07-17 | 2017-12-08 | 上海华虹宏力半导体制造有限公司 | The malleation charge pump of multivoltage output |
| CN109327133A (en) * | 2017-08-01 | 2019-02-12 | 北京兆易创新科技股份有限公司 | A kind of charge pump circuit |
| CN109600038A (en) * | 2018-12-27 | 2019-04-09 | 中国科学院微电子研究所 | A kind of charge pump system and memory with low output voltage ripple |
| CN111326203A (en) * | 2018-12-17 | 2020-06-23 | 北京兆易创新科技股份有限公司 | Circuit for controlling voltage ripple |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008054471A (en) * | 2006-08-28 | 2008-03-06 | Toshiba Corp | Voltage boosting circuit and voltage supplying circuit |
-
2021
- 2021-05-14 CN CN202110525835.9A patent/CN115347769B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6724241B1 (en) * | 2002-10-25 | 2004-04-20 | Atmel Corporation | Variable charge pump circuit with dynamic load |
| DE102005054207A1 (en) * | 2005-11-14 | 2007-05-16 | Infineon Technologies Ag | Charge pump circuit for use in e.g. dynamic random access memory, has evaluation circuit comparing voltage values with reference value, where time characteristics of voltage signal are changed in control loop depending on comparison result |
| CN105515370A (en) * | 2016-01-27 | 2016-04-20 | 上海华虹宏力半导体制造有限公司 | Charge pump circuit and memory |
| CN107453599A (en) * | 2017-07-17 | 2017-12-08 | 上海华虹宏力半导体制造有限公司 | The malleation charge pump of multivoltage output |
| CN109327133A (en) * | 2017-08-01 | 2019-02-12 | 北京兆易创新科技股份有限公司 | A kind of charge pump circuit |
| CN111326203A (en) * | 2018-12-17 | 2020-06-23 | 北京兆易创新科技股份有限公司 | Circuit for controlling voltage ripple |
| CN109600038A (en) * | 2018-12-27 | 2019-04-09 | 中国科学院微电子研究所 | A kind of charge pump system and memory with low output voltage ripple |
Non-Patent Citations (2)
| Title |
|---|
| 一种具有对称结构的低损耗低纹波电荷泵;万悦;吕坚;周云;阙隆成;田雷;;微处理机;20180615(03);3-7 * |
| 一种减小纹波电压的新型电荷泵调节电路;欧阳托日;黄鲁;;信息技术与网络安全;20180410(04);120-123 * |
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| CN115347769A (en) | 2022-11-15 |
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