CN115347757A - Power supply control system - Google Patents
Power supply control system Download PDFInfo
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- CN115347757A CN115347757A CN202110525671.XA CN202110525671A CN115347757A CN 115347757 A CN115347757 A CN 115347757A CN 202110525671 A CN202110525671 A CN 202110525671A CN 115347757 A CN115347757 A CN 115347757A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
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Abstract
A power control system is suitable for a direct current power supply, a power supply supporting ATX standard and a load unit. The power control system receives the output power of one of the power supply and the direct current power supply as an input voltage, and comprises a first switch to a seventh switch, a first direct current transformer and a second direct current transformer, and outputs various output voltages to the load unit under different states supporting Advanced Configuration and Power Interface (ACPI) by controlling a plurality of enabling ends and a plurality of disabling ends of the first switch to the seventh switch, the first direct current transformer and the second direct current transformer.
Description
Technical Field
The present invention relates to a power control system, and more particularly to a power control system compatible with an ATX standard power supply or a dc power supply as an input power.
Background
Most of the current motherboards supporting the X86 standard use a power supply supporting the ATX standard as an input power. However, IN an Embedded system (Embedded system), for convenience of power selection, a DC power supply of 12V or 24V is usually used as an input power supply, which is also called a DC-IN power supply. Therefore, in the development stage of the product, product planning personnel often have to develop different kinds of products for the same hardware architecture to make choices for the customers. This results in increased human resources and product development costs. In view of the above-mentioned phenomena, it is a problem to be solved whether other more flexible power control systems exist.
Disclosure of Invention
Therefore, the present invention is directed to a hardware device and a power control system compatible with both ATX standard power supply and dc power as input power.
Therefore, the present invention provides a power control system, which is suitable for a dc power supply, a power supply supporting the ATX standard, and a load unit, and includes a first switch to a seventh switch, a first dc transformer, and a second dc transformer.
The first switch comprises a first end for receiving a first input voltage with the magnitude of 5 volts from the power supply, an enabling end, a disabling end and a second end for outputting a first intermediate voltage with the magnitude of 5 volts. The second switch includes a first terminal electrically connected to the second terminal of the first switch for receiving the first intermediate voltage, an enable terminal, and a second terminal for outputting a first output voltage of 5 volts.
The first DC transformer includes an input terminal receiving a second input voltage of 12 volts from the power supply or the DC power supply, an enable terminal, a disable terminal, and an output terminal outputting a second intermediate voltage of 5 volts. The third switch includes a first terminal electrically connected to the output terminal of the first dc transformer for receiving the second intermediate voltage, an enable terminal, and a second terminal for outputting the first intermediate voltage.
The fourth switch includes a first terminal electrically connected to the second terminal of the third switch for receiving the first intermediate voltage, an enable terminal, a disable terminal, and an output terminal for outputting a second output voltage of 5 volts. The fifth switch includes a first terminal for receiving the second input voltage from the power supply or the dc power supply, an enable terminal, and a second terminal for outputting a third intermediate voltage.
The second dc transformer includes an input end electrically connected to the second end of the fifth switch for receiving the third intermediate voltage, an enable end, a disable end, and an output end for outputting a third output voltage of 3.3 volts. The sixth switch includes a first terminal electrically connected to the output terminal of the second dc transformer for receiving the third output voltage, an enable terminal, and a second terminal for outputting a fourth output voltage of 3.3 volts. The seventh switch includes a first terminal electrically connected to the output terminal of the second dc transformer for receiving the third output voltage, an enable terminal, a disable terminal, and a second terminal for outputting a fifth output voltage of 3.3 volts.
The first output voltage and the second output voltage are output in parallel to form a first parallel output voltage, the fourth output voltage and the fifth output voltage are output in parallel to form a second parallel output voltage, only one of the direct current power supply and the power supply can be electrically connected with the power supply control system, and the direct current power supply and the power supply can output the second input voltage, the first intermediate voltage, the third output voltage, the first parallel output voltage and the second parallel output voltage to the load unit.
Preferably, the power control system is further adapted to a chipset that supports Advanced Configuration and Power Interface (ACPI). The enable terminal and the disable terminal of the first switch receive the first input voltage and the second intermediate voltage, respectively. The enabling end of the second switch receives a signal indicating a state of depth Sx from the chipset. The enable terminal and the disable terminal of the first dc transformer receive the second input voltage and the first input voltage, respectively. The enabling end of the third switch receives the second intermediate voltage. The enable end and the disable end of the fourth switch respectively receive a signal indicating an S3 state from the chipset and the first input voltage. The enable terminal of the fifth switch receives the first input voltage. The enabling end of the second DC transformer receives the second input voltage and the first intermediate voltage. The disabling end of the second DC transformer receives the first input voltage. The enabling end of the sixth switch receives the signal indicating the state of the depth Sx from the chipset. The enable end and the disable end of the seventh switch receive the signal indicating the S3 state from the chipset and the first input voltage, respectively.
Preferably, the power control system further comprises a first diode, the first diode comprising an anode terminal for receiving the first input voltage and a cathode terminal electrically connected to the input terminal of the second dc transformer.
Preferably, when the chipset indicates that the load unit operates in the depth Sx state, the power control system outputs the first intermediate voltage and the third output voltage to the load unit. When the chipset indicates that the load unit operates in the deep S5 state, the power control system outputs the second input voltage, the first intermediate voltage, and the third output voltage to the load unit. When the chipset indicates that the load unit operates in the S5 state, the power control system outputs the second input voltage, the first intermediate voltage, the third output voltage, the first output voltage, and the fourth output voltage to the load unit.
When the chipset indicates that the load unit operates in the S0 state, the power control system outputs the second input voltage, the first intermediate voltage, the third output voltage, the first output voltage, the fourth output voltage, the second output voltage, and the fifth output voltage to the load unit. When the chipset indicates that the load unit operates in the S3 state, the power control system outputs the first intermediate voltage, the third output voltage, the first output voltage, the fourth output voltage, and the second output voltage to the load unit.
Preferably, when the signal indicating the state of the depth Sx output by the chipset is equal to logic 0, the second switch and the sixth switch are controlled to be turned off, so that the load unit operates in the state of the depth Sx. And when the signal indicating the depth Sx state output by the chip set is equal to logic 1, controlling the second switch and the sixth switch to be conducted so that the load unit does not operate in the depth Sx state.
Preferably, the power control system further comprises a first connector, a second connector, and a third connector. The first terminal and the second terminal both support ATX standard and respectively include 24 pins (pins) and 4 pins, and are electrically connected to the first switch, the fourth switch, the fifth switch, the seventh switch, the first dc transformer, the second dc transformer, and the first diode, and are configured to receive the first input voltage to output to the first terminal and the enabling terminal of the first switch, the disabling terminal of the fourth switch, the enabling terminal of the fifth switch, the disabling terminal of the seventh switch, the disabling terminal of the first dc transformer, the disabling terminal of the second dc transformer, and the disabling terminal of the first diode, and receive the second input voltage to output to the first terminal of the fifth switch, the first terminal and the enabling terminal of the first dc transformer, and the enabling terminal of the second dc transformer, when electrically connected to the power supply. The third connector is used for receiving the second input voltage when being electrically connected with the direct current power supply, so as to output the second input voltage to a 4 th pin and a 24 th pin of the first connector, and further output the second input voltage to the first end of the fifth switch, the first end and the enabling end of the first direct current transformer, and the enabling end of the second direct current transformer.
Compared with the prior art, the present invention controls the enable terminals and the disable terminals of the first switch to the seventh switch, the first dc transformer and the second dc transformer of the power control system, so that the hardware device can output various output voltages to the load unit in different states supporting Advanced Configuration and Power Interface (ACPI) no matter the power supply or the dc power supply is used as a power supply source.
[ description of the drawings ]
Other features and effects of the present invention will become apparent from the following detailed description of the embodiments with reference to the drawings, in which:
FIG. 1 is a block diagram illustrating one embodiment of a power control system of the present invention;
FIG. 2 is a schematic view illustrating three types of connectors of this embodiment;
FIG. 3 is a circuit diagram illustrating an aspect of a first switch of the embodiment;
FIG. 4 is a circuit diagram illustrating an aspect of a second switch of the embodiment; and
fig. 5 is a circuit diagram illustrating an aspect of a first dc transformer of the embodiment.
[ detailed description ] embodiments
Before the present invention is described in detail, it should be noted that in the following description, similar components are denoted by the same reference numerals.
Referring to fig. 1, an embodiment of the power control system of the present invention is applicable to a dc power supply, a power supply supporting the ATX standard, and a hardware device. The power control system 1 includes a first to seventh switches 11 to 17, a first DC transformer 18, a second DC transformer 19, and a first diode 20.
In this embodiment, the hardware device is, for example, an embedded system, and includes a chipset (PCH), a load unit, a chassis, and a motherboard. The chipset, the load unit and the power control system 1 are disposed on the motherboard and disposed in the enclosure together with the motherboard. The chipset supports Advanced Configuration and Power Interface (ACPI) standards. The load unit is, for example, a processor, at least one memory, and other application circuits and chips. The power supply supports the ATX standard. The dc power supply is, for example, an ac/dc transformer to convert ac mains power into a dc second input voltage, in this embodiment, the magnitude of the second input voltage is 12 volts, and in other embodiments, the second input voltage may be, for example, 24 volts or other values between 12 to 24 volts.
Referring to fig. 1 and 2, the power source of the hardware device is one of the power supply and the dc power source. More specifically, the main board is provided with a first connector 31, a second connector 32, and a third connector 33, so that when the power supply is disposed in the casing and the first input voltage V _5p0 \/atx is output through the first connector 31 and the second connector 32 or the dc power supply outputs the second input voltage +12VIN through the third connector 33, various voltages required for the operations of the chipset and the load unit can be provided.
More specifically, the first terminal 31 and the second terminal 32 both support ATX standard and respectively include 24 pins (pin) and 4 pins, and are electrically connected to the first switch 11, the fourth switch 14, the fifth switch 15, the seventh switch 17, the first dc transformer 18, the second dc transformer 19, and the first diode 20, and are configured to output the received first input voltage V _5p0 _atxwhen being electrically connected to the power supply, and output the received second input voltage +12VIN at a 4 th pin and a 24 th pin of the pins. When the power supply is not installed and the dc power supply inputs the second input voltage +12VIN through the third connector 33, the third connector outputs the second input voltage +12VIN to the 4 th pin and the 24 th pin of the first connector 31 and the second connector 32, and the first switch 11 to the seventh switch 17, the first dc transformer 18, the second dc transformer 19, and the first diode 20 are used to provide various voltages required by the operations of the chipset and the load unit. That is, when a power supply supporting the ATX standard is provided, the power supply outputs the first input voltage V _5p0 _atxthrough the first and second connectors 31 and 32, and when the power supply is powered by the dc power, the power supply is connected to the third connector 33, and outputs the second input voltage +12VIN to the first and second connectors 31 and 32 through the third connector 33, thereby providing various voltages required for the operations of the chipset and the load unit. Further, specifically, the following are: the third connector 33 of fig. 2 includes 8 pins, but in other embodiments, the third connector 33 may include other numbers of pins.
The first switch 11 includes a first terminal for receiving a first input voltage V _5p0 _atxof 5V from the power supply, an enable terminal for receiving the first input voltage V _5p0_atx, a disable terminal for receiving a second intermediate voltage V _5p0a _dc, and a second terminal for outputting a first intermediate voltage V _5p0 _aof 5V.
The second switch 12 includes a first terminal electrically connected to the second terminal of the first switch 11 for receiving the first intermediate voltage V _5p0_a, an enable terminal for receiving a signal SLP _ SUS # indicating a state of depth Sx from the chipset, and a second terminal for outputting a first output voltage 5VSB of 5 volts.
The first dc transformer 18 includes an input terminal for receiving the second input voltage +12VIN of 12V from the power supply or the dc power supply, an enable terminal for receiving the second input voltage +12VIN, a disable terminal for receiving the first input voltage V _5p0_atx, and an output terminal for outputting the second intermediate voltage V _5p0a _dcof 5V.
The third switch 13 includes a first terminal electrically connected to the output terminal of the first dc transformer 18 to receive the second intermediate voltage V _5p0a _dc, an enable terminal to receive the second intermediate voltage V _5p0a _dc, and a second terminal to output the first intermediate voltage V _5p0_a.
The fourth switch 14 includes a first terminal electrically connected to the second terminal of the third switch 13 for receiving the first intermediate voltage V _5p0_a, an enable terminal for receiving a signal SLP _ S3# from the chipset indicating the S3 state, a disable terminal for receiving the first input voltage V _5p0_atx, and an output terminal for outputting a second output voltage VCC of 5 volts.
The fifth switch 15 includes a first terminal for receiving the second input voltage +12VIN from the power supply or the dc power source, an enable terminal for receiving the first input voltage V _5p0_atx, and a second terminal for outputting a third intermediate voltage +12v _a.
The second dc transformer 19 includes an input terminal electrically connected to the second terminal of the fifth switch 15 for receiving the third intermediate voltage +12v _a, an enable terminal, a disable terminal, and an output terminal for outputting a third output voltage V _3p3 _aof 3.3V. The enable terminal receives the second input voltage +12VIN and the first intermediate voltage V _5p0_a. The disable terminal receives the first input voltage V _5p0_atx.
The sixth switch 16 includes a first terminal electrically connected to the output terminal of the second dc transformer 19 for receiving the third output voltage V _3p3_a, an enable terminal for receiving the signal SLP _ SUS # indicating the state of the depth Sx from the chipset, and a second terminal for outputting a fourth output voltage 3VSB of 3.3 volts.
The seventh switch 17 includes a first terminal electrically connected to the output terminal of the second dc transformer 19 to receive the third output voltage V _3p3_a, an enable terminal for receiving the signal SLP _ S3# indicating the S3 state from the chipset, a disable terminal for receiving the first input voltage V _5p0_atx, and a second terminal for outputting a fifth output voltage VCC3 with a magnitude of 3.3 volts.
The first diode 20 includes an anode terminal receiving the first input voltage V _5p0_atx, and a cathode terminal electrically connected to the input terminal of the second dc transformer 19.
More specifically, the first intermediate voltage V _5p0 _ais converted by at least one dc voltage converter, for example, first converting 3.3V and then converting 1.8V (or 1.5V) dc voltage to serve as a Standby power source (Standby power), so as to provide the Standby power source to the chipset as a power source required for operating in various power saving states of Advanced Configuration and Power Interface (ACPI).
In addition, the first output voltage 5VSB and the second output voltage VCC are also output in parallel as a first parallel output voltage 5v _dual. The fourth output voltage 3VSB and the fifth output voltage VCC3 are also output in parallel as a second parallel output voltage 3v _dual.
When the chipset indicates that the load unit is operating in the Deep Sx (Deep Sx) state, the chipset controls the output signal SLP _ SUS # indicating the Deep Sx state to be equal to logic 0, so that the second switch 12 and the sixth switch 16 are not turned on, and controls the output signal SLP _ S3# indicating the S3 state to be equal to logic 0, so that the fourth switch 14 and the seventh switch 17 are not turned on. At this time, when the power operation source of the hardware device is from the power supply, the first switch 11 is turned on, the first dc transformer 18 outputs the second intermediate voltage V _5p0a _dc, the third switch 13 is turned on to output the first intermediate voltage V _5p0_a, the fifth switch 15 is turned on, and the second dc transformer 19 outputs the third output voltage V _3p3_a. That is, the power control system 1 outputs the first intermediate voltage V _5p0 _aand the third output voltage V _3p3 _ato the load unit.
On the contrary, when the power operation source of the hardware device is from the dc power source, the first switch 11 is not turned on, the first dc transformer 18 outputs the second intermediate voltage V _5p0a _dc, the third switch 13 is turned on to output the first intermediate voltage V _5p0_a, the fifth switch 15 is not turned on, and the second dc transformer 19 outputs the third output voltage V _3p3_a. That is, the power control system 1 also outputs the first intermediate voltage V _5p0 _aand the third output voltage V _3p3 _ato the load unit.
When the chipset indicates that the load unit is operating in the Deep S5 (Deep S5) state, at this time, the signal SLP _ SUS # indicating the Deep Sx state output by the chipset is equal to logic 1, and the second switch 12 and the sixth switch 16 are controlled to be turned on, so that the power control system 1 outputs the second input voltage +12VIN, the first intermediate voltage V _5p0_a, and the third output voltage V _3p3 _ato the load unit.
When the chipset indicates that the load unit is operating in the S5 state, at this time, the signal SLP _ SUS # indicating the depth Sx state output by the chipset is equal to logic 1, the second switch 12 and the sixth switch 16 are controlled to be turned on, and the power control system 1 outputs the second input voltage +12VIN, the first intermediate voltage V _5p0_a, the third output voltage V _3p3_a, the first parallel output voltage 5v _finaloutput voltage via the first output voltage 5VSB, and the second parallel output voltage 3v _finaloutput voltage via the fourth output voltage 3VSB to the load unit.
When the chipset indicates that the load unit operates in the S0 state, at this time, the signal SLP _ SUS # indicating the depth Sx state output by the chipset is equal to logic 1, and the second switch 12 and the sixth switch 16 are controlled to be turned on, so that the power control system 1 outputs the second input voltage +12VIN, the first intermediate voltage V _5p0_a, the third output voltage V _3p3_a, the first parallel output voltage 5v _duplexoutput via the first output voltage 5VSB and the second output voltage VCC, and the second parallel output voltage 3v _duplexoutput via the fourth output voltage 3VSB and the fifth output voltage VCC3 to the load unit.
When the chipset indicates that the load unit operates in the S3 state, the chipset controls the output signal SLP _ SUS # indicating the depth Sx state to be equal to logic 1 so as to turn on the second switch 12 and the sixth switch 16, and controls the output signal SLP _ S3# indicating the S3 state to be equal to logic 1 so as to turn on the fourth switch 14 and the seventh switch 17. At this time, when the power operation source of the hardware device is from the power supply, the first switch 11 is turned on, the first dc transformer 18 outputs the second intermediate voltage V _5p0a _dc, the third switch 13 is turned on to output the first intermediate voltage V _5p0_a, the fifth switch 15 is turned on, and the second dc transformer 19 outputs the third output voltage V _3p3_a. That is, the power control system 1 outputs the first intermediate voltage V _5p0_a, the third output voltage V _3p3_a, the first parallel output voltage 5v _udual output through the first output voltage 5VSB and the second output voltage VCC, and the second parallel output voltage 3v _udual output through the fourth output voltage 3VSB to the load unit.
On the contrary, when the power operation source of the hardware device is from the dc power source, the first switch 11 is not turned on, the first dc transformer 18 outputs the second intermediate voltage V _5p0a _dc, the third switch 13 is turned on to output the first intermediate voltage V _5p0_a, the fifth switch 15 is not turned on, and the second dc transformer 19 outputs the third output voltage V _3p3_a. That is, the power control system 1 also outputs the first intermediate voltage V _5p0_a, the third output voltage V _3p3_a, the first parallel output voltage 5v _, duo via the first output voltage 5VSB and the second output voltage VCC, and the second parallel output voltage 3v _, duo via the fourth output voltage 3VSB to the load unit.
Referring to fig. 1 and 3, fig. 3 illustrates an aspect of the first switch 11. The first switch 11 includes two resistors R1, R2, an N-type transistor N1, and a P-type transistor P1. When the power supply outputs the first input voltage V _5p0 _atxthrough the first connector and when the first input voltage V _5p0 _atxreceived by the enable terminal reaches half of a rated value, the N-type transistor N1 is turned on and the P-type transistor P1 is turned on, so that the second terminal and the first terminal of the first switch 11 are turned on, that is, the first intermediate voltage V _5p0 _ais equal to the first input voltage V _5P0_ ATX. When the dc power supply outputs the second input voltage +12VIN through the second connector, and when the second intermediate voltage V _5p0a _dcreaches half of the rated value, the P-type transistor P1 is not turned on, and at this time, the N-type transistor N1 is also not turned on, so as to prevent the first intermediate voltage V _5p0 _afrom recharging the first input voltage V _5P0_ ATX.
Referring to fig. 1 and 4, fig. 4 illustrates one aspect of the second switch 12. The second switch 12 includes a P-type transistor P2. When the signal SLP _ SUS # indicating the state of the depth Sx from the chipset is equal to logic 1, the P-type transistor P2 is turned on, so that the second terminal and the first terminal of the second switch 12 are turned on, i.e., the first output voltage 5VSB is equal to the first intermediate voltage V _5p0 _.
Referring to fig. 1 and 5, fig. 5 illustrates one aspect of the first dc transformer 18. The first DC transformer 18 includes a resistor R4, an N-type transistor N2, and a first DC converter (DC-DC converter) 181. The first dc converter 181 has an enable terminal for controlling the first dc converter 181 to determine whether to convert an output voltage or not according to a logic signal received by the enable terminal. By the connection relationship between the resistor and the N-type transistor N2 and the enabling terminal of the first dc converter 181, the first dc converter 181 which originally has only the enabling purpose can be changed into the first dc transformer 18 which has two purposes of enabling and disabling. To be specifically noted are: in other embodiments, a dc transformer that has both enabling and disabling functions may be used.
Further, it is to be noted that: as seen in the prior art, the first to seventh switches 11 to 17, the first dc transformer 18, or the second dc transformer 19 have very many and known circuit configurations and forms, and the foregoing fig. 3 to 5 only illustrate the embodiments of two switches and one dc transformer simply and exemplarily, but not limited thereto.
In summary, by controlling the first switch to the seventh switch, the first dc transformer, and the plurality of enabled terminals and the plurality of disabled terminals of the second dc transformer of the power control system, the hardware device can output various output voltages to the load unit in different states supporting Advanced Configuration and Power Interface (ACPI) no matter using the power supply or the dc power source as a power supply source, so as to implement a power control system compatible with an ATX standard power supply or a dc power as an input power, and thus the objective of the present invention can be achieved.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (6)
1. A power control system adapted for a dc power supply, a power supply supporting ATX standard, and a load unit, comprising:
a first switch including a first terminal receiving a first input voltage of 5 volts from the power supply, an enable terminal, a disable terminal, and a second terminal outputting a first intermediate voltage of 5 volts;
a second switch including a first terminal electrically connected to the second terminal of the first switch for receiving the first intermediate voltage, an enable terminal, and a second terminal for outputting a first output voltage of 5 volts;
a first DC transformer including an input terminal receiving a second input voltage of 12 volts from the power supply or the DC power supply, an enable terminal, a disable terminal, and an output terminal outputting a second intermediate voltage of 5 volts;
a third switch, including a first end electrically connected to the output end of the first DC transformer for receiving the second intermediate voltage, an enable end, and a second end for outputting the first intermediate voltage;
a fourth switch including a first end electrically connected to the second end of the third switch for receiving the first intermediate voltage, an enable end, a disable end, and an output end for outputting a second output voltage of 5 volts;
a fifth switch including a first terminal receiving the second input voltage from the power supply or the dc power supply, an enable terminal, and a second terminal outputting a third intermediate voltage;
a second dc transformer including an input terminal electrically connected to the second terminal of the fifth switch for receiving the third intermediate voltage, an enable terminal, a disable terminal, and an output terminal for outputting a third output voltage of 3.3 volts;
a sixth switch including a first terminal electrically connected to the output terminal of the second dc transformer for receiving the third output voltage, an enable terminal, and a second terminal for outputting a fourth output voltage of 3.3 volts; and
a seventh switch including a first terminal electrically connected to the output terminal of the second dc transformer for receiving the third output voltage, an enable terminal, a disable terminal, and a second terminal for outputting a fifth output voltage of 3.3 volts;
the first output voltage and the second output voltage are output in parallel to form a first parallel output voltage, the fourth output voltage and the fifth output voltage are output in parallel to form a second parallel output voltage, only one of the direct current power supply and the power supply can be electrically connected with the power supply control system, and the direct current power supply and the power supply can output the second input voltage, the first intermediate voltage, the third output voltage, the first parallel output voltage and the second parallel output voltage to the load unit.
2. The power control system of claim 1, further adapted to a chipset supporting advanced configuration and power interface, wherein the enable terminal and the disable terminal of the first switch receive the first input voltage and the second intermediate voltage, respectively, the enable terminal and the disable terminal of the second switch receive a signal indicating a depth Sx state from the chipset, the enable terminal and the disable terminal of the first dc transformer receive the second input voltage and the first input voltage, respectively, the enable terminal and the disable terminal of the third switch receive the second intermediate voltage, the enable terminal and the disable terminal of the fourth switch receive a signal indicating an S3 state and the first input voltage, respectively, the enable terminal of the fifth switch receive the first input voltage, the enable terminal of the second dc transformer receive the second input voltage and the first intermediate voltage, the disable terminal of the second dc transformer receive the first input voltage, the sixth switch receive the signal indicating the depth Sx state and the enable terminal of the seventh switch receive the signal indicating the depth Sx state, respectively.
3. The power control system of claim 2, further comprising a first diode including an anode terminal receiving the first input voltage and a cathode terminal electrically connected to the input terminal of the second dc transformer.
4. The power control system of claim 3,
when the chipset indicates that the load unit is operating in the Sx state, the power control system outputs the first intermediate voltage and the third output voltage to the load unit,
when the chipset indicates the load unit to operate in the deep S5 state, the power control system outputs the second input voltage, the first intermediate voltage, and the third output voltage to the load unit,
when the chipset indicates that the load unit operates in the S5 state, the power control system outputs the second input voltage, the first intermediate voltage, the third output voltage, the first output voltage, and the fourth output voltage to the load unit,
when the chipset indicates the load unit to operate in the S0 state, the power control system outputs the second input voltage, the first intermediate voltage, the third output voltage, the first output voltage, the fourth output voltage, the second output voltage, and the fifth output voltage to the load unit,
when the chipset indicates that the load unit operates in the S3 state, the power control system outputs the first intermediate voltage, the third output voltage, the first output voltage, the fourth output voltage, and the second output voltage to the load unit.
5. The power control system of claim 4, wherein when the signal indicating the Sx state outputted from the chipset is equal to logic 0, the second switch and the sixth switch are controlled to be turned off, so that the load unit operates in the Sx state,
and when the signal indicating the depth Sx state output by the chip set is equal to logic 1, controlling the second switch and the sixth switch to be conducted so that the load unit does not operate in the depth Sx state.
6. The power control system of claim 4 further comprising a first connector, a second connector, and a third connector,
the first connector and the second connector both support the ATX standard and respectively include 24 pins and 4 pins, and are electrically connected to the first switch, the fourth switch, the fifth switch, the seventh switch, the first dc transformer, the second dc transformer, and the first diode, and are configured to receive the first input voltage to output to the first terminal and the enable terminal of the first switch, the disable terminal of the fourth switch, the enable terminal of the fifth switch, the disable terminal of the seventh switch, the disable terminal of the first dc transformer, the disable terminal of the second dc transformer, and the anode terminal of the first diode, and further receive the second input voltage to output to the first terminal of the fifth switch, the first terminal and the enable terminal of the first dc transformer, and the enable terminal of the second dc transformer, when electrically connected to the power supply,
the third connector is used for receiving the second input voltage when being electrically connected with the direct current power supply so as to output the second input voltage to a 4 th pin and a 24 th pin of the first connector, and further output the second input voltage to the first end of the fifth switch, the first end and the enabling end of the first direct current transformer and the enabling end of the second direct current transformer.
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| CN202110525671.XA CN115347757A (en) | 2021-05-14 | 2021-05-14 | Power supply control system |
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| Country | Link |
|---|---|
| CN (1) | CN115347757A (en) |
-
2021
- 2021-05-14 CN CN202110525671.XA patent/CN115347757A/en active Pending
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