CN115346589A

CN115346589A - Method and device for manufacturing failure bit map for memory chip test and electronic equipment

Info

Publication number: CN115346589A
Application number: CN202110517604.3A
Authority: CN
Inventors: 郑相贤; 杨红; 杨涛; 王文武; 陈睿; 李永亮
Original assignee: Institute of Microelectronics of CAS; Zhenxin Beijing Semiconductor Co Ltd
Current assignee: Institute of Microelectronics of CAS; Zhenxin Beijing Semiconductor Co Ltd
Priority date: 2021-05-12
Filing date: 2021-05-12
Publication date: 2022-11-15

Abstract

The application discloses a method and a device for manufacturing a failure bitmap for testing a memory chip and electronic equipment. The method comprises the following steps: dividing each memory bank of the memory chip under test into a first number of unit areas; selecting one untested memory bank from the chip, determining a memory space in the first memory, and dividing the memory space into a first number of units; sequentially testing each unit area in the selected storage library; marking failed units in the storage space according to the detection of a first failed bit in a unit area; according to the fact that all unit areas in the selected memory banks are tested, the chip is switched to any memory bank which is not tested, and the chip is switched to the memory bank which is not tested until all the memory banks in the chip are tested; a first fail bit map is constructed using each fail cell. The method greatly simplifies the manufacturing process, shortens the manufacturing time of the failure bitmap, improves the working efficiency and reduces the production cost.

Description

Method and device for manufacturing failure bit map for memory chip test and electronic equipment

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a method and an apparatus for manufacturing a fail bit map for memory chip testing, and an electronic device.

Background

The memory to be tested in the memory wafer test confirms the passing or failure information of the tested memory chip through the execution of each test item, and for the failure memory, a test failure bit map is made by taking a wafer as a unit in order to confirm the position information of the failure bit. The existing method is to test the tested memory chip, store the test pass or bit failure information of the whole area of the tested memory chip, read the stored information again, and make the failure bitmap according to the stored information, which is complex in process and long in time consumption. When a fail bit map is created for all unit bits of a memory chip to be tested, a mass production wafer test factory that tests a large number of wafers has a large amount of information stored in wafer units, and a lot of test time is required to process the fail bit map, which results in low work efficiency in a mass production system.

When a memory wafer test is executed, a verification operation is performed after a "fail bit map" for verifying a defective bit position of a memory is created based on a plurality of test items by using an operation margin test of the memory and an execution result of each test item. The time for searching the area of the test memory is increased by confirming the position of the failure bit according to the capacity of the memory product. Since many test items are generated with defects, the number of test items to be confirmed by the fail bit map is increasing, and if it is stored as a wafer-by-wafer bit map, the size of the bit map stored as a wafer-by-wafer bit map becomes very large.

Disclosure of Invention

The invention aims to provide a method and a device for manufacturing a failure bitmap for testing a memory chip and electronic equipment. The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview and is intended to neither identify key/critical elements nor delineate the scope of such embodiments. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is presented later.

According to an aspect of the embodiments of the present disclosure, there is provided a method for making a fail bit map for memory chip testing, including:

dividing each memory bank of the memory chip under test into a first number of unit areas; the chip comprises a plurality of pins, and each pin corresponds to at least one storage bank;

selecting one untested memory bank from the chip, determining a memory space in a first memory prepared in advance, and dividing the memory space into the first number of units; the first number of cells correspond one-to-one to all the unit areas in the selected bank;

sequentially testing each unit area in the selected storage library;

marking failed units in the storage space according to the detection of a first failed bit in one unit area; the failure unit is a unit corresponding to the unit area where the failure bit is located;

according to the fact that all the unit areas in the selected storage banks are tested, the chip is switched to any storage bank which is not tested, and the chip is switched to the storage bank which is not tested until all the storage banks in the chip are tested;

and constructing a first failure bit map by using each failure unit.

According to another aspect of the embodiments of the present disclosure, there is provided a fail bit map making apparatus for memory chip testing, including:

a dividing module for dividing each memory bank of the memory chip to be tested into a first number of unit areas; the chip comprises a plurality of pins, and each pin corresponds to at least one storage bank;

a selection module, configured to select an untested memory bank from any one of the memory banks in the chip, determine a memory space in a first memory prepared in advance, and divide the memory space into the first number of units; the first number of cells correspond one-to-one to all the unit areas in the selected bank;

a test module, configured to sequentially test each unit area in the selected repository;

a first marking module, configured to mark a failed unit in the storage space according to a first failed bit detected in one unit area; the failure unit is a unit corresponding to the unit area where the failure bit is located;

a diversion module, configured to divert to any untested memory bank from the chip according to the completion of testing all the unit areas in the selected memory bank until all the memory banks in the chip are tested;

and the construction module is used for constructing a first failure bitmap by utilizing each failure unit.

According to another aspect of the embodiments of the present disclosure, there is provided an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement any one of the above fail bit map making methods for memory chip testing.

According to another aspect of the embodiments of the present disclosure, there is provided a computer-readable storage medium having a computer program stored thereon, the program being executed by a processor to implement the fail bit map making method for memory chip testing of any one of the above.

The technical scheme provided by one aspect of the embodiment of the disclosure can have the following beneficial effects:

according to the method for manufacturing the failure bit map for the memory chip test, the failure units corresponding to the unit areas where the failure bits are located are marked in the storage space of the first memory in the test process, and the failure bit map can be constructed after the test is completed.

Additional features and advantages of the disclosure will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the disclosure. The objectives and other advantages of the disclosure will be realized and attained by the structure particularly pointed out in the written description and claims thereof as well as the appended drawings.

Drawings

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present disclosure, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a flow chart of a method for generating a fail bit map for memory chip testing according to an embodiment of the present application;

FIG. 2 shows parameters of LPDDR 4;

FIG. 3 shows a schematic diagram of dividing a unit area of an IO Pin;

FIG. 4 is a diagram illustrating the correspondence relationship between each unit area of the storage library and each unit of the storage space;

FIG. 5 is a flowchart illustrating a method for generating a fail bit map for testing a memory chip according to another embodiment of the present application;

FIG. 6 shows a second fail bit map;

FIG. 7 is a schematic diagram of all the banks corresponding to an IO Pin in FIG. 6;

FIG. 8 is a flowchart illustrating a method for generating a fail bit map for testing a memory chip according to another embodiment of the present application;

FIG. 9 is a block diagram of an electronic device according to another embodiment of the present application;

FIG. 10 shows a schematic diagram of a computer-readable storage medium of another embodiment of the present application.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.

Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.

As shown in fig. 1, an embodiment of the present application provides a method for making a fail bit map for memory chip testing, including:

s10, dividing each memory bank of the tested memory chip into a first number of unit areas; the tested memory chip comprises a second number of input and output pins, and each input and output pin corresponds to a third number of memory banks; each memory bank includes a fourth number of bits.

As shown in FIG. 2, for example, LPDDR4 × 8 with 4G bits has 8 IO pins, which are labeled IO0, IO1, IO2, IO3, IO4, IO5, IO6 and IO7. As shown in fig. 3, each IO Pin corresponds to 16 banks (banks), one Bank includes 32M bits, and one Bank includes 32 unit regions, where X represents a row address, Y represents a column address, and FB represents a fail bit. LPDDR is the abbreviation of Low Power Double Data Rate SDRAM, i.e., low Power memory. IO Pin represents an input/output Pin. The input Pin in the IO Pin is used for receiving an input signal transmitted from the test system to the pad of the chip to be tested, and the output Pin in the IO Pin is used for transmitting a signal of the pad of the chip to be tested to the test system. The test system judges whether the test of the tested chip passes or fails according to the output signal. That is, in the example of 4 gbits LPDDR4 × 8, the first number is 32, the second number is 8, the third number is 16, and the fourth number is 33554432.

S20, selecting an untested memory bank from the tested memory chip, determining a memory space in a first memory prepared in advance, and dividing the memory space into a first number of units; the first number of units in the first memory are in one-to-one correspondence with the first number of unit areas in the selected memory bank. The first memory prepared in advance is a memory external to the memory chip under test.

The first number of cells is divided into a third number of chunks, and the third number of chunks corresponds to the third number of banks one to one. And dividing the third number of chunks into a second number of blocks, wherein the second number of blocks corresponds to the second number of input/output pins one to one.

Taking LPDDR4 × 8 of 4 gbits as an example, each megabit area in LPDDR4 × 8 is taken as one unit area, and there are 32 unit areas in total. A storage space is selected in the second memory and is divided into 32 units with the same size, and the 32 units are in one-to-one correspondence with the 32 unit areas in the LPDDR4 x 8. For example, each unit can be set to 1 bit, that is, 1 bit in the first memory is used to correspondingly represent one unit area in LPDDR4 × 8, and the first memory always shares 32 bits to represent one Bank. The 4G bit LPDDR4 x 8 includes 8 IO Pin in total, each IO Pin corresponds to 16 banks.

As shown in fig. 4, unit regions (1), (2), (3), (8230 \ 8230:

corresponding to the units (1), (2), (3), (8230), (32) in the storage space B respectively.

S30, sequentially testing each unit area in the selected storage library, and marking a failure unit in the storage space when a first failure bit is detected in one unit area; the fail cell is a cell corresponding to a unit area where the fail bit is located.

In some embodiments, after the first failed bit is detected in one unit area, the testing of the rest bits of the unit area is stopped, and the testing of the next unit area is switched. According to the embodiment, all bits in the unit area do not need to be tested, and the rest bits are not tested as long as a failure bit is tested, so that the test time is greatly shortened.

All unit regions of IO0 are shown in fig. 3. Even if only one bit in the unit area (1) of fig. 3 fails, a cell in the first memory corresponding to the unit area (1) is automatically marked as a failed cell, so that the time for making a failed bitmap when a test item is performed can be reduced. For example, if each cell is set to 1 bit, the cell corresponding to the unit area (1) is automatically marked as a failed cell when at least one bit in the unit area (1) fails. Since the space required to store each cell is very small, the storage capacity required in the first memory is greatly reduced.

S40, when all the unit areas in the selected memory bank are tested, turning to S20 until all the memory banks of the tested memory chip are tested.

And S50, constructing a first failure bit map by utilizing the failure units.

The failure unit corresponds to a unit region with a failure bit, and through the first failure bit map, a worker can visually observe the generation position of the failure bit, for example, as shown in fig. 4, in the first failure bit map, if the unit (1) is a failure unit, the unit region (1) corresponding to the unit (1) is the unit region with the failure bit.

In mass production, it is only necessary to confirm the approximate position of the fail bit in the whole area of the memory chip to satisfy the analysis requirement, so that it is not necessary to make a fail bit map of all bits of one memory chip which takes a long test time. Compared with the technical scheme that the memory chip to be tested is tested in the prior art, the test passing or bit failure information obtained by the test is stored, the stored information is read again, and the failure bitmap is manufactured according to the stored information, the method of the embodiment has the advantages that the process is greatly simplified, the manufacturing time consumption of the failure bitmap is shortened, the working efficiency is improved, and the production cost is reduced.

As shown in fig. 5, in some embodiments, the method further comprises:

s60, marking the chunk where each failure unit is located as a failure chunk, and marking the block corresponding to each failure chunk as a failure block to obtain a second failure bitmap; wherein, each chunk is respectively corresponding to each storage library one by one; each block corresponds to each input/output pin one by one.

As shown in fig. 6, it can be intuitively determined from the second failure bitmap that the specific region corresponding to which IO Pin fails in LPDDR4 × 8 with 4G bits exists, and the region corresponding to the IO Pin has a failure bit, so that the IO Pin having the failure bit can be intuitively known from the second failure bitmap shown in fig. 6 according to the failure flag. Each block corresponds to a memory bank, and each block corresponds to an input/output pin. As shown in FIG. 7, each IO Pin includes 16 banks, the Bank with the invalid bit is marked, so that it can be visually displayed which Bank has the invalid bit. In some cases, the worker only needs to know that the area corresponding to which specific pin has the failure bit, and the worker can intuitively determine which area corresponding to which pin has the failure bit through the second failure bit map.

As shown in fig. 8, in some embodiments, prior to S50, the method further comprises:

s40', after the first failure bit is detected in one unit area, testing the rest bits of the unit area continuously until all the bits in the unit area are tested, then testing the next unit area, and storing the test passing or failure information of each bit in a second memory prepared in advance while testing. The second memory prepared in advance is a memory outside the memory chip under test.

After S50 or S60, the method further comprises:

and S70, judging the repairability of the chip according to the test passing or failure information of each bit through a memory redundancy analyzer.

When the repairability of the Memory chip is judged by the MRA (Memory Redundancy Analyzer), the failure Memory information of fig. 2 is required. Both the first memory and the second memory are selectively used according to the purpose of use in the present embodiment.

The test result of the tested memory chip is stored in the first memory, and simultaneously, the whole capacity of the tested memory chip is divided into required areas to be stored in the second memory, so that the failure bit map can be manufactured in more test items, meanwhile, the test time of a large number of wafers is shortened, and the generation position of the failure bit of the tested memory chip can be checked through the first memory.

Another embodiment of the present application provides a fail bit map making apparatus for memory chip testing, including:

a selection module, configured to select an untested memory bank from the chip, determine a memory space in the first memory, and divide the memory space into the first number of units; the first number of cells corresponds one-to-one to all the unit areas in the selected bank;

In certain embodiments, the apparatus further comprises:

the second marking module is used for marking the chunk where each failure unit is located as a failure chunk, marking the block corresponding to each failure chunk as a failure block, and obtaining a second failure bitmap; wherein, each chunk corresponds to each storage library one by one; each block is in one-to-one correspondence with each pin.

In some embodiments, the test module is further configured to, before all the unit regions in the selected repository are tested, after a first failed bit is detected in one of the unit regions, stop testing the remaining bits of the unit region, and switch to testing a next unit region.

In some embodiments, the test module is further configured to, before the time when all the unit areas in the selected repository are tested, after a first failed bit is detected in one of the unit areas, continue to test remaining bits in the unit area until all the bits in the unit area are tested, test the next unit area, and store the test pass or fail information of each of the bits in a second pre-prepared memory while the test is performed.

The device for manufacturing the fail bit map for testing the memory chip provided by this embodiment can implement the method for manufacturing the fail bit map according to any of the above embodiments, in the testing process, the fail unit corresponding to the unit region where the fail bit is located is marked in the storage space of the first memory, and the fail bit map can be constructed after the testing is completed.

Another embodiment of the present application provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the fail bit map making method for memory chip testing according to any of the above embodiments. As shown in fig. 9, the electronic device 10 may include: the system comprises a processor 100, a memory 101, a bus 102 and a communication interface 103, wherein the processor 100, the communication interface 103 and the memory 101 are connected through the bus 102; the memory 101 stores a computer program that can be executed on the processor 100, and the processor 100 executes the computer program to perform the method provided by any one of the foregoing embodiments.

The Memory 101 may include a high-speed Random Access Memory (RAM), and may also include a non-volatile Memory (non-volatile Memory), such as at least one disk Memory. The communication connection between the network element of the system and at least one other network element is realized through at least one communication interface 103 (which may be wired or wireless), and the internet, a wide area network, a local network, a metropolitan area network, and the like can be used.

The bus 102 may be an ISA bus, PCI bus, EISA bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. The memory 101 is used for storing a program, and the processor 100 executes the program after receiving an execution instruction, and the method disclosed in any of the foregoing embodiments of the present application may be applied to the processor 100, or implemented by the processor 100.

Processor 100 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware or instructions in the form of software in the processor 100. The Processor 100 may be a general-purpose Processor, and may include a Central Processing Unit (CPU), a Network Processor (NP), and the like; but may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components. The various methods, steps, and logic blocks disclosed in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in the memory 101, and the processor 100 reads the information in the memory 101 and completes the steps of the method in combination with the hardware.

The electronic device provided by the embodiment of the application and the method provided by the embodiment of the application have the same inventive concept and have the same beneficial effects as the method adopted, operated or realized by the electronic device.

Another embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored, where the computer program is executed by a processor to implement the fail bit map making method for testing a memory chip according to any of the above embodiments. Referring to fig. 10, a computer-readable storage medium is shown as an optical disc 20, on which a computer program (i.e., a program product) is stored, and when the computer program is executed by a processor, the computer program performs the method provided by any of the foregoing embodiments.

It should be noted that examples of the computer-readable storage medium may also include, but are not limited to, a phase change memory (PRAM), a Static Random Access Memory (SRAM), a Dynamic Random Access Memory (DRAM), other types of Random Access Memories (RAM), a Read Only Memory (ROM), an Electrically Erasable Programmable Read Only Memory (EEPROM), a flash memory, or other optical and magnetic storage media, which are not described in detail herein.

The computer-readable storage medium provided by the above-mentioned embodiments of the present application and the method provided by the embodiments of the present application have the same advantages as the method adopted, executed or implemented by the application program stored in the computer-readable storage medium.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, the person skilled in the art can also design a method which is not exactly the same as the method described above. Further, although the embodiments are described separately above, this does not mean that the measures in the respective embodiments cannot be used advantageously in combination.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the disclosure, and these alternatives and modifications are intended to fall within the scope of the disclosure.

Claims

1. A method for making a fail bit map for memory chip testing, comprising:

optionally selecting an untested memory bank from the chip, determining a memory space in a first memory prepared in advance, and dividing the memory space into the first number of units; the first number of cells correspond one-to-one to all the unit areas in the selected bank;

sequentially testing each unit area in the selected storage library;

marking failed cells in said storage space based on detecting a first failed bit in one of said cell regions; the failure unit is a unit corresponding to the unit area where the failure bit is located;

turning to any untested memory bank from the chip until all the memory banks in the chip are tested according to the completion of the test of all the unit areas in the selected memory bank;

and constructing a first failure bit map by using each failure unit.

2. The method of claim 1, further comprising:

marking the chunk where each failure unit is located as a failure chunk, and marking the block corresponding to each failure chunk as a failure block to obtain a second failure bitmap; wherein, each chunk corresponds to each storage bank one by one; each block is in one-to-one correspondence with each pin.

3. The method according to claim 1, wherein before all of the unit areas in the selected bank are tested, the method further comprises:

and after the first failure bit is detected in one unit area, stopping testing the rest bits of the unit area, and switching to testing the next unit area.

4. The method according to claim 1, wherein before said time when all of said unit regions in said selected bank are tested, said method further comprises:

and after detecting a first failure bit in one unit area, continuously testing the rest bits in the unit area until all the bits in the unit area are tested, then testing the next unit area, and storing the test passing or failure information of each bit in a second memory prepared in advance while testing.

5. The method of claim 4, further comprising: and judging the repairability of the chip according to the test passing or failure information of each bit through a memory redundancy analyzer.

6. An apparatus for generating a fail bit map for memory chip testing, comprising:

a selection module, configured to select an untested memory bank from the chip, determine a memory space in a first memory prepared in advance, and divide the memory space into the first number of units; the first number of cells corresponds one-to-one to all the unit areas in the selected bank;

a first marking module, configured to mark a failed unit in the storage space according to a first failed bit detected in one of the unit areas; the failure unit is a unit corresponding to the unit area where the failure bit is located;

7. The apparatus of claim 6, further comprising:

the second marking module is used for marking the chunk where each failure unit is located as a failure chunk, marking the block corresponding to each failure chunk as a failure block, and obtaining a second failure bitmap; wherein, each chunk corresponds to each storage bank one by one; each block is in one-to-one correspondence with each pin.

8. The apparatus of claim 6, wherein the testing module is further configured to stop testing the remaining bits of the unit areas and switch to testing the next unit area after detecting the first failed bit in one unit area before all the unit areas in the selected bank are tested.

9. The apparatus of claim 6, wherein the testing module is further configured to, before the testing of all the unit areas in the selected repository is completed, after a first failed bit is detected in one of the unit areas, continue to test remaining bits in the unit area until all the bits in the unit area are tested, test a next unit area, and store test pass or fail information of each of the bits in a second memory prepared in advance while the testing is performed.

10. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor executing the program to implement the method of any one of claims 1-5.

11. A computer-readable storage medium, on which a computer program is stored, characterized in that the program is executed by a processor to implement the method according to any of claims 1-5.