CN115344441A - Method, system, device and storage medium for adaptive testing of chip - Google Patents
Method, system, device and storage medium for adaptive testing of chip Download PDFInfo
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- CN115344441A CN115344441A CN202210823754.1A CN202210823754A CN115344441A CN 115344441 A CN115344441 A CN 115344441A CN 202210823754 A CN202210823754 A CN 202210823754A CN 115344441 A CN115344441 A CN 115344441A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test input/output devices or peripheral units
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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- G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
- G06F16/20—Information retrieval; Database structures therefor; File system structures therefor of structured data, e.g. relational data
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Abstract
The invention provides a method, a system, a device and a storage medium for self-adaptive testing of chips, which can automatically adapt to different chips, adjust the parameters of a test program aiming at the performance parameters of the chip to be tested, reduce the test cost and improve the test efficiency, and the method comprises the following steps: establishing a database, wherein chip data of historical detection are stored in the database; acquiring known characteristics of a chip to be tested, and matching the known characteristics with a database to obtain characteristic parameters of the chip to be tested; pushing a test program corresponding to the chip according to the matching result; and testing the chip by adopting a test program.
Description
Technical Field
The invention relates to the technical field of chip testing, in particular to a method, a system, a device and a storage medium for self-adaptive testing of a chip.
Background
At present, the types of chips are various, communication interfaces of different types of chips are different, and traditional programming test equipment can only meet a certain communication protocol chip, so that the traditional programming test equipment can only program and test a single type of chip generally, a great deal of effort and time of testers are required to write programs when the traditional programming test equipment is used for programming test, a great deal of labor cost is consumed, the test efficiency is low, the traditional programming test equipment can not test the performance parameters of each chip in a targeted manner, meanwhile, the types of the test chips are very limited, and the chips in the market are difficult to cover various brands and models of the chips.
Disclosure of Invention
In view of the above problems, the present invention provides a method, a system, a device and a storage medium for adaptive testing of chips, which can automatically adapt to different chips, and can adjust parameters of a test program according to performance parameters of the chip to be tested, thereby reducing test cost and improving test efficiency.
The technical scheme is as follows: a self-adaptive test method of a chip is characterized by comprising the following steps:
establishing a database, wherein chip data of historical detection are stored in the database;
acquiring known characteristics of a chip to be tested, and matching the known characteristics with a database to obtain characteristic parameters of the chip to be tested;
pushing a test program corresponding to the chip according to the matching result;
and testing the chip by adopting a test program.
Further, the reading of the known characteristics of the chip to be tested and the matching of the database to obtain the characteristic parameters of the chip to be tested specifically include:
and acquiring the ID of the chip to be tested, and matching the ID with the database to obtain the characteristic parameters of the chip to be tested.
Further, the characteristic parameters of the chip to be tested include any one or more of a communication protocol, a brand, a capacity, a voltage, a current, a power-on time sequence, an encryption area, a register, a package size, a frequency and a baud rate.
Further, the pushing the test program corresponding to the chip according to the matching result includes:
pushing a test item matched with a chip to be tested;
calling a corresponding test program template from a test program database according to the pushed test items;
and automatically filling characteristic parameters of the chip to be tested in the called test program template to form the test program.
Further, when the information of the chip to be tested is not included in the retrieved database, a directory corresponding to the chip is established in the database, and a vocabulary entry of the characteristic parameter is set in the directory corresponding to the chip for inputting the corresponding characteristic parameter.
Furthermore, the information of the design manual of the input chip is identified through the text, the keyword search of the characteristic parameters is carried out on the text information, and all searched keywords matched with the characteristic parameters are pushed to the information input personnel for reference.
A chip test system, includes chip anchor clamps and test circuit board and treater, it is a plurality of can install on the test circuit board the chip anchor clamps, its characterized in that: the processor is used for executing the self-adaptive test method of the chip.
Furthermore, a plurality of interface circuits are respectively arranged on the test circuit board corresponding to each pin of the chip, each interface circuit at least comprises a power supply interface, a grounding interface and an I/O interface, a controllable switch is respectively arranged on each interface circuit, the controllable switches are connected with the processor and the test loop, the processor reads the packaging information in the characteristic parameters of the chip to be tested, which is obtained by matching, and controls the controllable switches corresponding to the interface circuits to be closed according to the packaging information of the chip to be tested, so that the interface circuit of each pin on the test circuit board corresponds to the pin packaged by the chip to be tested.
A computer device, comprising: comprising a processor, a memory, and a program;
the program is stored in the memory, and the processor calls the program stored in the memory to execute the adaptive testing method of the chip.
A computer-readable storage medium characterized by: the computer-readable storage medium is used for storing a program for executing the adaptive testing method of the chip as described above.
Compared with the related technology, the chip self-adaptive testing method, the chip self-adaptive testing system, the chip self-adaptive testing device and the chip self-adaptive testing storage medium have the advantages that the database is arranged to record chip data, other characteristic parameters can be automatically adapted to the chip in the database according to known characteristics of the chip, the testing item and the testing program template can be adapted, then the adapted characteristic parameters are automatically filled in the testing program template to generate a testing program, and the testing program can be used for testing the chip; by using the mode, the test program can carry out customized adjustment and adaptation on the performance parameters of each chip to be tested, thereby being beneficial to improving the accuracy of the test result; the application provides a chip test system, a plurality of test fixture can be connected to a test circuit board, can test a plurality of chips that await measuring simultaneously, further improves efficiency of software testing.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.
FIG. 1 is a schematic diagram illustrating steps of a method for adaptive testing of a chip according to an embodiment;
FIG. 2 is a schematic diagram of a chip holder according to an embodiment;
FIG. 3 is a schematic diagram of a circuit test board according to an embodiment;
FIG. 4 is a schematic diagram of an interface circuit of a pin of one of the chips of the circuit test board in the embodiment;
FIG. 5 is a diagram illustrating an internal structure of a computer device according to an embodiment.
Detailed Description
In the following description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific aspects of embodiments of the invention or by which embodiments of the invention may be practiced. It is to be understood that embodiments of the invention may be utilized in other respects, and include structural or logical changes not depicted in the figures. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
It should be understood that although steps are illustrated in the disclosed embodiments as numbered for ease of understanding, the numbers do not represent the order in which the steps are performed, nor do they represent that the steps numbered in order must be performed together. It should be understood that one or several of the steps numbered in sequence may be individually performed to solve the corresponding technical problem and achieve a predetermined technical solution. Even though illustrated in the figures as a plurality of steps listed together, does not necessarily indicate that the steps must be performed together; the figures are merely exemplary to list the steps together for ease of understanding.
As shown in fig. 1, the adaptive testing method for a chip of the present invention at least includes the following steps:
step 1: establishing a database, wherein chip data of historical detection are stored in the database;
step 2: acquiring known characteristics of a chip to be tested, and matching the known characteristics with a database to obtain characteristic parameters of the chip to be tested;
and step 3: pushing a test program corresponding to the chip according to the matching result;
and 4, step 4: and testing the chip by adopting a test program.
Specifically, in an embodiment of the present invention, in step 1, a database is established, in which chip data of historical detection is stored, and specifically, in this embodiment, the characteristic parameters of the chip to be tested, which are held in the database, include a communication protocol, a brand, a capacity, a voltage, a current, a power-on timing sequence, an encryption area, a register, a package size, a frequency, and a baud rate.
Taking the communication protocol as an example, the chip may include a chip based on eprom, a chip based on SWD protocol, a chip based on I2C protocol, a chip based on SPI protocol, a chip based on java protocol, an Lvds interface display screen chip, and so on.
In step 2, the ID of the chip to be tested is obtained, the characteristic parameters of the chip to be tested are obtained from the database in a matching manner according to the ID of the chip to be tested, the obtained characteristic parameters may be any one or more of a communication protocol, a brand, a capacity, a voltage, a current, a power-on time sequence, an encryption area, a register, a package size, a frequency and a baud rate, and are specifically determined according to the test items of the chip
In step 3, pushing a test program corresponding to the chip according to the matching result, including:
pushing a test item matched with a chip to be tested;
calling a corresponding test program template from a test program database according to the pushed test items;
and automatically filling characteristic parameters of the chip to be tested in the called test program template to form a test program.
Subsequently, in step 4, a chip test is performed using a test program.
In the above embodiment, the data of the chip to be tested is stored in the database, and when the information of the chip to be tested is not included in the database, a directory corresponding to the chip is established in the database, and a vocabulary entry of the characteristic parameter is set under the directory corresponding to the chip for inputting the corresponding characteristic parameter, and for the characteristic parameter input into the chip, a tester can read a design manual of the chip and manually add the characteristic parameter, so that after the data of the chip to be tested is added, the method in steps 1 to 4 in the above embodiment can be executed to obtain the test program for testing.
In another embodiment of the invention, the information of the design manual of the whole chip is directly input based on the text recognition function, the keyword search of the characteristic parameters is carried out on the text information for the items of the characteristic parameters to be filled, all the searched keywords matched with the characteristic parameters are pushed to the information input personnel for reference, and the outgoing page number of the keywords is also pushed to the input personnel for the input personnel to determine whether the items are the required characteristic information.
In the method of the embodiment, the database is set to record the chip data, other characteristic parameters can be automatically adapted to the chip in the database according to the known characteristics of the chip, the test item and the test program template can be adapted, the adapted characteristic parameters are automatically filled in the test program template to generate a test program, and the test program can be used for testing the chip; by using the mode of the invention, the test program can carry out customized adjustment and adaptation on the performance parameters of each chip to be tested, which is beneficial to improving the accuracy of the test result;
in an embodiment of the present invention, a chip testing system is further provided, which includes a chip clamp 100, a testing circuit board 200 and a processor, where the chip clamp 100 may be used to fix a chip, and the chip clamp 100 may be mounted on the testing circuit board 200 and then connected to a testing circuit to run a testing program, as shown in fig. 2;
fig. 3 shows a test circuit board 200 according to an embodiment, wherein a plurality of chip holders 100 can be mounted on the test circuit board 200, and after the test circuit is connected, the processor is configured to perform the adaptive test method for the chip as described above.
A typical test scenario for testing a chip testing system is as follows: the resulting test program is run so that any type of signal is generated, a plurality of signals together constituting a test pattern or test vector, a test vector is applied to the chip, the output generated by the chip is fed back into the system to measure its parameters, the measurement result is compared with stored empirical values, and if the measurement result is within an acceptable range, the test is deemed to be passed.
Referring to fig. 4, in an embodiment of the present invention, each pin of a corresponding chip on a test circuit board is respectively provided with a plurality of interface circuits, each interface circuit at least includes a power supply 201, a ground 202, and an I/O interface 203, each interface circuit is respectively provided with a controllable switch 204, the controllable switch 204 is connected to a processor and a test loop, the processor reads package information in characteristic parameters of the chip to be tested obtained by matching, and controls the controllable switch of the corresponding interface circuit to be closed according to the package information of the chip to be tested, so that the interface circuit of each pin on the test circuit board corresponds to the pin of the package of the chip to be tested.
The power supply 201 is controlled by 3 grades of power output and is respectively suitable for different types of chips, and the first path of power is matched with the low-power-consumption chip. Each power supply independently controls and outputs programmable power supply outputs of 0-5V and 0-500ma, the second gear outputs any programmable power supply outputs of 5-12V and 1A, the power supply is adaptive to an MCU power management chip and a power chip, and the third gear outputs programmable power supply outputs of voltage and current in the interval of 12-21V 1A.
In this embodiment, the corresponding relationship between the interface circuit of the test circuit board and the determined pins of the package of the chip to be tested may be established by reading the package information in the characteristic parameters. The embodiment of the invention realizes the position determination of the pin of the chip package to be tested, so that a test circuit board does not need to be arranged for one type of chip, the test circuit board can be compatible with the chip test of various types, the universality is good, the development cost and time of test equipment are reduced, and the chip test cost is reduced.
The chip test system provided by the embodiment can realize the test of the chip to be tested, the connection between the test circuit board and the chip clamp is simple and easy to realize, the test of a plurality of chips can be realized at one time, and the test efficiency is improved.
In an embodiment of the present invention, there is also provided a computer apparatus including: comprising a processor, a memory, and a program;
a program is stored in the memory, and the processor calls the program stored in the memory to execute the adaptive testing method of the chip.
The computer apparatus may be a terminal, and its internal structure diagram may be as shown in fig. 5. The computer device comprises a processor, a memory, a network interface, a display screen and an input device which are connected through a bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The network interface of the computer device is used for connecting and communicating with an external terminal through a network. The computer program is executed by a processor to implement a method for adaptive testing of a chip. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covered on the display screen, a key, a track ball or a touch pad arranged on a shell of the computer device, an external keyboard, a touch pad or a mouse and the like.
The Memory may be, but is not limited to, a Random Access Memory (RAM), a Read Only Memory (ROM), a Programmable Read-Only Memory (PROM), an Erasable Read-Only Memory (EPROM), an electrically Erasable Read-Only Memory (EEPROM), and the like. The memory is used for storing programs, and the processor executes the programs after receiving the execution instructions.
The processor may be an integrated circuit chip having signal processing capabilities. The Processor may be a general-purpose Processor, and includes a Central Processing Unit (CPU), a Network Processor (NP), and the like. The Processor may also be other general purpose processors, digital Signal Processors (DSPs), application Specific Integrated Circuits (ASICs), field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The various methods, steps, and logic blocks disclosed in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
It will be appreciated by those skilled in the art that the configuration shown in fig. 5 is a block diagram of only a portion of the configuration associated with the present application, and is not intended to limit the computing device to which the present application may be applied, and that a particular computing device may include more or fewer components than shown, or may combine certain components, or have a different arrangement of components.
In an embodiment of the present invention, there is also provided a computer-readable storage medium for storing a program for executing the adaptive testing method of a chip as described above.
As will be appreciated by one of skill in the art, embodiments of the present invention may be provided as a method, computer apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, computer apparatus, or computer program products according to embodiments of the invention. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal, create means for implementing the functions specified in the flowchart and/or flowchart block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart.
The application of the method, system, computer device and computer readable storage medium for adaptive testing of chips provided by the present invention has been described in detail, and the principle and implementation of the present invention are explained herein by using specific embodiments, and the description of the embodiments is only used to help understand the method and core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
1. A self-adaptive test method of a chip is characterized by comprising the following steps:
establishing a database, wherein chip data of historical detection are stored in the database;
acquiring known characteristics of a chip to be tested, and matching the known characteristics with a database to obtain characteristic parameters of the chip to be tested;
pushing a test program corresponding to the chip according to the matching result;
and testing the chip by adopting a test program.
2. The adaptive test method for chips according to claim 1, wherein: the reading of the known characteristics of the chip to be tested and the matching of the database to obtain the characteristic parameters of the chip to be tested specifically include:
and acquiring the ID of the chip to be tested, and matching the ID with the database to obtain the characteristic parameters of the chip to be tested.
3. The adaptive test method for chips according to claim 2, characterized in that: the characteristic parameters of the chip to be tested comprise any one or more of a communication protocol, a brand, capacity, voltage, current, power-on time sequence, an encryption area, a register, packaging size, frequency and baud rate.
4. The adaptive test method for chips according to claim 3, wherein: the pushing of the test program corresponding to the chip according to the matching result comprises the following steps:
pushing a test item matched with a chip to be tested;
calling a corresponding test program template from a test program database according to the pushed test items;
and automatically filling characteristic parameters of the chip to be tested in the called test program template to form the test program.
5. The adaptive test method for chips according to claim 1, wherein: and when the information of the chip to be tested is not received and recorded in the database, establishing a catalogue corresponding to the chip in the database, and setting an entry of the characteristic parameter under the catalogue corresponding to the chip for inputting the corresponding characteristic parameter.
6. The adaptive test method for chips according to claim 5, wherein: and identifying the information of the design manual of the input chip through the text, performing keyword retrieval on the text information according to the characteristic parameters, and pushing all the retrieved keywords matched with the characteristic parameters to the information input personnel for reference.
7. The utility model provides a chip test system, includes chip anchor clamps and test circuit board and treater, can install a plurality ofly on the test circuit board the chip anchor clamps, its characterized in that: the processor is used for executing the adaptive testing method of the chip.
8. The chip test system according to claim 7, wherein: the testing circuit board is provided with a plurality of interface circuits corresponding to each pin of the chip, each interface circuit at least comprises a power supply interface, a grounding interface and an I/O interface, each interface circuit is provided with a controllable switch, the controllable switches are connected with the processor and the testing loop, the processor reads the packaging information in the characteristic parameters of the chip to be tested, which is obtained by matching, and controls the controllable switches of the corresponding interface circuits to be closed according to the packaging information of the chip to be tested, so that the interface circuit of each pin on the testing circuit board corresponds to the pin packaged by the chip to be tested.
9. A computer device, comprising: comprising a processor, a memory, and a program;
the program is stored in the memory, and the processor calls the program stored in the memory to execute the adaptive testing method of the chip according to any one of claims 1 to 6.
10. A computer-readable storage medium characterized by: the computer-readable storage medium stores a program for executing the adaptive testing method of a chip according to any one of claims 1 to 6.
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| CN202210823754.1A CN115344441A (en) | 2022-07-14 | 2022-07-14 | Method, system, device and storage medium for adaptive testing of chip |
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| CN202210823754.1A CN115344441A (en) | 2022-07-14 | 2022-07-14 | Method, system, device and storage medium for adaptive testing of chip |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115549820A (en) * | 2022-12-02 | 2022-12-30 | 深圳市锦锐科技股份有限公司 | Radio chip testing method and chip testing system |
| CN115856587A (en) * | 2023-02-21 | 2023-03-28 | 成都天成电科科技有限公司 | Chip testing method and device, storage medium and electronic equipment |
| CN115902595A (en) * | 2023-02-20 | 2023-04-04 | 之江实验室 | Chip testing system and chip testing method |
| CN116580748A (en) * | 2023-04-21 | 2023-08-11 | 深圳市晶存科技有限公司 | Configuration method, device, equipment and storage medium of memory chip test fixture |
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2022
- 2022-07-14 CN CN202210823754.1A patent/CN115344441A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115549820A (en) * | 2022-12-02 | 2022-12-30 | 深圳市锦锐科技股份有限公司 | Radio chip testing method and chip testing system |
| CN115549820B (en) * | 2022-12-02 | 2023-03-24 | 深圳市锦锐科技股份有限公司 | Radio chip testing method and chip testing system |
| CN115902595A (en) * | 2023-02-20 | 2023-04-04 | 之江实验室 | Chip testing system and chip testing method |
| CN115856587A (en) * | 2023-02-21 | 2023-03-28 | 成都天成电科科技有限公司 | Chip testing method and device, storage medium and electronic equipment |
| CN116580748A (en) * | 2023-04-21 | 2023-08-11 | 深圳市晶存科技有限公司 | Configuration method, device, equipment and storage medium of memory chip test fixture |
| CN116580748B (en) * | 2023-04-21 | 2024-02-23 | 深圳市晶存科技有限公司 | Configuration method, device, equipment and storage medium of memory chip test fixture |
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