CN115332340A - Super junction VDMOS device with dynamic characteristic adjusted and preparation method thereof - Google Patents

Super junction VDMOS device with dynamic characteristic adjusted and preparation method thereof Download PDF

Info

Publication number
CN115332340A
CN115332340A CN202210945512.XA CN202210945512A CN115332340A CN 115332340 A CN115332340 A CN 115332340A CN 202210945512 A CN202210945512 A CN 202210945512A CN 115332340 A CN115332340 A CN 115332340A
Authority
CN
China
Prior art keywords
type
conductive type
conductive
layer
conductivity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210945512.XA
Other languages
Chinese (zh)
Inventor
柴展
栗终盛
罗杰馨
徐大朋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Gongcheng Semiconductor Technology Co Ltd
Original Assignee
Shanghai Gongcheng Semiconductor Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Gongcheng Semiconductor Technology Co Ltd filed Critical Shanghai Gongcheng Semiconductor Technology Co Ltd
Priority to CN202210945512.XA priority Critical patent/CN115332340A/en
Publication of CN115332340A publication Critical patent/CN115332340A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention provides a super-junction VDMOS device for adjusting dynamic characteristics and a preparation method thereof, wherein a groove positioned at the top of a first conductive type column is formed in the super-junction VDMOS device, and a grid structure positioned on a first conductive type source region, a second conductive type body region and the first conductive type column and extending into the groove is formed by combining the groove, so that the grid structure extends a certain distance into the first conductive type column, the effective area of the grid structure can be increased by adjusting the depth and the width of the groove, the thickness of a grid dielectric layer at the bottom of the groove is changed, so that the Crss under high leakage voltage is remarkably increased, the Crss under low leakage voltage is kept unchanged, the ratio of Ciss and Crss is adjusted, meanwhile, the on-resistance can be reduced, the dynamic characteristics of the super-junction VDMOS device are adjusted, and under the condition of keeping high switching speed and low switching power consumption, the switching current oscillation is reduced, and the EMI noise is relieved.

Description

Super junction VDMOS device with dynamic characteristic adjusted and preparation method thereof
Technical Field
The invention belongs to the field of semiconductor device manufacturing, and relates to a super junction VDMOS device with dynamic characteristics adjusted and a preparation method thereof.
Background
In the Field of Semiconductor power devices, VDMOSFETs (Vertical Double Diffused Metal Oxide Semiconductor Field Effect transistors) are widely used because of their advantages such as high operating frequency, good thermal stability, and simple driving circuits. The source-drain breakdown voltage (BVdss) and the on-resistance (Rdson) are two important performance parameters of a power device, and for the two performance parameters, the common design requirement is that the power device not only has a high BVdss, but also has a low Rdson to reduce power consumption.
A Super Junction structure (Super Junction) is introduced into a drift region of a traditional VDMOS device, a doping region formed by alternately arranging a series of P-type and N-type semiconductor thin layers is adopted to replace a single lightly doped drift region in the traditional VDMOS device so as to form the Super Junction VDMOS device, and when the device is in an off state, due to the fact that depletion region electric fields in a P-type layer and an N-type layer generate a mutual compensation effect, the doping concentration of the P-type layer and the N-type layer can be made to be very high, and the breakdown voltage of the device cannot be reduced; when conducting, the high-concentration doping can enable the on-resistance to be remarkably reduced, and due to the special structure, the compromise relationship between the BVdss and the Rdson can be effectively optimized, and the wide attention in the industry is drawn due to the advantages of small on-resistance, high conducting speed, low switching loss and the like.
In a MOSFET device, the gate is insulated by a thin gate dielectric layer, so that the power MOSFET has capacitances between gate-drain, gate-source and drain-source, as shown in fig. 1, where the input capacitance (Ciss) is the sum of the gate-source parasitic capacitance (Cgs) and the gate-drain parasitic capacitance (Cgd), i.e., ciss = Cgs + Cgd; the output capacitance (Coss) is the sum of the drain-source parasitic capacitance (Cds) and the gate-drain parasitic capacitance (Cgd), i.e., coss = Cds + Cgd; the feedback capacitance (Crss), also referred to as miller capacitance, crss = Cgd. The power MOSFET is a voltage-driven device, the process that the grid driving voltage of the power MOSFET is increased from 0V to a specified voltage can be understood as the process that the internal parasitic capacitor is charged, the larger the parasitic capacitor is, the more the required charging charge Qg is, the lower the corresponding turn-on speed is, and meanwhile, the adverse effect that the turn-on loss is increased is brought; similarly, the turn-off speed and turn-off loss during turn-off are determined by the discharge process of the parasitic capacitor. In the whole switching process, the Miller capacitor Crss and the corresponding gate-drain charge (Qgd) thereof play a leading role, so that the switching speed can be effectively improved and the switching loss can be reduced by reducing Cgd.
With the development of semiconductor technology, semiconductor devices are being miniaturized and low-cost, a super-junction VDMOS device can make the device chip area smaller and lower in cost under the same Rdson by reducing the Pitch (Pitch) of the super-junction structure cells, but the parasitic capacitance is reduced and the switching speed is faster due to the reduction of the device chip area, however, since the super-junction VDMOS device uses a lateral electric field, the middle N region is completely depleted at high voltage, the stored charge is small, coss and Crss are both very small, vds (drain-source voltage) starts to fall very fast, when Vds is reduced to 50V or lower, the widths of the depletion layers of the N and P regions are reduced until being disappeared and gradually recovered to the original high doping state, which is equivalent to the sudden increase of the stored charge, so that the capacitance is suddenly increased, especially during the switching process, when the drain voltage is relatively small, the capacitance of the super-junction VDMOS device is subjected to sudden change (dV/dt), which easily causes the problems of oscillation and EMI (electromagnetic Interference) and the like of the device can also cause serious failure. Therefore, some application schemes such as charging piles and the like which have long verification period and are not easy to modify can give up the miniaturized super-junction VDMOS device with high cost performance, and select the traditional super-junction VDMOS device.
Therefore, the super junction VDMOS device with the dynamic characteristics adjusted and the preparation method thereof are necessary.
Disclosure of Invention
In view of the above disadvantages of the prior art, an object of the present invention is to provide a super junction VDMOS device with dynamic characteristics adjusted and a manufacturing method thereof, so as to solve the problem that in the prior art, the super junction VDMOS device is prone to oscillation and electromagnetic interference due to a rapid change in capacitance.
To achieve the above and other related objects, the present invention provides a super junction VDMOS device adjusting dynamic characteristics, the super junction VDMOS device including:
a first conductive type substrate;
the first conduction type epitaxial layer is positioned on the surface of the first conduction type substrate;
second conductive type columns distributed in the first conductive type epitaxial layer at intervals so as to form a super junction structure by separating the first conductive type columns among the second conductive type columns, wherein the tops of the first conductive type columns are provided with grooves;
a second conductivity type body region within the first conductivity type epitaxial layer and on the second conductivity type pillar;
a first conductive-type source region located within the second conductive-type body region;
a gate structure located on the first conductivity-type source region, the second conductivity-type body region, and the first conductivity-type pillar and extending into the trench, the gate structure including a gate dielectric layer and a gate conductive layer located on a surface of the gate dielectric layer;
the interlayer dielectric layer wraps the grid structure;
the front metal layer is positioned on the surfaces of the first conduction type source region and the second conduction type body region;
the back metal layer is positioned on the surface, far away from the first conductive type epitaxial layer, of the first conductive type substrate.
Optionally, the cross-sectional profile of the groove comprises a rectangle, a trapezoid, a triangle, or an arc.
Optionally, the semiconductor device further includes a second conductive type contact region located in the second conductive type body region and adjacent to the first conductive type source region.
Optionally, the super junction VDMOS device structure further includes a first conductivity type buffer layer, the first conductivity type buffer layer is located between the first conductivity type substrate and the first conductivity type epitaxial layer, and a doping concentration of the first conductivity type buffer layer is between that of the first conductivity type substrate and the first conductivity type epitaxial layer.
Optionally, the first conductivity type is n-type, and the second conductivity type is p-type; or the first conductivity type is p-type and the second conductivity type is n-type.
The invention also provides a preparation method of the super junction VDMOS device for adjusting dynamic characteristics, which comprises the following steps:
providing a first conductive type substrate;
forming a first conductive type epitaxial layer on the surface of the first conductive type substrate;
forming second conductive type columns distributed at intervals in the first conductive type epitaxial layer, and forming a super junction structure by spacing the first conductive type columns among the second conductive type columns;
performing ion implantation to form a second conductive type body region on the second conductive type column in the first conductive type epitaxial layer;
forming a trench in a top portion of the first conductive type pillar;
forming a gate structure, wherein the gate structure is positioned on the first conductive type column and extends into the groove, the gate structure comprises a gate dielectric layer and a gate conductive layer positioned on the surface of the gate dielectric layer, and the gate structure extends to the upper surface of the second conductive type body region;
forming an interlayer dielectric layer, wherein the interlayer dielectric layer wraps the grid structure;
performing ion implantation, and forming a first conductive type source region in the second conductive type body region, wherein the first conductive type source region extends to the lower surface of the gate structure;
and forming a front metal layer and a back metal layer, wherein the front metal layer is positioned on the surfaces of the first conductive type source region and the second conductive type body region, and the back metal layer is positioned on the surface of the first conductive type substrate far away from the first conductive type epitaxial layer.
Optionally, the method further includes a step of forming a first conductivity type buffer layer between the first conductivity type substrate and the first conductivity type epitaxial layer, and a doping concentration of the first conductivity type buffer layer is between that of the first conductivity type substrate and that of the first conductivity type epitaxial layer.
Optionally, the cross-sectional profile of the groove formed includes a rectangle, a trapezoid, a triangle, or an arc.
Optionally, a step of forming a second conductive-type contact region disposed adjacent to the first conductive-type source region in the second conductive-type body region is further included.
Optionally, the first conductivity type is n-type, and the second conductivity type is p-type; or the first conductivity type is p-type and the second conductivity type is n-type.
As described above, according to the super-junction VDMOS device for adjusting dynamic characteristics and the manufacturing method thereof of the present invention, the trench located at the top of the first conductive type column is formed in the super-junction VDMOS device, and the gate structure located on the first conductive type source region, the second conductive type body region, and the first conductive type column and extending into the trench is formed in combination with the trench, so that the gate structure extends a certain distance into the first conductive type column, the effective area of the gate structure can be increased by adjusting the depth and the width of the trench, and the thickness of the gate dielectric layer at the bottom of the trench is changed, so that the Crss under high leakage voltage is significantly increased, and the Crss under low leakage voltage is maintained unchanged, so as to adjust the ratio of cis and the Crss, and simultaneously reduce the on-resistance, thereby adjusting the dynamic characteristics of the super-junction VDMOS device, and reducing the switching current oscillation and alleviating EMI noise while maintaining the high switching speed and the low switching power consumption.
Drawings
Fig. 1 shows a schematic diagram of the capacitance of a MOSFET device in the prior art.
Fig. 2 is a flowchart of a manufacturing process of the super junction VDMOS device with dynamic characteristics adjusted according to the embodiment of the present invention.
Fig. 3 to 8 show schematic structural diagrams presented in steps of a method for manufacturing a super junction VDMOS device in an embodiment of the present invention.
Fig. 9 shows a Crss simulation comparison diagram of the super junction VDMOS device in the embodiment of the present invention and the existing super junction VDMOS device.
Fig. 10 is a diagram showing a Rdson simulation comparison of a super junction VDMOS device in an embodiment of the present invention and an existing super junction VDMOS device.
Description of the element reference numerals
110. First conductive type substrate
120. Epitaxial layer of first conductivity type
130. Second conductivity type pillar
140. First conductivity type pillar
141. Groove
150. Body region of the second conductivity type
160. Grid structure
161. Gate dielectric layer
162. Gate conductive layer
170. Interlayer dielectric layer
180. Source region of the first conductivity type
190. Contact region of the second conductivity type
210. Front metal layer
220. Back metal layer
S1 to S9
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. Where an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
Expressions such as "between … …" may be used herein to include both endpoints, and expressions such as "plurality" may be used herein to represent two or more unless specifically limited otherwise. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.
It should be noted that the drawings provided in the present embodiment are only for schematically illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 8, the present embodiment provides a super junction VDMOS device including:
a first conductive type substrate 110;
a first conductive type epitaxial layer 120, the first conductive type epitaxial layer 120 being located on a surface of the first conductive type substrate 110;
second conductive type pillars 130, the second conductive type pillars 130 are distributed in the first conductive type epitaxial layer 120 at intervals, so as to partition first conductive type pillars 140 between the second conductive type pillars 130, and the first conductive type pillars 140 and the second conductive type pillars 130 are alternately arranged to form a super junction structure, and a trench 141 is formed at the top of the first conductive type pillars 140;
a second conductive-type body region 150, the second conductive-type body region 150 being located within the first conductive-type epitaxial layer 120 and on the second conductive-type pillars 130;
a first conductive-type source region 180, the first conductive-type source region 180 being located within the second conductive-type body region 150;
a gate structure 160, the gate structure 160 being located on the first conductive type source region 180, the second conductive type body region 150 and the first conductive type pillar 140 and extending into the trench 141, the gate structure 160 comprising a gate dielectric layer 161 and a gate conductive layer 162 located on a surface of the gate dielectric layer 161;
an interlayer dielectric layer 170, wherein the gate structure 160 is coated by the interlayer dielectric layer 170;
a front metal layer 210, the front metal layer 210 being located on the surfaces of the first conductive type source region 180 and the second conductive type body region 150;
a back metal layer 220, wherein the back metal layer 220 is located on a surface of the first conductive type substrate 110 away from the first conductive type epitaxial layer 120.
In the present embodiment, the trench 141 located at the top of the first conductive type column 140 is formed in the super junction VDMOS device, and in combination with the trench 141, the gate structure 160 located on the first conductive type source region 180, the second conductive type body region 150 and the first conductive type column 140 and extending into the trench 141 is formed, so that the gate structure 160 extends into the first conductive type column 140 for a certain distance, so as to increase the effective area of the gate structure 160 by adjusting the depth, the width profile and the like of the trench 141 on the premise of reducing the device size, and by changing the thickness of the gate dielectric layer 161 at the bottom of the trench 141, the Crss under high drain voltage can be significantly increased, and the Crss under low drain voltage can be maintained unchanged, so as to adjust the ratio of Ciss and Crss, and at the same time, the on-resistance can be reduced, thereby adjusting the dynamic characteristics of the super junction VDMOS device, and reducing switching current oscillation and alleviating EMI noise while maintaining high switching speed and low switching power consumption.
It should be noted that in the present embodiment, the first conductive type epitaxial layer 120 is divided into a plurality of first conductive type pillars 140 by a plurality of second conductive type pillars 130, and the first conductive type pillars 140 and the second conductive type pillars 130 are alternately arranged to form a super junction structure, so that the first conductive type pillars 140 are substantially a portion of the first conductive type epitaxial layer 120.
As an example, the first conductivity type is n-type and the second conductivity type is p-type, or the first conductivity type is p-type and the second conductivity type is n-type.
Specifically, n-type conductivity (mostly electrons) can be formed by doping a group-five element such as nitrogen, phosphorus, arsenic, or the like in a semiconductor substrate such as germanium, silicon, or the like, and p-type conductivity (mostly holes) can be formed when a group-three element such as boron, aluminum, or the like is doped. In this embodiment, the first conductive type is preferably an n-type, and the corresponding second conductive type is a p-type, but the present invention is not limited thereto, and the first conductive type may also be a p-type and the corresponding second conductive type is an n-type as required.
As an example, the cross-sectional profile of the groove 141 may include a rectangular shape, a trapezoidal shape, a triangular shape, or a circular arc shape.
Specifically, referring to fig. 4, the groove 141 having a rectangular cross-sectional shape is illustrated in the present embodiment, but the shape of the groove 141 is not limited thereto, and may also include a trapezoid, a triangle, or an arc, and the like, which is not limited herein.
The effective area of the gate structure 160 can be changed by adjusting the depth and width of the trench 141, and the proportion of Ciss and Crss of the super junction VDMOS device can be adjusted, so as to adjust the dynamic characteristics of the super junction VDMOS device, and the specific structural parameters of the trench 141 are not limited herein. Referring to fig. 9, when the depth of the trench 141 is increased, the Crss of the super junction VDMOS device can be significantly increased.
As an example, a second conductive-type contact region 190 is further included in the second conductive-type body region 150 and disposed adjacent to the first conductive-type source region 180.
Specifically, in the present embodiment, the second conductive type contact region 190 has the second conductive type, and the doping concentration of the second conductive type contact region 190 is greater than the doping concentration of the second conductive type body region 150, so that the contact characteristics can be improved by contacting the second conductive type contact region 190 with the front metal electrode 210.
As an example, the super-junction VDMOS device may further include a first conductivity-type buffer layer (not shown), where the first conductivity-type buffer layer is located between the first conductivity-type substrate 110 and the first conductivity-type epitaxial layer 120, and a doping concentration of the first conductivity-type buffer layer is between doping concentrations of the first conductivity-type substrate 110 and the first conductivity-type epitaxial layer 120, so that impurity atoms of the first conductivity-type substrate 110 may be prevented from diffusing into the first conductivity-type epitaxial layer 120 during a high temperature process, and a breakdown voltage of the device may be prevented from being reduced due to an increase in the doping concentration of the first conductivity-type epitaxial layer 120.
As an example, the gate conductive layer 162 is preferably a polysilicon layer, and the work function thereof can be changed by doping to lower the threshold voltage of the device; the gate dielectric layer 161 is preferably silicon dioxide; the kinds of the gate conductive layer 162 and the gate dielectric layer 161 are not limited thereto.
The interlayer dielectric layer 170 may be, but not limited to, a silicon nitride layer, the front metal layer 210 and the back metal layer 220 may include an aluminum metal layer, a copper metal layer, and the like, and the selection of the material of each structural layer of the super junction VDMOS device may be adaptively changed according to the need, which is not limited herein.
As shown in fig. 2, the present invention further provides a method for manufacturing a super junction VDMOS device with dynamic characteristics adjusted, which may be used for manufacturing the super junction VDMOS device, but the method for manufacturing the super junction VDMOS device is not limited thereto, and in this embodiment, the super junction VDMOS device is manufactured by the following manufacturing method, and thus the description of the super junction VDMOS device is not repeated herein.
Specifically, the preparation method can comprise the following steps:
referring to fig. 3, step S1 is performed to provide a first conductive type substrate 110.
Specifically, in the present embodiment, the first conductive type is n-type, and the second conductive type is p-type, but not limited thereto, in another embodiment, the first conductive type may also be p-type, and the corresponding second conductive type is n-type. The material, thickness and doping concentration of the first conductive type substrate 110 may be selected according to the requirement, and are not limited herein.
Next, step S2 is performed to form a first conductive type epitaxial layer 120 on the surface of the first conductive type substrate 110. The specific material, thickness and doping concentration of the first conductive type epitaxial layer 120 can be selected according to the requirement, and are not limited herein.
Further, a step of forming a first conductive type buffer layer (not shown) between the first conductive type substrate 110 and the first conductive type epitaxial layer 120 may be further included, and a doping concentration of the first conductive type buffer layer is between doping concentrations of the first conductive type substrate 110 and the first conductive type epitaxial layer 120, so that impurity atoms of the first conductive type substrate 110 may be prevented from diffusing into the first conductive type epitaxial layer 120 during a high temperature process, and a breakdown voltage of the device may be prevented from being reduced due to an increase in the doping concentration of the first conductive type epitaxial layer 120.
Next, step S3 is performed to form second conductive type pillars 130 spaced apart from each other in the first conductive type epitaxial layer 120, and form a super junction structure by spacing first conductive type pillars 140 between the second conductive type pillars 130.
Specifically, the process steps for forming the first conductivity type epitaxial layer 120 and the second conductivity type pillar 130 can refer to the conventional process for manufacturing a super junction VDMOS device, which is not limited herein.
Next, referring to fig. 4, step S4 is performed to perform ion implantation, and a second conductive type body region 150 located on the second conductive type pillar 130 is formed in the first conductive type epitaxial layer 120.
Next, referring to fig. 5, step S5 is performed to form a trench 141 on the top of the first conductive type pillar 140.
Specifically, the trench 141 having a certain distance from the side of the second conductive type pillar 130 may be formed on the top of the first conductive type pillar 140 by coating, exposing, and developing, so as to provide an extension space for the subsequent preparation of the gate structure 160 through the trench 141. The shape of the trench 141 may be selected as needed, for example, the shape may include a rectangle, a trapezoid, a triangle, or an arc, and the like, and by adjusting the depth and the width of the trench 141, the effective area of the gate structure 160 may be changed, and the ratio of Ciss to Crss of the super-junction VDMOS device may be adjusted, so as to adjust the dynamic characteristics of the super-junction VDMOS device, as can be seen from fig. 9, when the depth of the trench 141 is increased, the Crss of the super-junction VDMOS device may be significantly increased.
Next, referring to fig. 6, step S6 is performed to form a gate structure 160, where the gate structure 160 is located on the first conductivity type pillar 140 and extends into the trench 141, the gate structure 160 includes a gate dielectric layer 161 and a gate conductive layer 162 located on a surface of the gate dielectric layer 161, and the gate structure 160 extends to an upper surface of the second conductivity type body 150.
Next, step S7 is performed to form an interlayer dielectric layer 170, and the gate structure 160 is covered by the interlayer dielectric layer 170. The material of the interlayer dielectric layer 170 may be, for example, a silicon nitride layer, and the specific material is not limited herein.
Next, referring to fig. 7, step S8 is performed to form a first conductive type source region 180 in the second conductive type body region 150, wherein the first conductive type source region 180 extends to the lower surface of the gate structure 160.
Further, a step of forming a second conductive type contact region 190 adjacent to the first conductive type source region 180 in the second conductive type body region 150 may be further included, and a doping concentration of the second conductive type contact region 190 is greater than a doping concentration of the second conductive type body region 150, so that the second conductive type contact region 190 may improve contact characteristics when contacting with the front metal electrode 210.
Next, referring to fig. 8, step S9 is performed to form a front metal layer 210 and a back metal layer 220, where the front metal layer 210 is located on the surfaces of the first conductive type source region 180 and the second conductive type body region 150, in this embodiment, the front metal layer 210 is located on the surfaces of the first conductive type source region 180 and the second conductive type contact region 190, and the back metal layer 220 is located on the surface of the first conductive type substrate 110 away from the first conductive type epitaxial layer 120.
Fig. 9 illustrates a Crss simulation comparison diagram of the super-junction VDMOS device in this embodiment and the super-junction VDMOS device in this embodiment, where a curve represents the super-junction VDMOS device in this embodiment, B curve represents the super-junction VDMOS device in this embodiment having the first trench depth, C curve represents the super-junction VDMOS device in this embodiment having the second trench depth, and the second trench depth is greater than the first trench depth, and fig. 10 illustrates that the curves a and a ' correspond to Vg =4.5v, and the curves B and B ' correspond to Vg =10V under different Vg, and the curves a ' and B ' correspond to the Rdson simulation comparison diagram of the curves a and B ' corresponding to the super-junction VDMOS device in fig. 9. As can be seen from fig. 9 and 10, when the trench depth is increased, the Crss and Rdson on-resistance decreases significantly, and the BVdss remains substantially unchanged, and similarly, a corresponding effect is achieved when the trench width is increased, and a corresponding effect is achieved when the gate dielectric layer thickness in the trench is decreased according to the capacitive principle.
In summary, according to the super-junction VDMOS device for adjusting dynamic characteristics and the manufacturing method thereof of the present invention, the trench located at the top of the first conductive type column is formed in the super-junction VDMOS device, and the gate structure located on the first conductive type source region, the second conductive type body region, and the first conductive type column and extending into the trench is formed in combination with the trench, so that the gate structure extends a certain distance into the first conductive type column, the effective area of the gate structure can be increased by adjusting the depth and the width of the trench, and the thickness of the gate dielectric layer at the bottom of the trench is changed, so that the Crss under high leakage voltage is significantly increased, and the Crss under low leakage voltage is maintained unchanged, so as to adjust the ratio of cis and the Crss, and simultaneously reduce the on-resistance, thereby adjusting the dynamic characteristics of the super-junction VDMOS device, and reducing the switching current oscillation and alleviating EMI noise under the condition of maintaining high switching speed and low switching power consumption.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (10)

1. A super-junction VDMOS device for adjusting dynamic characteristics, comprising:
a first conductive type substrate;
the first conduction type epitaxial layer is positioned on the surface of the first conduction type substrate;
second conductive type columns distributed in the first conductive type epitaxial layer at intervals so as to form a super junction structure by separating the first conductive type columns among the second conductive type columns, wherein the tops of the first conductive type columns are provided with grooves;
a second conductivity type body region within the first conductivity type epitaxial layer and on the second conductivity type pillar;
a first conductive-type source region located within the second conductive-type body region;
a gate structure located on the first conductivity-type source region, the second conductivity-type body region, and the first conductivity-type pillar and extending into the trench, the gate structure including a gate dielectric layer and a gate conductive layer located on a surface of the gate dielectric layer;
the interlayer dielectric layer wraps the grid structure;
the front metal layer is positioned on the surfaces of the first conduction type source region and the second conduction type body region;
the back metal layer is positioned on the surface, far away from the first conductive type epitaxial layer, of the first conductive type substrate.
2. The super-junction VDMOS device of claim 1, wherein: the cross section of the groove is rectangular, trapezoidal, triangular or circular arc.
3. The superjunction VDMOS device of claim 1, wherein: the semiconductor device further comprises a second conductive type contact region which is positioned in the second conductive type body region and is adjacent to the first conductive type source region.
4. The superjunction VDMOS device of claim 1, wherein: the super-junction VDMOS device structure further comprises a first conduction type buffer layer, wherein the first conduction type buffer layer is located between the first conduction type substrate and the first conduction type epitaxial layer, and the doping concentration of the first conduction type buffer layer is between the doping concentrations of the first conduction type substrate and the first conduction type epitaxial layer.
5. The superjunction VDMOS device of claim 1, wherein: the first conductivity type is n-type, and the second conductivity type is p-type; or the first conductivity type is p-type and the second conductivity type is n-type.
6. A preparation method of a super junction VDMOS device for adjusting dynamic characteristics is characterized by comprising the following steps:
providing a first conductive type substrate;
forming a first conductive type epitaxial layer on the surface of the first conductive type substrate;
forming second conductive type columns distributed at intervals in the first conductive type epitaxial layer, and forming a super junction structure by spacing the first conductive type columns among the second conductive type columns;
performing ion implantation to form a second conductive type body region on the second conductive type column in the first conductive type epitaxial layer;
forming a trench in a top portion of the first conductive type pillar;
forming a gate structure, wherein the gate structure is positioned on the first conductive type column and extends into the groove, the gate structure comprises a gate dielectric layer and a gate conductive layer positioned on the surface of the gate dielectric layer, and the gate structure extends to the upper surface of the second conductive type body region;
forming an interlayer dielectric layer, wherein the interlayer dielectric layer wraps the grid structure;
performing ion implantation, and forming a first conductive type source region in the second conductive type body region, wherein the first conductive type source region extends to the lower surface of the gate structure;
and forming a front metal layer and a back metal layer, wherein the front metal layer is positioned on the surfaces of the first conductive type source region and the second conductive type body region, and the back metal layer is positioned on the surface of the first conductive type substrate far away from the first conductive type epitaxial layer.
7. The method for manufacturing the super junction VDMOS device according to claim 6, wherein: the method further comprises the step of forming a first conduction type buffer layer between the first conduction type substrate and the first conduction type epitaxial layer, wherein the doping concentration of the first conduction type buffer layer is between that of the first conduction type substrate and that of the first conduction type epitaxial layer.
8. The method for manufacturing the super junction VDMOS device according to claim 6, wherein: the cross section of the formed groove is rectangular, trapezoidal, triangular or circular arc.
9. The method for manufacturing the super junction VDMOS device according to claim 6, wherein: further comprising the step of forming a second conductivity type contact region in the second conductivity type body region disposed adjacent to the first conductivity type source region.
10. The method for manufacturing the super junction VDMOS device according to claim 6, wherein: the first conductivity type is n-type, and the second conductivity type is p-type; or the first conductivity type is p-type and the second conductivity type is n-type.
CN202210945512.XA 2022-08-08 2022-08-08 Super junction VDMOS device with dynamic characteristic adjusted and preparation method thereof Pending CN115332340A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210945512.XA CN115332340A (en) 2022-08-08 2022-08-08 Super junction VDMOS device with dynamic characteristic adjusted and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210945512.XA CN115332340A (en) 2022-08-08 2022-08-08 Super junction VDMOS device with dynamic characteristic adjusted and preparation method thereof

Publications (1)

Publication Number Publication Date
CN115332340A true CN115332340A (en) 2022-11-11

Family

ID=83921201

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210945512.XA Pending CN115332340A (en) 2022-08-08 2022-08-08 Super junction VDMOS device with dynamic characteristic adjusted and preparation method thereof

Country Status (1)

Country Link
CN (1) CN115332340A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116613190A (en) * 2023-06-02 2023-08-18 上海功成半导体科技有限公司 Super junction device and electronic device

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1763974A (en) * 2004-10-18 2006-04-26 株式会社东芝 Semiconductor device and method of manufacturing the same
US20110169103A1 (en) * 2010-01-12 2011-07-14 Maxpower Semiconductor Inc. Devices, components and methods combining trench field plates with immobile electrostatic charge
CN107591453A (en) * 2017-10-24 2018-01-16 贵州芯长征科技有限公司 Groove grid super node MOSFET device and preparation method thereof
US20190288073A1 (en) * 2018-03-14 2019-09-19 Fuji Electric Co., Ltd. Silicon carbide semiconductor device and silicon carbide semiconductor circuit device
CN113451389A (en) * 2020-03-24 2021-09-28 株式会社东芝 Semiconductor device and method for manufacturing the same
CN113611748A (en) * 2021-08-04 2021-11-05 济南市半导体元件实验所 High-voltage planar gate MOS device with groove structure and processing technology thereof
CN113808946A (en) * 2020-06-12 2021-12-17 芯恩（青岛）集成电路有限公司 Super junction power device and preparation method thereof
CN113838937A (en) * 2021-09-01 2021-12-24 无锡芯朋微电子股份有限公司 Deep-groove super-junction MOSFET power device and preparation method thereof
CN114464670A (en) * 2022-04-11 2022-05-10 江苏长晶科技股份有限公司 Super-junction MOSFET with ultralow specific conductance and preparation method thereof
CN114497219A (en) * 2020-11-13 2022-05-13 现代自动车株式会社 Semiconductor device with a plurality of semiconductor chips

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1763974A (en) * 2004-10-18 2006-04-26 株式会社东芝 Semiconductor device and method of manufacturing the same
US20110169103A1 (en) * 2010-01-12 2011-07-14 Maxpower Semiconductor Inc. Devices, components and methods combining trench field plates with immobile electrostatic charge
CN107591453A (en) * 2017-10-24 2018-01-16 贵州芯长征科技有限公司 Groove grid super node MOSFET device and preparation method thereof
US20190288073A1 (en) * 2018-03-14 2019-09-19 Fuji Electric Co., Ltd. Silicon carbide semiconductor device and silicon carbide semiconductor circuit device
CN113451389A (en) * 2020-03-24 2021-09-28 株式会社东芝 Semiconductor device and method for manufacturing the same
CN113808946A (en) * 2020-06-12 2021-12-17 芯恩（青岛）集成电路有限公司 Super junction power device and preparation method thereof
CN114497219A (en) * 2020-11-13 2022-05-13 现代自动车株式会社 Semiconductor device with a plurality of semiconductor chips
CN113611748A (en) * 2021-08-04 2021-11-05 济南市半导体元件实验所 High-voltage planar gate MOS device with groove structure and processing technology thereof
CN113838937A (en) * 2021-09-01 2021-12-24 无锡芯朋微电子股份有限公司 Deep-groove super-junction MOSFET power device and preparation method thereof
CN114464670A (en) * 2022-04-11 2022-05-10 江苏长晶科技股份有限公司 Super-junction MOSFET with ultralow specific conductance and preparation method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116613190A (en) * 2023-06-02 2023-08-18 上海功成半导体科技有限公司 Super junction device and electronic device
CN116613190B (en) * 2023-06-02 2024-05-31 上海功成半导体科技有限公司 Super junction device and electronic device

Similar Documents

Publication Publication Date Title
US8890280B2 (en) Trench-type semiconductor power devices
US6849880B1 (en) Power semiconductor device
US7928505B2 (en) Semiconductor device with vertical trench and lightly doped region
US7535057B2 (en) DMOS transistor with a poly-filled deep trench for improved performance
KR100929714B1 (en) Mos-gated transistor with reduced miller capacitance
US7023050B2 (en) Super junction / resurf LDMOST (SJR-LDMOST)
US7514743B2 (en) DMOS transistor with floating poly-filled trench for improved performance through 3-D field shaping
US11888022B2 (en) SOI lateral homogenization field high voltage power semiconductor device, manufacturing method and application thereof
US8421147B2 (en) MOS transistor with elevated gate drain capacity
CN107093622B (en) Longitudinal super-junction double-diffusion metal oxide semiconductor field effect transistor with semi-insulating polycrystalline silicon layer
CN112164722A (en) Shielded gate MOSFET device with uniformly doped channel and processing technology
CN107564965B (en) Transverse double-diffusion MOS device
CN106887451B (en) Super junction device and manufacturing method thereof
CN107546274B (en) LDMOS device with step-shaped groove
CN115332338B (en) Super-junction VDMOS device for adjusting dynamic characteristics and preparation method thereof
CN115332340A (en) Super junction VDMOS device with dynamic characteristic adjusted and preparation method thereof
CN116031303B (en) Super junction device, manufacturing method thereof and electronic device
US11316021B2 (en) High density power device with selectively shielded recessed field plate
Wang et al. Reducing the specific on-resistance for a trench-gate-integrated SOI LDMOS by using the double silicon drift layers
CN112993021B (en) Lateral double-diffusion metal oxide semiconductor field effect transistor
CN216213475U (en) Shielding gate groove type power MOSFET device
CN115763521A (en) Super junction device terminal structure and preparation method thereof
CN110504321B (en) Silicon-on-insulator LDMOS transistor with PN column
CN115332339A (en) Super junction VDMOS device with dynamic characteristic adjusted and preparation method thereof
CN112635559A (en) Plane gate super junction MOSFET

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20221111

WD01 Invention patent application deemed withdrawn after publication