CN115332321A - Semiconductor structure and forming method thereof - Google Patents

Abstract

The disclosed embodiments provide a semiconductor structure and a method of forming the same, the semiconductor structure comprising: a substrate; the semiconductor column comprises a first doping area, a channel area and a second doping area which are sequentially distributed along a first direction, the semiconductor column is provided with a hollow area, and at least the channel area surrounds the hollow area; a bit line extending in a second direction, the bit line contacting the first doped regions of the plurality of semiconductor pillars arranged in the second direction; a word line extending in a third direction, the word line surrounding the channel regions of the plurality of semiconductor pillars arranged in the third direction. Embodiments of the present disclosure are advantageous at least in improving the electrical performance of semiconductor structures.

Description

Semiconductor structure and forming method thereof

Technical Field

The disclosed embodiments relate to the field of semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same.

Background

As the integration density of dynamic memories is moving toward higher density, higher requirements are placed on the layout of transistors and the size of transistors in the dynamic memory array structure. When the full-surrounding gate transistor structure is used as a transistor in a dynamic memory, a smaller pattern size can be obtained under a given process condition, and the integration density of the dynamic memory is favorably increased.

While the layout of the dynamic memory structure and how to reduce the size of the dynamic memory structure are studied, it is also necessary to improve the electrical performance of the small-sized dynamic memory. Specifically, in the process of turning on the word line driving transistor of the dynamic memory, the driving capability of the word line to the partial channel region far away from the word line is poor, and further, the performance of the semiconductor structure is affected.

Disclosure of Invention

The semiconductor structure and the forming method thereof provided by the embodiment of the disclosure are at least beneficial to improving the electrical performance of the semiconductor structure.

An aspect of an embodiment of the present disclosure provides a semiconductor structure, including: a substrate; the semiconductor device comprises a substrate, a plurality of semiconductor columns and a plurality of control circuits, wherein the semiconductor columns are arranged on the substrate at intervals and comprise first doping regions, channel regions and second doping regions which are sequentially distributed along a first direction; a bit line extending along the second direction, the bit line being in contact with the first doped regions of the plurality of semiconductor pillars arranged along the second direction; and a word line extending along the third direction, the word line surrounding channel regions of the plurality of semiconductor pillars arranged along the third direction.

In some implementations, in a cross section perpendicular to the first direction, a cross-sectional area of the hollow region is a first area, a sum of cross-sectional areas of the hollow region and the channel region is a second area, and a ratio of the first area to the second area is 1:3 to 5:6.

in some implementations, the hollow region penetrates through the semiconductor pillar in a direction pointing along the first doped region toward the second doped region, and both the first doped region and the second doped region surround the hollow region.

In some implementations, further comprising: the insulating layer is filled in the hollow area; or the insulating layer is positioned in part of the hollow area, and an air gap is formed by the insulating layer and the semiconductor column in a surrounding mode.

In some implementations, further comprising: the insulating layer is positioned in part of the hollow area, the insulating layer is at least positioned on the inner wall of the second doping area facing the hollow area, and the hollow area outside the insulating layer is an air gap.

In some implementations, the insulating layer is also located on an inner wall of the first doped region facing the hollow region and on an inner wall of the channel region facing the hollow region.

In some implementations, the insulating layer also blocks an end region of the hollow region adjacent to the second doped region; and/or the insulating layer also blocks an end region of the hollow region adjacent to the first doped region.

In some implementations, further comprising: the insulating layer at least blocks the end part area of the hollow area adjacent to the second doping area, the insulating layer is positioned in part of the hollow area, and the hollow area outside the insulating layer is an air gap.

In some implementations, the device further includes a capacitor electrically connected to the second doped region, and the capacitor is located on a surface of the insulating layer away from the first doped region.

In some implementations, the first direction is a direction perpendicular to the surface of the substrate.

In some implementations, further comprising: and the semiconductor layer is positioned on the surface of the substrate and extends along the second direction, and the semiconductor layer is connected with the outer wall, adjacent to the surface of the substrate, of the semiconductor columns distributed along the second direction.

In some implementations, the semiconductor pillar is a unitary structure with the semiconductor layer.

In some implementations, the bit line is also located at a surface of the semiconductor layer, and the bit line surrounds a portion of the first doped region of the semiconductor pillar.

Correspondingly, another aspect of the embodiments of the present disclosure further provides a method for forming a semiconductor structure, including providing a substrate; forming a plurality of semiconductor columns which are arranged at intervals and are positioned on a substrate, wherein each semiconductor column comprises a first doping area, a channel area and a second doping area which are sequentially distributed along a first direction, each semiconductor column is provided with a hollow area, and at least the channel area surrounds the hollow area; forming a bit line extending along the second direction, wherein the bit line is contacted with the first doping regions of the plurality of semiconductor columns arranged along the second direction; and forming a word line extending along the third direction, wherein the word line surrounds the channel regions of the plurality of semiconductor columns arranged along the third direction.

In some embodiments, the first direction is a direction perpendicular to the substrate surface, the hollow region penetrates through the semiconductor pillar in a direction along the first doped region toward the second doped region, and the first doped region and the second doped region both surround the hollow region, and the forming the semiconductor pillar includes: forming a plurality of sacrificial structures which are arranged at intervals and extend along a first direction on a substrate; forming a semiconductor film on the surface of the sacrificial structure; removing the semiconductor film on the top surface of the sacrificial structure far away from the substrate, wherein the semiconductor film on the side surface of the sacrificial structure is used as a semiconductor column; and removing the sacrificial structure to form a hollow area.

In some implementations, forming the bit line includes: before removing the sacrificial structure, forming a bit line layer positioned between the side walls of partial first doping regions of the semiconductor columns; and removing part of the bit line layer to form a plurality of mutually independent bit lines extending along the second direction.

In some implementations, forming a semiconductor film on a surface of the sacrificial structure further includes: forming a semiconductor film on the substrate except the sacrificial structure, wherein the semiconductor film on the substrate except the sacrificial structure is used as an initial semiconductor layer; the bit line layer is also located on the initial semiconductor layer, and removing a portion of the bit line layer further includes: and removing part of the initial semiconductor layer at the bottom of the bit line layer to form a semiconductor layer extending along the second direction, wherein the semiconductor layer is connected with the outer wall of the semiconductor column arranged along the second direction, which is adjacent to the surface of the substrate.

In some implementations, further comprising: and forming an insulating layer in the hollow area, wherein the insulating layer at least blocks the top area of the hollow area far away from the substrate, the insulating layer is positioned in part of the hollow area, and the hollow area outside the insulating layer is an air gap.

In some implementations, further comprising: and forming a capacitor, wherein the capacitor is electrically connected with the second doped region and is positioned on the top surface of the insulating layer far away from the substrate.

The technical scheme provided by the embodiment of the disclosure has at least the following advantages:

in the above technical solution, the semiconductor pillar on the substrate is used for forming a semiconductor channel of a transistor, the semiconductor pillar includes a first doped region, a channel region and a second doped region which are sequentially distributed along a direction away from the substrate surface, wherein the channel region of the semiconductor pillar is used for forming a conductive channel in the semiconductor channel of the transistor, the word line extending along a third direction surrounds the channel region of the semiconductor pillar, the channel region for driving the transistor forms a conductive channel, the semiconductor pillar has a hollow region, and at least the channel region of the semiconductor pillar is arranged around the hollow region, so that the distance from the channel region to the word line is controlled in a small range, thereby preventing a part of the channel region far away from the word line from being controlled by the word line, facilitating formation of a depletion layer in a process of controlling the channel region by the word line to be conductive, facilitating increase of a switching current ratio of the transistor, and further facilitating improvement of electrical performance of the semiconductor structure.

Drawings

One or more embodiments are illustrated by corresponding figures in the drawings, which are not to be construed as limiting the embodiments, unless expressly stated otherwise, the drawings are not to scale; in order to more clearly illustrate the embodiments of the present disclosure or technical solutions in the conventional art, the drawings required to be used in the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without inventive efforts.

Fig. 1 is a cross-sectional view of a semiconductor structure provided in an embodiment of the present disclosure in a first direction;

fig. 2 is a cross-sectional view of another semiconductor structure provided in an embodiment of the present disclosure in a first direction;

fig. 3 is a cross-sectional view of another semiconductor structure provided in an embodiment of the present disclosure in a first direction;

fig. 4 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present disclosure;

fig. 5 is a cross-sectional view of another semiconductor structure provided in an embodiment of the present disclosure in a first direction;

fig. 6 is a cross-sectional view of another semiconductor structure provided in an embodiment of the present disclosure in a first direction;

fig. 7 is a cross-sectional view of another semiconductor structure provided in an embodiment of the present disclosure in a first direction;

fig. 8 is a cross-sectional view of another semiconductor structure provided in an embodiment of the present disclosure in a first direction;

fig. 9 is a cross-sectional view of another semiconductor structure provided in an embodiment of the present disclosure in a first direction;

fig. 10 is a cross-sectional view of another semiconductor structure provided in an embodiment of the present disclosure in a first direction;

fig. 11 is a cross-sectional view of another semiconductor structure provided in an embodiment of the present disclosure in a first direction;

fig. 12 is a cross-sectional view of another semiconductor structure provided in an embodiment of the present disclosure in a first direction;

fig. 13 to fig. 18 are schematic views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present disclosure.

Detailed Description

As known from the background art, in the process of turning on the word line driving transistor of the dynamic memory, the driving capability of the word line to the portion of the channel region far away from the word line is poor, thereby affecting the performance of the semiconductor structure.

Through analysis, the problem that a part of a channel region is far away from a word line can be avoided by reducing the size of a semiconductor column for forming a semiconductor channel, but the process difficulty is increased and the electrical performance of a transistor can be changed due to the fact that the semiconductor column with the smaller size is formed.

To solve the above problem, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, the semiconductor structure including: the semiconductor structure comprises a substrate, a first doping area, a channel area and a second doping area which are sequentially distributed along the direction far away from the surface of the substrate, wherein the channel area of a semiconductor column is used for forming a conductive channel in a semiconductor channel of a transistor; on the other hand, the semiconductor column with the hollow area is arranged, so that the problem of poor capability of a word line driving channel area can be solved by reducing the size of the semiconductor column, and the manufacturing difficulty of the semiconductor structure is favorably reduced.

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in the embodiments of the disclosure, numerous technical details are set forth in order to provide a better understanding of the embodiments of the disclosure. However, the claimed embodiments of the present disclosure may be practiced without these specific details or with various changes and modifications based on the following embodiments.

Fig. 1 is a cross-sectional view of a semiconductor structure provided in an embodiment of the present disclosure in a first direction; fig. 2 is a cross-sectional view of another semiconductor structure provided in an embodiment of the present disclosure in a first direction; fig. 3 is a cross-sectional view of another semiconductor structure provided in an embodiment of the present disclosure in a first direction; fig. 4 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present disclosure; fig. 5 is a cross-sectional view of another semiconductor structure provided in an embodiment of the present disclosure in a first direction; fig. 6 is a cross-sectional view of another semiconductor structure provided in an embodiment of the present disclosure in a first direction; fig. 7 is a cross-sectional view of another semiconductor structure provided in an embodiment of the present disclosure in a first direction; fig. 8 is a cross-sectional view of another semiconductor structure provided in an embodiment of the present disclosure in a first direction; fig. 9 is a cross-sectional view of another semiconductor structure provided in an embodiment of the present disclosure in a first direction; fig. 10 is a cross-sectional view of another semiconductor structure provided in an embodiment of the present disclosure in a first direction; fig. 11 is a cross-sectional view of another semiconductor structure provided in an embodiment of the present disclosure in a first direction; fig. 12 is a cross-sectional view of another semiconductor structure provided in an embodiment of the present disclosure in a first direction.

Referring to fig. 1, 4 and 5, a semiconductor structure includes: a substrate 100; a plurality of semiconductor columns 110 disposed at intervals on the substrate 100, wherein the semiconductor columns 110 include a first doped region I, a channel region II, and a second doped region III sequentially distributed along a first direction Z, the semiconductor columns 110 have a hollow region 111, and at least the channel region II surrounds the hollow region 111; a bit line 120 extending along the second direction X, the bit line 120 contacting the first doping regions I of the plurality of semiconductor pillars 110 arranged along the second direction X; and a word line 130 extending along the third direction Y, the word line 130 surrounding the channel regions II of the plurality of semiconductor pillars 110 arranged along the third direction Y. The channel region II of the semiconductor pillar 110 is used for forming a conductive channel in the semiconductor channel, the word line 130 extending along the third direction Y surrounds the semiconductor pillar 110 of the channel region II, the channel region II is used for driving the transistor to form a conductive channel, the semiconductor pillar 110 has a hollow region 111, and at least the channel region II of the semiconductor pillar 110 is arranged around the hollow region 111, so that not only is the distance between the channel region II and the word line 130 controlled within a smaller range, but also the formation of a depletion layer in the process of controlling the conduction of the channel region II by the word line 130 is promoted, the switching current ratio of the transistor is increased, and the electrical performance of the semiconductor structure is improved; the semiconductor pillar 110 with the hollow region 111 is also utilized to avoid the problem of poor ability of the word line 130 to drive the channel region II by reducing the size of the semiconductor pillar 110, thereby reducing the difficulty of manufacturing the semiconductor pillar.

The material of the substrate 100 is a semiconductor material, and in some embodiments, the material of the substrate 100 is silicon. In other embodiments, the substrate 100 may be a germanium substrate, a silicon carbide substrate, or a silicon-on-insulator substrate.

The semiconductor pillar 110 is a semiconductor channel of a transistor, and in some embodiments, the transistor may be a full-surrounding gate transistor, which may achieve a minimum pattern size under a given process condition, and is advantageous for increasing the integration density of a semiconductor structure. The material of the semiconductor pillar 110 is a semiconductor material, and in some embodiments, the material of the semiconductor pillar 110 may be silicon.

In some embodiments, the substrate 100 may include a first substrate layer 104 and a second substrate layer 103 sequentially stacked in a first direction. The material of the first substrate layer 104 may be silicon, and the material of the second substrate layer 103 may be silicon germanium.

In some embodiments, the semiconductor pillar 110 has a cylindrical structure, which is advantageous for preventing the tip discharge phenomenon from occurring on the outer sidewall of the semiconductor pillar 110.

Referring to fig. 4, in some implementations, the first direction Z is a direction perpendicular to the surface of the substrate 100. That is, the extending direction of the semiconductor pillar 110 may be a direction perpendicular to the surface of the substrate 100, and the extending direction of the semiconductor pillar 110 for forming a semiconductor channel is set to be a direction perpendicular to the surface of the substrate 100, which is beneficial to obtaining the semiconductor pillar 110 by simple preparation in a patterning manner and reducing the difficulty in manufacturing a semiconductor structure. It is understood that in other embodiments, the first direction Z may be other directions, such as a direction parallel to the surface of the substrate 100.

Referring to fig. 4, the semiconductor pillar 110 includes a first doped region I, a channel region II, and a second doped region III sequentially distributed along the first direction Z, where the first doped region I and the second doped region III are used to form a source and a drain of a transistor, and the channel region II of the semiconductor pillar 110 is used to form a conductive channel of the transistor. The first doped region I and the second doped region III are doped regions, and in some embodiments, the type of dopant ions in the doped regions may be different from the type of dopant ions in the channel region II. Specifically, in one example, the dopant ions in the doped region may be N-type ions, the dopant ions in the channel region II may be P-type ions, the P-type ions may be at least one of boron ions, indium ions or gallium ions, and the N-type ions may be at least one of arsenic ions, phosphorus ions or antimony ions. In another example, the dopant ions in the doped region may be P-type ions, and the dopant ions in the channel region II may be N-type ions. In other embodiments, the type of dopant ions in the doped region may also be the same as the type of dopant ions in the channel region II, i.e., the semiconductor pillar 110 may be used to form a junction-free field effect transistor.

Further, taking the first direction Z as a direction perpendicular to the surface of the substrate 100 as an example, the semiconductor pillars 110 on the substrate 100 may be arranged in an array, the arrangement direction of the rows in the semiconductor pillars 110 is a second direction X, the arrangement direction of the columns is a third direction Y, and the second direction X is different from the third direction Y. It should be noted that the definitions of "row" and "column" are opposite, that is, the arrangement direction of the columns may be defined as the second direction X, and the arrangement direction of the rows may be defined as the third direction Y.

Referring to fig. 4, the word line 130 extends in the third direction Y and surrounds the channel region II of the semiconductor pillar 110. Specifically, each word line 130 may surround the channel region II of one column of the semiconductor pillars 110 arranged along the third direction Y. The word line 130 serves as a gate of the transistor, and is used for turning on the channel region II based on the control signal, so as to realize the transmission of carriers between the source and the drain. The material of the word line 130 is a conductive material, and in some examples, the material of the word line 130 may include at least one of polysilicon, tungsten, molybdenum, titanium, cobalt, or ruthenium.

Referring to fig. 4, the semiconductor structure further includes: and a gate dielectric layer 140, wherein the gate dielectric layer 140 surrounds the channel region II of the semiconductor pillar 110 and is located between the word line 130 and the semiconductor pillar 110. The gate dielectric layer 140 is used to make the source of the transistor driven by the word line 130 and the drain of the transistor conductive. In some embodiments, the gate dielectric layer 140 may be made of silicon oxide, and a thermal oxidation process is adopted to form silicon oxide on the semiconductor pillar 110 made of silicon, which is beneficial to reducing the difficulty in preparing the gate dielectric layer 140. In other embodiments, the material of the gate dielectric layer 140 may also be silicon nitride or silicon oxynitride.

Referring to fig. 1, 4 or 5, a semiconductor pillar 110 in a semiconductor structure has a hollow region 111, and the hollow region 111 may be a void or hole without semiconductor pillar material.

Referring to fig. 4, in some implementations, the cross-sectional shape of the hollow region 111 includes a circle in a cross-section perpendicular to the first direction Z. Therefore, the inner wall of the semiconductor pillar 110 facing the hollow area 111 is a smooth inner wall, which is beneficial to avoiding the phenomenon of point discharge on the inner wall of the semiconductor pillar 110 facing the hollow area 111, and is further beneficial to improving the electrical performance of the semiconductor structure. In other embodiments, the cross-sectional shape of the hollow area 111 in a cross-section perpendicular to the first direction Z may also be an ellipse or other irregular shape.

Referring to fig. 1 or fig. 4, in some embodiments, the semiconductor pillar 110 is a cylindrical structure, the hollow region 111 may be located in an axial region at the center of the channel region II of the semiconductor pillar 110, and on a cross section perpendicular to the first direction Z, the size of a circle cut by the hollow region 111 is the same, that is, the hollow region 111 is a cylindrical region, and in addition, the thickness of the channel region II outside the hollow region 111 is the same, so that it is beneficial to ensure that the shape of the channel region II driven by the word line 130 is uniform, and the channel region II with the uniform shape is beneficial to improving the electrical performance of the semiconductor structure.

Referring to fig. 4, in some embodiments, the hollow region 111 penetrates the semiconductor pillar 110 in a direction pointing along the first doped region I toward the second doped region III, and both the first doped region I and the second doped region III surround the hollow region 111. Therefore, the continuous channel region II is formed between the first doping region I and the second doping region III in the first direction Z, a continuous carrier transmission channel is formed between the first doping region I and the second doping region III, and the carrier transmission between the first doping region I and the second doping region III is facilitated.

In some embodiments, referring to fig. 4, in a cross section perpendicular to the first direction Z, a cross sectional shape of the hollow region 111 surrounded by the first doping region I and a cross sectional shape of the hollow region surrounded by the second doping region III are the same, and are also the same as a cross sectional shape of the hollow region 111 surrounded by the channel region II, so that it is not only beneficial to ensure that the first doping region I and the second doping region III have the continuous channel region II connected in the first direction Z, but also beneficial to reduce difficulty in preparing the hollow region 111 by using the same process and simultaneously preparing and forming the hollow region 111 in the cross section perpendicular to the first direction Z.

In some implementations, in a cross section perpendicular to the first direction Z, a cross-sectional area of the hollow region 111 is a first area, a sum of cross-sectional areas of the hollow region 111 and the channel region II is a second area, and a ratio of the first area to the second area is 1:3 to 5:6. for example, the ratio of the first area to the second area may be 1: 3. 2:3 or 1:2. an excessively small ratio of the first area to the second area may result in an excessively thin thickness of the semiconductor pillar 110 surrounding the hollow region 111, and the excessively thin thickness of the semiconductor pillar 110 may have poor structural stability; the ratio of the first area to the second area is too large, which may cause the spacing distance between the word line 130 and the channel region II adjacent to the hollow region 111 to be too large, and thus the word line 130 drives the channel region II to be turned on, and therefore, the ratio of the first area to the second area is set to 1:3 to 5:6, the semiconductor structure is not only beneficial to ensuring higher structural stability, but also beneficial to avoiding overlarge spacing distance between the partial channel region II far away from the word line 130 and the word line 130, and the electrical performance of the semiconductor structure is beneficial to being improved.

Referring to fig. 2 and 6, in some implementations, the semiconductor structure further includes: and an insulating layer 113, wherein the hollow space 111 is filled with the insulating layer 113. Therefore, the semiconductor column 110 with the hollow region 111 is prevented from being deformed under the action of external force, and the structural stability of the semiconductor structure is improved.

In some embodiments, referring to fig. 3 and 10, the insulating layer 113 is located in the partial hollow region 111, and the insulating layer 113 and the semiconductor pillar 110 enclose an air gap 114, where the insulating layer 113 is beneficial to ensure that the semiconductor pillar 110 has high structural stability, and the air gap 114 is beneficial to promote heat dissipation of the semiconductor structure. Moreover, the air gap 114 has a low dielectric constant, which is beneficial to reducing the parasitic capacitance of the semiconductor structure, and is further beneficial to improving the electrical performance of the semiconductor structure.

In addition, the insulating layer 113 is an insulating material, and in some embodiments, the material of the insulating layer 113 may be silicon nitride with high hardness and better support. In other embodiments, the material of the insulating layer 113 may also be an insulating material such as silicon oxide, silicon oxynitride, or a high-K dielectric material.

In some embodiments, the hollow region 111 penetrates the semiconductor pillar 110, the first doped region I and the second doped region III both surround the hollow region 111, the insulating layer 113 is located in a portion of the hollow region 111, the insulating layer 113 is located at least on an inner wall of the second doped region III facing the hollow region 111, and the hollow region 111 outside the insulating layer 113 is an air gap 114. The insulating layer 113 located on the inner wall of the second doped region III is beneficial to providing support for the structure located at one end of the second doped region III far away from the channel region II, avoiding the structure located at one end of the second doped region III, which is caused by the overlarge opening of the hollow region 111, from losing support and falling off, and avoiding the formation of a subsequent structure, and impurities with conductivity enter the hollow region 111, thereby being beneficial to avoiding the failure of the transistor.

In some implementations, referring to fig. 7, the insulating layer 113 is also located at an inner wall of the first doping region I facing the hollow region 111, and at an inner wall of the channel region II facing the hollow region 111. The insulating layer 113 on the inner wall of the first doped region I provides support for the insulating layer 113 on the inner wall of the channel region II, and further provides support for the insulating layer 113 on the inner wall of the second doped region III, so that the insulating layer 113 on the inner wall of the second doped region III is prevented from falling off.

In some implementations, referring to fig. 8, the insulating layer 113 further blocks an end region of the hollow region 111 adjacent to the second doped region III, which is beneficial to provide a more stable support for a structure located at an end of the second doped region III and to prevent impurities from entering the hollow region 111, thereby providing good protection for the hollow region 111.

In some embodiments, referring to fig. 9, the insulating layer 113 also blocks an end region of the hollow region 111 adjacent to the first doped region I. When the insulating layer 113 is formed on the inner wall of the semiconductor pillar 110 facing the hollow area 111, the insulating layer 113 with a certain thickness is also formed on the substrate 100 facing the hollow area 111, that is, the insulating layer 113 located at the end region of the hollow area 111 adjacent to the first doped region I remains on the insulating layer 113 on the substrate 100 facing the hollow area 111, which is beneficial to avoiding adding an additional removing process to remove the insulating layer 113 on the substrate 100, and is further beneficial to reducing the manufacturing difficulty of the semiconductor structure.

In some embodiments, referring to fig. 10, the insulating layer 113 blocks an end region of the hollow region 111 adjacent to the first doping region I and an end region of the hollow region 111 adjacent to the second doping region III. The insulating layer 113 for blocking the end region of the hollow region 111 adjacent to the second doped region III is beneficial to providing good protection for the hollow region 111, and the insulating layer 113 for blocking the end region of the hollow region 111 adjacent to the first doped region I is beneficial to avoiding adding an additional removal process to remove the insulating layer 113 on the substrate 100, thereby being beneficial to reducing the manufacturing difficulty of the semiconductor structure.

In some implementations, referring to fig. 11 and 12, the insulating layer 113 at least blocks an end region of the hollow region 111 adjacent to the second doping region III, and the insulating layer 113 is located in a part of the hollow region 111, and the hollow region 111 outside the insulating layer 113 is an air gap 114. It should be noted that, when the semiconductor pillar 110 is smaller in size, the top opening of the hollow area 111 far away from the substrate 100 is also smaller, and it is difficult to fill the insulating layer 113 in the hollow area 111, so that the insulating layer 113 can be formed only at the top opening of the hollow area 111 far away from the substrate 100, which ensures that the insulating layer 113 has a certain protection effect on the hollow area 111, and ensures that the insulating layer 113 provides support for a subsequently formed structure, and is beneficial to reducing the difficulty of forming the insulating layer 113 in the hollow area 111.

In some embodiments, the semiconductor structure further includes a capacitor (not shown), the capacitor is electrically connected to the second doped region III, and the capacitor is located on a surface of the insulating layer 113 away from the first doped region I. Since the surface of the insulating layer 113 away from the first doped region I provides a certain support for the capacitor, the capacitor has higher structural stability.

Referring to fig. 1 to 12, the semiconductor structure further includes a plurality of bit lines 120 extending along the second direction X, each bit line 120 being located between and electrically connected to portions of the first doped regions I of the plurality of semiconductor pillars 110 arranged along the second direction X, for leading out a source or a drain of the transistor, and for providing an electrical signal to the source or the drain of the transistor.

In addition, the material of the bit line 120 is a conductive material, and in some embodiments, the material of the bit line 120 may include at least one of tungsten, molybdenum, titanium, cobalt, or ruthenium.

In some implementations, referring to fig. 1-12, the semiconductor structure further includes: and a semiconductor layer 112, wherein the semiconductor layer 112 is located on the surface of the substrate 100 and extends along the second direction X, and the semiconductor layer 112 is connected to the outer wall of the semiconductor pillar 110 arranged along the second direction X, which is adjacent to the surface of the substrate 100. The semiconductor layer 112 connects the first doping regions I of the semiconductor pillars 110 arranged along the second direction X to each other, which is advantageous for improving the ability of the bit line 120 to provide a control signal to the first doping regions I of the semiconductor pillars 110 arranged along the second direction X.

In some implementations, the semiconductor pillar 110 and the semiconductor layer 112 are a unitary structure. The semiconductor pillar 110 is formed simultaneously with the semiconductor layer 112 integrally formed with the semiconductor pillar 110, which is advantageous for reducing the difficulty in manufacturing the semiconductor layer 112. In addition, compared to the semiconductor pillar 110 and the semiconductor layer 112 which are separate bodies, the barrier to the transfer of carriers between the semiconductor pillar 110 and the semiconductor layer 112 which are integrally formed is smaller.

In some implementations, referring to fig. 1 to 12, the bit line 120 is also located on the surface of the semiconductor layer 112, and the bit line 120 surrounds a portion of the first doping region I of the semiconductor pillar 110. Therefore, the contact area between the bit line 120 and the first doped region I is increased, which is beneficial to promoting the ability of the bit line 120 to transmit the control signal to the first doped region I, and is further beneficial to improving the electrical performance of the semiconductor structure.

In some embodiments, the semiconductor structure further includes a dielectric layer 150, the dielectric layer 150 filling a region between adjacent semiconductor pillars 110, filling a region between adjacent word lines 130, and filling a region between adjacent bit lines 120. The material of the dielectric layer 150 is an insulating material, and in some embodiments, the material of the dielectric layer 150 may be at least one of silicon oxide or silicon nitride.

The semiconductor structure provided by the above embodiment includes: a first doping region I, a channel region II and a second doping region III sequentially distributed in a direction away from the surface of the substrate 100, wherein the channel region II of the semiconductor pillar 110 is used for forming a channel region of a transistor, the word line 130 extending along the third direction Y surrounds the channel region II of the semiconductor pillar 110, the channel region II for driving the transistor forms a conductive channel, the semiconductor pillar 110 has a hollow region 111, and at least the channel region II of the semiconductor pillar 110 is arranged around the hollow region 111, so that, on one hand, the distance from the channel region II to the word line 130 is controlled in a smaller range, thereby avoiding the central part of the channel region II farther from the word line 130 from being controlled by the word line 130, promoting the formation of a depletion layer in the process of controlling the channel region II to be conducted by the word line 130, and increasing the on-off current ratio of the transistor; on the other hand, the problem of poor capability of the word line 130 to drive the channel region II by reducing the size of the semiconductor pillar 110 is avoided, which is beneficial to reducing the manufacturing difficulty of the semiconductor structure.

In another aspect, a method for forming a semiconductor structure is provided for forming the semiconductor structure according to the above embodiments, and the method for forming a semiconductor structure according to the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, for the same or corresponding parts as those in the foregoing embodiments, reference may be made to the detailed description of the foregoing embodiments, and details will not be described below.

Fig. 13 to fig. 18 are schematic views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present disclosure.

The forming method of the semiconductor structure comprises the following steps: referring to fig. 13 to 15, a substrate 100 is provided; a plurality of semiconductor pillars 110 arranged at intervals on the substrate 100 are formed, the semiconductor pillars 110 include a first doped region I, a channel region II, and a second doped region III sequentially distributed along a first direction Z, the semiconductor pillars 110 have a hollow region 111, and at least the channel region II surrounds the hollow region 111. The hollow region 111 prevents the channel region II far away from the word line 130 from being controlled by the word line 130, so that the formation of a depletion layer is promoted when the word line 130 controls the conduction of the channel region II, the switching current ratio of the transistor is increased, and the electrical performance of the semiconductor structure is improved.

In some embodiments, the first direction Z may be a direction perpendicular to the surface of the substrate 100, the hollow region 111 may penetrate through the semiconductor pillar 110 in a direction pointing along the first doped region I toward the second doped region III, and both the first doped region I and the second doped region III surround the hollow region 111, and the forming the semiconductor pillar 110 includes: referring to fig. 13 to 14, a plurality of sacrificial structures 101 arranged at intervals and extending along the first direction Z are formed on a substrate 100. The sacrificial structure 101 is used as a support for forming the semiconductor pillar 110 to assist in forming the semiconductor pillar 110, which is beneficial to reducing the difficulty of the process for forming the semiconductor pillar 110.

Specifically, the step of forming the semiconductor pillar 110 using the sacrificial structure 101 may include:

referring to fig. 13 to 14, an initial substrate 200 is provided; the initial substrate 200 may include an initial first substrate layer 201 and an initial second substrate layer 202 stacked in a first direction, in some embodiments, the initial first substrate layer 201 may be a silicon layer, the initial second substrate layer 202 may be a silicon germanium layer, a mask layer having an etching window is formed on the initial second substrate layer 202, the initial second substrate layer 202 with a partial thickness exposed by the mask layer is etched to form the sacrificial structure 101, and then the mask layer is removed. The method for forming the sacrificial structure 101 by patterning the initial second substrate layer 202 is beneficial to simplifying the process flow for forming the sacrificial structure 101 and saving the preparation cost.

In some embodiments, the initial substrate 200 may be patterned by using a SADP (Self-aligned Double Patterning) process or a salqp (Self-aligned Quadruple Patterning) process, where the SADP process or the salqp process may form a pattern with a smaller size, which is beneficial to improving the fineness of the Patterning process of the initial substrate 200 and forming the sacrificial structure 101 with a smaller size, thereby reducing the size of the semiconductor structure.

In addition, the material of the sacrificial structure 101 formed using the silicon germanium layer is silicon germanium.

Referring to fig. 15, a semiconductor film is formed on the surface of the sacrificial structure 101, and specifically, an epitaxial process may be used to form a semiconductor film on the surface of the sacrificial structure 101. And a semiconductor film at the side of the sacrificial structure 101 is used as the semiconductor pillar 110. In some embodiments, referring to fig. 15, forming a semiconductor film on a surface of the sacrificial structure 101 further includes: a semiconductor film is formed on the substrate 100 other than the sacrificial structure 101, and the semiconductor film on the substrate 100 other than the sacrificial structure 101 serves as an initial semiconductor layer. The initial semiconductor layer is used to form a semiconductor layer connected to a portion of the first doping region I of the semiconductor pillar 110. Forming the initial semiconductor layer while forming the semiconductor pillars 110 is advantageous to simplify the process flow and to save the manufacturing cost.

In some embodiments, after the semiconductor pillar 110 is formed, a doping process is further performed on the semiconductor pillar 110 to form a channel region II and doped regions located at two sides of the channel region II, that is, the channel region II, the first doped region I, and the second doped region III are formed. The doped regions at both sides of the channel region II form a source and a drain of the semiconductor structure. Specifically, in some embodiments, the semiconductor pillar 110 may be doped using any one of ion implantation or thermal diffusion to form the channel region II, the first doping region I, and the second doping region III of the semiconductor pillar 110.

Referring to fig. 16 to 17, a bit line 120 extending along the second direction X is formed, and the bit line 120 contacts the first doping region I of the plurality of semiconductor pillars 110 arranged along the second direction X to be electrically connected to the first doping region I, for extracting a source or a drain of a transistor, and for supplying an electrical signal to the source or the drain of the transistor. In some implementations, forming bit line 120 includes: referring to fig. 16, a bit line layer 102 is formed between sidewalls of a portion of the first doped region I of the semiconductor pillar 110, and the bit line layer 102 may also be formed on the initial semiconductor layer, specifically, a deposition process may be used to deposit a bit line layer material all over, and then remove the excess bit line layer material to form the bit line layer 102. Or, a mask layer covering the semiconductor pillar 110 is formed first, a bit line layer material is deposited over the entire surface by using a deposition process, and the bit line layer 102 located between the sidewalls of the first doped region I of the semiconductor pillar 110 is obtained after the mask layer covering the semiconductor pillar 110 is removed.

Referring to fig. 16 to 17, after forming the bit line layer 102, the bit line layer 102 may be patterned to remove a portion of the bit line layer 102, so as to form a plurality of bit lines 120 extending along the second direction X and independent of each other.

In some embodiments, referring to fig. 16-17, removing a portion of the bit line layer 102 further comprises: the initial semiconductor layer at the bottom of the bit line layer 102 is removed to form a semiconductor layer 112 extending along the second direction X, and the semiconductor layer 112 is connected to the outer wall of the semiconductor pillars 110 arranged along the second direction X adjacent to the surface of the substrate 100. When part of the bit line layer 102 is removed, the initial semiconductor layer at the bottom of the bit line layer 102 is also removed, so that the mutually isolated semiconductor layers 112 at the bottom of the bit lines 120 are also formed while the mutually independent bit lines 120 are formed, which is beneficial to simplifying the process flow for forming the semiconductor layers 112 and reducing the preparation cost of the semiconductor structure. In addition, the semiconductor layer 112 contacting the bottom surface of the substrate 100 adjacent to the bit line 120 is formed, which is beneficial to increasing the contact area between the bit line 120 and the first doped region I, and further beneficial to promoting the carrier transmission between the bit line 120 and the first doped region I, and improving the electrical performance of the semiconductor structure.

In some embodiments, the initial semiconductor layer at the bottom of the partial bit line layer 102 is removed simultaneously with the removal of the substrate 100 with a partial thickness at the bottom of the partial initial semiconductor layer, which is beneficial to avoiding the generation of connection between the semiconductor layers 112 caused by the residual initial semiconductor layer, and thus beneficial to avoiding the failure of the semiconductor structure.

Referring to fig. 18, word lines extending in the third direction Y are formed, and the word lines 130 surround the channel regions II of the plurality of semiconductor pillars 110 arranged in the third direction Y. Specifically, after the bit line 120 is formed, a first dielectric layer filling between sidewalls of the first doping regions I of the adjacent semiconductor pillars 110 may be formed, the first dielectric layer exposes sidewalls of the channel regions II of the semiconductor pillars 110, word line layers filling between sidewalls of the channel regions II of the adjacent semiconductor pillars 110 are formed on the first dielectric layer, the word line layers are patterned, a portion of the word line layers are removed, and word lines 130 extending along the third direction Y and independent of each other are formed, wherein a process of forming the first dielectric layer and a process of forming the word line layers may be a deposition process. The material of the first dielectric layer may be an insulating material, for example, silicon oxide.

Referring to fig. 18, before forming the word line layer, it may further include: a gate dielectric layer 140 is formed, and the gate dielectric layer 140 surrounds the channel region II of the semiconductor pillar 110. Specifically, after the first dielectric layer is formed, the semiconductor pillar 110 may be directly oxidized by a thermal oxidation process, and the gate dielectric layer 140 is formed on the side surface of the channel region II of the semiconductor pillar 110. In some embodiments, the side of the second doped region III of the semiconductor pillar 110 is also formed with a gate dielectric layer 140.

Referring to fig. 18, after forming the word lines 130 and the gate dielectric layer 140, a deposition process may be further used to form a second dielectric layer between sidewalls of adjacent word lines 130 and between sidewalls of the second doping regions III of adjacent semiconductor pillars 110, where the second dielectric layer and the first dielectric layer form a dielectric layer 150, and the dielectric layer 150 fills a region between adjacent semiconductors, fills a region between adjacent word lines 130, and fills a region between adjacent bit lines 120, so as to form isolation between adjacent bit lines 120, isolation between adjacent word lines 130, and isolation between adjacent semiconductor pillars 110.

In some embodiments, referring to fig. 18, after the dielectric layer 150 is formed, the semiconductor film of the sacrificial structure 101 far from the top surface of the substrate 100 is removed to expose the top surface of the sacrificial structure 101, and then the sacrificial structure 101 is removed by using an etching process with a higher etching selectivity for the sacrificial structure 101 to form the hollow region 111. In this way, by removing the sacrificial structure 101, the semiconductor pillar 110 having the hollow region 111 can be easily prepared. It is advantageous to simplify the process of preparing the semiconductor pillars 110 having the hollow regions 111.

Referring to fig. 11 or 12, in some implementations, after removing the sacrificial structure 101, further comprising: an insulating layer 113 is formed in the hollow region 111, the insulating layer 113 at least blocks a top region of the hollow region 111 away from the substrate 100, the insulating layer 113 is located in a part of the hollow region 111, and the hollow region 111 outside the insulating layer 113 is an air gap 114. The insulating layer 113 is favorable for providing support for a structure at one end of the second doped region III away from the substrate 100, so as to prevent the structure at one end of the second doped region III from being released due to an excessively large opening of the hollow region 111, and to ensure that the semiconductor column 110 has high structural stability. The air gap 114 is beneficial to promoting the heat dissipation of the semiconductor structure, and the air gap 114 has a low dielectric constant, which is beneficial to reducing the parasitic capacitance of the semiconductor structure, thereby being beneficial to improving the electrical performance of the semiconductor structure.

Specifically, a deposition process may be adopted to form the insulating layer 113 in the hollow area 111, where the length of the hollow area 111 in the first direction Z is larger, and when the width perpendicular to the first direction Z is smaller, due to the limitation of the deposition process, the deposition process may form the insulating layer 113 only in the top area of the hollow area 111 away from the substrate 100, and meanwhile, the hollow area 111 outside the insulating layer 113 is ensured to be the air gap 114.

In some implementations, forming the insulating layer 113 further includes: and forming a capacitor, wherein the capacitor is electrically connected to the second doped region III and is located on the top surface of the insulating layer 113 away from the substrate 100. The surface of the insulating layer 113 far away from the first doped region I can be used for supporting the capacitor, so that the capacitor is prevented from falling off, and the structural stability of the capacitor is improved.

In the method for forming the semiconductor structure provided by the above embodiment, the semiconductor pillar 110 having the hollow region 111 is formed, and the hollow region 111 prevents the central portion of the channel region II, which is far away from the word line 130, from being controlled by the word line 130, thereby promoting the formation of a depletion layer in the process of controlling the conduction of the channel region II by the word line 130, increasing the on-off current ratio of the transistor, and facilitating the improvement of the electrical performance of the semiconductor structure. Moreover, the semiconductor pillar 110 having the hollow region 111 is formed by using the sacrificial structure 101, which is beneficial to reducing the difficulty in manufacturing the semiconductor pillar 110.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the present disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure in practice. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the disclosure, and it is intended that the scope of the disclosure be limited only by the claims appended hereto.

Claims (19)

1. A semiconductor structure, comprising:

a substrate;

the semiconductor column comprises a first doping area, a channel area and a second doping area which are sequentially distributed along a first direction, the semiconductor column is provided with a hollow area, and at least the channel area surrounds the hollow area;

a bit line extending in a second direction, the bit line contacting the first doped regions of the plurality of semiconductor pillars arranged in the second direction;

a word line extending in a third direction, the word line surrounding the channel regions of the plurality of semiconductor pillars arranged in the third direction.

2. The semiconductor structure of claim 1, wherein a cross-sectional area of the hollow region in a cross-section perpendicular to the first direction is a first area, a sum of cross-sectional areas of the hollow region and the channel region is a second area, and a ratio of the first area to the second area is 1:3 to 5:6.

3. the semiconductor structure of claim 1, wherein the hollow region extends through the semiconductor pillar in a direction along the first doped region toward the second doped region, and wherein the first doped region and the second doped region both surround the hollow region.

4. The semiconductor structure of claim 1 or 3, further comprising: the insulating layer is filled in the hollow area; or, the insulating layer is positioned in part of the hollow area, and an air gap is formed by the insulating layer and the semiconductor column in a surrounding mode.

5. The semiconductor structure of claim 3, further comprising: the insulating layer is positioned in part of the hollow area, the insulating layer is at least positioned on the inner wall of the second doping area facing the hollow area, and the hollow area outside the insulating layer is an air gap.

6. The semiconductor structure of claim 5, wherein the insulating layer is further located in the first doped region toward an inner wall of the hollow region and in the channel region toward the inner wall of the hollow region.

7. The semiconductor structure of claim 6, wherein the insulating layer further blocks an end region of the hollow region adjacent to the second doped region; and/or the insulating layer also blocks an end region of the hollow region adjacent to the first doped region.

8. The semiconductor structure of claim 3, further comprising: the insulating layer at least blocks an end part region of the hollow region adjacent to the second doping region, the insulating layer is positioned in part of the hollow region, and the hollow region outside the insulating layer is an air gap.

9. The semiconductor structure of claim 5 or 8, further comprising a capacitor electrically connected to the second doped region and located at a surface of the insulating layer remote from the first doped region.

10. The semiconductor structure of claim 1, wherein the first direction is a direction perpendicular to the surface of the substrate.

11. The semiconductor structure of claim 10, further comprising: the semiconductor layer is positioned on the surface of the substrate and extends along the second direction, and the semiconductor layer is connected with the outer wall, adjacent to the surface of the substrate, of the semiconductor columns arranged along the second direction.

12. The semiconductor structure of claim 11, wherein the semiconductor pillar is a unitary structure with the semiconductor layer.

13. The semiconductor structure of claim 11, wherein the bit line is further located on a surface of the semiconductor layer, and the bit line surrounds a portion of the first doped region of the semiconductor pillar.

14. A method for forming a semiconductor structure is provided,

providing a substrate;

forming a plurality of semiconductor columns which are arranged at intervals and are positioned on the substrate, wherein the semiconductor columns comprise a first doping area, a channel area and a second doping area which are sequentially distributed along a first direction, the semiconductor columns are provided with a hollow area, and at least the channel area surrounds the hollow area;

forming a bit line extending along a second direction, the bit line contacting the first doped regions of the plurality of semiconductor pillars arranged along the second direction;

forming a word line extending in a third direction, the word line surrounding the channel regions of the plurality of semiconductor pillars arranged in the third direction.

15. The method of claim 14, wherein the first direction is a direction perpendicular to the substrate surface, the hollow region penetrates the semiconductor pillar in a direction along the first doped region toward the second doped region, and the first doped region and the second doped region both surround the hollow region, and forming the semiconductor pillar comprises:

forming a plurality of sacrificial structures arranged at intervals and extending along the first direction on the substrate;

forming a semiconductor film on the surface of the sacrificial structure;

removing the semiconductor film on the top surface of the sacrificial structure far away from the substrate, wherein the semiconductor film on the side surface of the sacrificial structure is used as the semiconductor pillar;

and removing the sacrificial structure to form the hollow area.

16. The method of forming a semiconductor structure of claim 15, wherein forming the bit line comprises:

before removing the sacrificial structure, forming a bit line layer positioned between the side walls of part of the first doped region of the semiconductor column; and removing part of the bit line layer to form a plurality of mutually independent bit lines extending along the second direction.

17. The method of forming a semiconductor structure according to claim 16, wherein the forming the semiconductor film on the surface of the sacrificial structure further comprises:

forming a semiconductor film on the substrate other than the sacrificial structures, the semiconductor film on the substrate other than the sacrificial structures serving as an initial semiconductor layer;

the bit line layer is also located on the initial semiconductor layer, removing a portion of the bit line layer further comprising:

and removing part of the initial semiconductor layer at the bottom of the bit line layer to form a semiconductor layer extending along the second direction, wherein the semiconductor layer is connected with the outer wall, adjacent to the surface of the substrate, of the semiconductor pillar arranged along the second direction.

18. The method of forming a semiconductor structure of claim 15, further comprising:

and forming an insulating layer in the hollow area, wherein the insulating layer at least blocks the top area of the hollow area far away from the substrate, the insulating layer is positioned in part of the hollow area, and the hollow area outside the insulating layer is an air gap.

19. The method of forming a semiconductor structure of claim 18, further comprising: and forming a capacitor, wherein the capacitor is electrically connected with the second doped region and is positioned on the top surface of the insulating layer far away from the substrate.

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