CN115332187A - Package based on interposer - Google Patents
Package based on interposer Download PDFInfo
- Publication number
- CN115332187A CN115332187A CN202211257968.3A CN202211257968A CN115332187A CN 115332187 A CN115332187 A CN 115332187A CN 202211257968 A CN202211257968 A CN 202211257968A CN 115332187 A CN115332187 A CN 115332187A
- Authority
- CN
- China
- Prior art keywords
- chip
- interposer
- package
- plate
- shaped body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000009434 installation Methods 0.000 claims abstract description 5
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 13
- 239000011368 organic material Substances 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 4
- 239000000945 filler Substances 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- 239000012778 molding material Substances 0.000 claims description 3
- 239000011347 resin Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- 238000004806 packaging method and process Methods 0.000 abstract description 9
- 239000004065 semiconductor Substances 0.000 abstract description 5
- 238000000034 method Methods 0.000 description 11
- 239000003292 glue Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 5
- 239000002131 composite material Substances 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 238000009713 electroplating Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910052809 inorganic oxide Inorganic materials 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
Abstract
The embodiment of the invention provides a package based on an interposer, and belongs to the field of semiconductor packaging. The package at least includes: the chip comprises a substrate, an intermediate layer, a first chip set and a second chip set, wherein the first chip set and the second chip set respectively comprise at least one chip; the interposer includes a first portion and a second portion; the first chip group is connected to one side of the first part through flip chip; the other side of the first part and the second part are stacked to define at least one space for accommodating the second chipset; one side of the space is a substrate, and the second chip set is connected to the substrate through an inverted installation; the first part is a plate-shaped body, the second part comprises a plurality of columnar bodies, the columnar bodies are positioned on the periphery of one surface of the plate-shaped body, and the sum of the cross-sectional areas of the plurality of columnar bodies is smaller than the area of the surface of the plate-shaped body. The package realizes miniaturization and large capacity of a chip package structure through a three-dimensional structure of an interposer.
Description
Technical Field
The present invention relates to the field of semiconductor packaging, and in particular to an interposer-based package.
Background
With the rapid development of the electronic industry, electronic devices are required to be more and more miniaturized, multi-functionalized, and have a large capacity in order to meet the needs of users, and thus, a semiconductor package having a plurality of semiconductor chips is required. The semiconductor package in the prior art not only has complex process and high manufacturing cost, but also can not realize the miniaturization and the large capacity of the package by the existing package structure.
Disclosure of Invention
The invention provides a package based on an interposer, which realizes miniaturization and large capacity of a chip package structure through a three-dimensional structure of the interposer.
To achieve the above object, an embodiment of the present invention provides an interposer-based package, which includes at least: the chip comprises a substrate, an intermediate layer, a first chip set and a second chip set, wherein the first chip set and the second chip set respectively comprise at least one chip; the interposer includes a first portion and a second portion; the first chip group is connected to one side of the first part through a flip chip; the other side of the first part and the second part are stacked to define at least one space for accommodating the second chipset; one side of the space is a substrate, and the second chip set is connected to the substrate through an inverted installation; the first part is a plate-shaped body, the second part comprises a plurality of columnar bodies, the columnar bodies are positioned on the periphery of one surface of the plate-shaped body, and the sum of the cross-sectional areas of the plurality of columnar bodies is smaller than the area of the surface of the plate-shaped body.
Optionally, the column is located at the periphery of one surface of the plate-shaped body, and includes: the columnar bodies are located on the peripheries of two opposite sides of one surface of the plate-shaped body, or the columnar bodies are located at four corners of the periphery of one surface of the plate-shaped body, or the columnar bodies are located on the whole periphery of one surface of the plate-shaped body.
Optionally, a through hole is formed in the interposer, and a conductive metal pillar is arranged in the through hole and used for connecting multiple chips; the size of the perforations is 20-100 microns.
Optionally, the perforation mode is at least one of mechanical perforation, laser perforation and photoetching and etching opening; the perforated material is metal.
Optionally, a gap exists between the space and the second chipset, and the size of the gap is determined by the second chipset.
Optionally, the thickness of the interposer is in a range of 100-400 microns, wherein the thickness of the first portion of the interposer is in a range of: 100-200 microns; the second portion of the interposer has a thickness in a range of: 100-200 microns.
Optionally, the interposer further includes at least: redistribution wires disposed in at least one of the first portion and the second portion.
Optionally, the material of the interposer is an organic material, and the type of the organic material is at least one of a molding material and a resin with a filler.
Optionally, the second chipset is a low power consumption chip.
Optionally, the package further comprises a heat sink; the radiating fins are arranged on at least one surface of the first chip group and used for radiating the first chip group.
The invention provides a package based on an interposer, which at least comprises: the chip comprises a substrate, an intermediate layer, a first chip set and a second chip set, wherein the first chip set and the second chip set respectively comprise at least one chip; the interposer includes a first portion and a second portion; the first chip set is connected to one side of the first part through an inverted installation; the other side of the first part and the second part are stacked to define at least one space for accommodating the second chipset; one side of the space is a substrate, and the second chip set is connected to the substrate through an inverted installation; the first part is a plate-shaped body, the second part comprises a plurality of cylindrical bodies, the cylindrical bodies are positioned on the periphery of one surface of the plate-shaped body, and the sum of the cross-sectional areas of the plurality of cylindrical bodies is smaller than the area of the surface of the plate-shaped body. The invention realizes the miniaturization and the large capacity of the chip packaging structure through the three-dimensional structure of the intermediate layer.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:
FIGS. 1a-1c are schematic diagrams of a chip package according to the present invention;
FIGS. 2a-2c are schematic views of another chip package of the present invention;
fig. 3 is a schematic diagram of a chip package including a heat sink of the present invention.
Description of the reference numerals
101-a first portion;
102-a second portion;
103-perforation;
104-a first chipset;
105-a second chipset;
106-substrate.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating embodiments of the invention, are given by way of illustration and explanation only, not limitation.
The invention provides a package based on an interposer, which at least comprises: a substrate 106, an interposer, a first chipset 104 and a second chipset 105, wherein each of the first chipset 104 and the second chipset 105 comprises at least one chip; the interposer includes a first portion 101 and a second portion 102; the first chip group 104 is connected to one side of the first portion 101 by flip chip; the other side of the first part 101 and the second part 102 are stacked to define at least one space for accommodating the second chipset 105; one side of the space is a substrate 106, and the second chipset 105 is connected to the substrate 106 through a flip chip. In flip chip packaging, the silicon chip is directly mounted on the substrate using solder bumps rather than wire bonds, providing dense interconnections with high electrical and thermal performance. The flip chip interconnection realizes ultimate miniaturization, reduces the packaging parasitic effect and realizes a new mode of chip power distribution and ground wire distribution which cannot be realized by other traditional packaging methods. The invention is an independent intermediate layer, connects the chips together in a flip-chip manner, has good flexibility, can be used for packaging the chips with low power consumption, can be suitable for connecting the chips with high performance and high power consumption, and has heat dissipation capability.
The first part 101 is a plate-shaped body, the second part 102 comprises a plurality of columns, the columns are located on the periphery of one surface of the plate-shaped body, and the sum of the cross-sectional areas of the columns is smaller than the area of the surface of the plate-shaped body, namely, the columns do not occupy one surface of the plate-shaped body. The column body is located at the periphery of one surface of the plate body and comprises: the columnar bodies are located on the peripheries of two opposite sides of one surface of the plate-shaped body, or the columnar bodies are located at four corners of the periphery of one surface of the plate-shaped body, or the columnar bodies are located on the whole periphery of one surface of the plate-shaped body.
Fig. 1a-1c are schematic diagrams of a chip package according to an embodiment of the invention, where fig. 1a is a cross-sectional view of the interposer of fig. 1c, fig. 1b is a left side view of the interposer of fig. 1c (a left side view or a right side view of the interposer of fig. 1 c), and fig. 1b is a right side view of the interposer of fig. 1c, which are schematic diagrams of the interposer of fig. 1c, and are schematic diagrams of the interposer of the invention, each of which is a cylindrical body located at the periphery of two opposite sides of one surface of the plate-shaped body.
As shown in fig. 1c, the interposer-based package includes at least: the chip package comprises a substrate 106, an interposer, a first chip set 104 and a second chip set 105, wherein the first chip set 104 and the second chip set 105 each comprise at least one chip; the interposer includes a first portion 101 and a second portion 102; the first chip 104 group is connected to one side of the first portion 101 by flip chip; the connection of the first chip set 104 with the first portion 101 is underfilled; the other side of the first part 101 and the second part 102 are stacked to define at least one space for accommodating the second chipset 105; one side of the space is a substrate 106, the second chipset 105 is connected to the substrate 106 by flip chip, and the connection between the second chipset 105 and the substrate 106 is filled with underfill. There is a gap between the space and the second chipset 105, the size of the gap being determined by the second chipset 105. The second chipset 105 is a low power chip, such as a sensor, a master chip, etc.; the gap is mainly used to protect the second chipset 105 from being damaged during the assembly process. The connection of the interposer second portion 102 to the substrate 106 is underfill.
A through hole 103 is arranged in the interposer, and a conductive metal column is arranged in the through hole 103 and used for connecting multiple chips; the perforations 103 have a size of 20-100 microns, which is typically the pore size. The perforation 103 is at least one of mechanical perforation, laser perforation and photoetching and etching opening; the material of the through hole 103 is metal.
The material of the intermediate layer is organic material, the type of the organic material is at least one of molding material and resin with filler, and the filler can be inorganic oxide, such as silicon oxide, aluminum oxide and the like. The interposer has a thickness in the range of 100-400 microns, wherein the first portion 101 of the interposer has a thickness in the range of: 100-200 microns; the thickness range of the second portion 102 of the interposer is: 100-200 microns.
The interposer further comprises at least: redistribution wires disposed in at least one of the first portion 101 and the first portion 101.
In another preferred embodiment, as shown in fig. 2a-2c, the interposer in the package is located at the periphery of the ring structure, and the hollow structure of the ring structure is used for arranging the chip, wherein fig. 2a is a cross-sectional view of the interposer in fig. 2c, the left side view in fig. 2b is a side view of the interposer in fig. 2c (left side view or right side view of the interposer in fig. 2 c), and the right side view in fig. 2b is a bottom view of the interposer in fig. 2 c.
The interposer further includes a first portion 101 and a second portion 102, the first portion 101 is a plate-shaped body, and the second portion 102 includes a plurality of columns located on the entire periphery of one surface of the plate-shaped body. The left side view of fig. 2b is a side view of the interposer as well, and the right side view of fig. 2b is a bottom view of the interposer.
The interposer reduces stress of the chip by using an organic material, and realizes miniaturization and high capacity of a chip packaging structure by a three-dimensional structure of the interposer.
The package of the present invention further includes a heat sink disposed on at least one surface of the first chip set 104 for dissipating heat of the first chip set 104. Fig. 3 is a schematic diagram of a chip package including a heat sink according to the present invention, which is shown in fig. 3, and connects a chip (first chip group 104) with high power consumption at the outermost side for better heat dissipation. The interposer connects a plurality of chips, and the second chipset 105 and the substrate 106 are connected by solder balls. The second chipset 105 has a fill underneath to protect the connections between the chips and the substrate 106. The interposer may be an arch structure or a rectangular frame structure with a void in the middle. The interposer and the substrate 106 are directly connected by solder balls, and organic filling or film glue can be added to the solder balls to improve reliability. The second chipset 105 may be a low power chip, such as a memory chip, a north-south bridge chip, or the like. The first chip group 104 is a high power consumption chip, which is connected to the interposer through solder balls. The heat sink is connected to the back of the first chip set 104 by an interfacial heat sink material (heat conductive material). The heat sink can also be connected with a liquid or air cooling device.
The method for fabricating an interposer in a package of the present invention may comprise the steps of: s1: adding a stripping glue to one side of the carrier plate; s2: preparing redistribution wires on the lift-off glue, comprising: sequentially forming a first seed conductive layer and a dielectric layer on the stripping glue, wherein the dielectric layer is provided with a circuit pattern; s3: filling electroplating materials into the gaps of the dielectric layer to form a conductive connecting layer; s4: repeating S2 and S3 for preparing a plurality of layers of redistribution traces to obtain a first portion 101 of the interposer; s5: forming a new seed conductive layer on the first portion 101, and coating a photoresist; s6: photoetching the light resistance to form a conducting channel; s7: electroplating the conducting channel to form a conducting metal column for leading out a chip pin; s8: removing the photoresist and etching to remove the redundant seed conducting layer; s9: pressing the etched conductive metal column by using an organic material for wrapping the conductive metal column to obtain a second part 102 of the intermediate layer; s10: and removing the carrier plate to form the intermediate layer.
The method for fabricating the interposer in the package of the present invention may further comprise the steps of: s1: adding a stripping glue to one side of the carrier plate; s2: preparing redistribution wires on the lift-off glue, comprising: sequentially forming a first seed conductive layer and a dielectric layer on the stripping glue, wherein the dielectric layer is provided with a circuit pattern; s3: filling electroplating materials into the gaps of the dielectric layer to form a conductive connecting layer; s4: repeating S2 and S3 for preparing a plurality of layers of redistribution traces to obtain a first portion 101 of the interposer; s5: vertically routing the redistribution wires on the periphery of the first part 101 to obtain a conductive metal column; s6: the conductive metal posts are compression molded with an organic material for encapsulating the conductive metal posts, resulting in the second portion 102 of the interposer, wherein the carrier is removed at any step after step S4 or step S6.
The manufacturing method of the intermediate layer utilizes the organic composite material to manufacture the intermediate layer, so that the design of the metal through hole is not limited by the punching technology; the organic composite material comprises more material types, so that the material which is relatively close to the thermal expansion coefficient of the chip is easy to find to reduce the stress of the chip; and the manufacturing method can utilize the panel manufacturing process, thereby greatly reducing the manufacturing cost.
The package based on an interposer proposed by the present invention comprises at least: a substrate 106, an interposer, a first chipset 104 and a second chipset 105, wherein the first chipset 104 and the second chipset 105 each comprise at least one chip; the interposer includes a first portion 101 and a second portion 102; the first chip group 104 is connected to one side of the first portion 101 by flip chip; the other side of the first part 101 and the second part 102 are stacked to define at least one space for accommodating the second chipset 105; one side of the space is a substrate 106, and the second chipset 105 is connected to the substrate 106 through a flip chip. The invention realizes the miniaturization and the large capacity of the chip packaging structure through the three-dimensional structure of the intermediate layer. The interposer organic composite material is not limited by the punching technology in the design of metal through holes, and the organic composite material comprises more material types, so that materials which are close to the thermal expansion coefficient of the chip can be easily found to reduce the stress of the chip.
Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, the embodiments of the present invention are not limited to the details of the above embodiments, and various simple modifications can be made to the technical solutions of the embodiments of the present invention within the technical idea of the embodiments of the present invention, and the simple modifications all belong to the protection scope of the embodiments of the present invention.
It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, the embodiments of the present invention do not describe every possible combination.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.
The above are merely examples of the present application and are not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (10)
1. An interposer-based package, comprising:
the chip comprises a substrate, an intermediate layer, a first chip set and a second chip set, wherein the first chip set and the second chip set respectively comprise at least one chip;
the interposer includes a first portion and a second portion;
the first chip group is connected to one side of the first part through a flip chip;
the other side of the first part and the second part are stacked to define at least one space for accommodating the second chipset;
one side of the space is a substrate, and the second chip set is connected to the substrate through an inverted installation;
the first part is a plate-shaped body, the second part comprises a plurality of columnar bodies, the columnar bodies are positioned on the periphery of one surface of the plate-shaped body, and the sum of the cross-sectional areas of the plurality of columnar bodies is smaller than the area of the surface of the plate-shaped body.
2. The package of claim 1, wherein the column is located at a periphery of one surface of the plate, comprising:
the columnar bodies are located at the peripheries of opposite sides of one surface of the plate-shaped body, or,
the columnar bodies are located at four corners of the periphery of one surface of the plate-shaped body, or,
the columnar body is located on the entire periphery of one surface of the plate-like body.
3. The package of claim 1,
the interposer is provided with a through hole, and a conductive metal column is arranged in the through hole and used for connecting multiple chips;
the size of the perforations is 20-100 microns.
4. The package of claim 3,
the perforation mode is at least one of mechanical perforation, laser perforation and photoetching and etching opening;
the perforated material is metal.
5. The package of claim 1,
a gap exists between the space and the second chipset, and the size of the gap is determined by the second chipset.
6. The package of claim 1,
the interposer has a thickness in the range of 100-400 microns, wherein,
the thickness of the first portion of the interposer ranges from: 100-200 microns;
the second portion of the interposer has a thickness in a range of: 100-200 microns.
7. The package of claim 1,
the interposer further comprises at least: redistribution wires disposed in at least one of the first portion and the second portion.
8. The package of claim 1,
the material of the intermediate layer is organic material, and the type of the organic material is at least one of molding material and resin with filler.
9. The package of claim 1,
the second chip group is a low-power chip.
10. The package of claim 1, further comprising a heat sink;
the radiating fins are arranged on at least one surface of the first chip group and used for radiating the first chip group.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211257968.3A CN115332187A (en) | 2022-10-14 | 2022-10-14 | Package based on interposer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211257968.3A CN115332187A (en) | 2022-10-14 | 2022-10-14 | Package based on interposer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115332187A true CN115332187A (en) | 2022-11-11 |
Family
ID=83913331
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211257968.3A Pending CN115332187A (en) | 2022-10-14 | 2022-10-14 | Package based on interposer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115332187A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116093044A (en) * | 2023-04-10 | 2023-05-09 | 北京华封集芯电子有限公司 | Multi-chip integration method and structure |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103117275A (en) * | 2013-01-31 | 2013-05-22 | 华为技术有限公司 | Chip packaging structure and chip packaging method |
| CN110349864A (en) * | 2019-07-24 | 2019-10-18 | 气派科技股份有限公司 | A kind of packaging method and chip package product of chip cooling piece |
| CN111524870A (en) * | 2019-02-05 | 2020-08-11 | 英飞凌科技股份有限公司 | Semiconductor device with radar semiconductor chip and associated production method |
| CN113257778A (en) * | 2021-07-06 | 2021-08-13 | 江苏长晶科技有限公司 | 3D stacked fan-out type packaging structure with back lead-out function and manufacturing method thereof |
| CN114256193A (en) * | 2020-09-25 | 2022-03-29 | 英特尔公司 | Singulation of microelectronic assemblies with direct bonding interfaces |
| CN114613756A (en) * | 2020-12-08 | 2022-06-10 | 三星电子株式会社 | Semiconductor device having stacked package structure and method of manufacturing semiconductor device |
-
2022
- 2022-10-14 CN CN202211257968.3A patent/CN115332187A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103117275A (en) * | 2013-01-31 | 2013-05-22 | 华为技术有限公司 | Chip packaging structure and chip packaging method |
| CN111524870A (en) * | 2019-02-05 | 2020-08-11 | 英飞凌科技股份有限公司 | Semiconductor device with radar semiconductor chip and associated production method |
| CN110349864A (en) * | 2019-07-24 | 2019-10-18 | 气派科技股份有限公司 | A kind of packaging method and chip package product of chip cooling piece |
| CN114256193A (en) * | 2020-09-25 | 2022-03-29 | 英特尔公司 | Singulation of microelectronic assemblies with direct bonding interfaces |
| CN114613756A (en) * | 2020-12-08 | 2022-06-10 | 三星电子株式会社 | Semiconductor device having stacked package structure and method of manufacturing semiconductor device |
| CN113257778A (en) * | 2021-07-06 | 2021-08-13 | 江苏长晶科技有限公司 | 3D stacked fan-out type packaging structure with back lead-out function and manufacturing method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116093044A (en) * | 2023-04-10 | 2023-05-09 | 北京华封集芯电子有限公司 | Multi-chip integration method and structure |
| CN116093044B (en) * | 2023-04-10 | 2023-09-01 | 北京华封集芯电子有限公司 | Multi-chip integration method and structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8729690B2 (en) | Assembly having stacked die mounted on substrate | |
| CN103077933B (en) | Three-dimensional chip integrates to wafer scale | |
| KR102239259B1 (en) | Stacked semiconductor die assembly with high efficiency thermal path and molded underfill | |
| US7750459B2 (en) | Integrated module for data processing system | |
| US7847415B2 (en) | Method for manufacturing a multichip module assembly | |
| CN104025285A (en) | Multi die package structures | |
| CN105895623B (en) | Substrate design and forming method thereof for semiconductor package part | |
| US20080099903A1 (en) | Stacked chip package, embedded chip package and fabricating method thereof | |
| CN115332187A (en) | Package based on interposer | |
| CN112928028A (en) | Board-level chip packaging method with embedded circuit and packaging structure thereof | |
| US11955401B2 (en) | Package structure | |
| CN115312406A (en) | Chip packaging structure and preparation method | |
| CN112820726B (en) | Chip packaging structure and preparation method thereof | |
| CN115332216A (en) | Interposer for chip packaging and chip packaging | |
| KR100851108B1 (en) | Wafer level system in package and fabrication method thereof | |
| CN116613154B (en) | 2.5D packaging structure for improving power signal transmission and preparation method thereof | |
| CN220233193U (en) | 2.5D packaging structure for improving power signal transmission | |
| CN115332214B (en) | Interposer for chip packaging and manufacturing method | |
| US20230238360A1 (en) | Semiconductor package assembly and electronic device | |
| US20220375822A1 (en) | Electronic package and method for manufacturing the same | |
| US20220208733A1 (en) | Chip Package and Method of Forming Chip Packages | |
| CN116705784A (en) | 2.5D packaging structure for improving power signal transmission and preparation method thereof | |
| CN116454038A (en) | Packaging method and packaging structure | |
| JP2024037144A (en) | Manufacturing method and semiconductor structure of high heat dissipation hybrid substrate | |
| CN115332226A (en) | Packaging structure based on ceramic intermediate layer and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20221111 |