CN115328830A - PCIe host-to-device interrupt sending method and system - Google Patents

PCIe host-to-device interrupt sending method and system Download PDF

Info

Publication number
CN115328830A
CN115328830A CN202211268879.9A CN202211268879A CN115328830A CN 115328830 A CN115328830 A CN 115328830A CN 202211268879 A CN202211268879 A CN 202211268879A CN 115328830 A CN115328830 A CN 115328830A
Authority
CN
China
Prior art keywords
interrupt
pcie
transaction layer
host
pcie host
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202211268879.9A
Other languages
Chinese (zh)
Inventor
王少虎
郑德金
耿平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nanjing Semidrive Technology Co Ltd
Original Assignee
Nanjing Semidrive Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanjing Semidrive Technology Co Ltd filed Critical Nanjing Semidrive Technology Co Ltd
Priority to CN202211268879.9A priority Critical patent/CN115328830A/en
Publication of CN115328830A publication Critical patent/CN115328830A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/24—Interrupt
    • G06F2213/2424—Interrupt packet, e.g. event

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Small-Scale Networks (AREA)
  • Bus Control (AREA)

Abstract

A PCIe host-to-device interrupt sending method, comprising: receiving an interrupt transaction layer data packet by the PCIe device; judging whether the interrupt transaction layer data packet is matched with a reserved address space in a base address register or not; if the interrupt transaction layer data packet is matched with the reserved address space in the base address register, transmitting PCIe host interrupt request confirmation information to an interrupt generation module of PCIe equipment; an interrupt generating module of the PCIe equipment generates a general interrupt request message of the PCIe equipment according to the interrupt request confirmation information of the PCIe host and sends the general interrupt request message to an interrupt controller; an interrupt handling response procedure of the PCIe host is executed. The invention also provides an interrupt sending system from the PCIe host to the equipment, which realizes the mechanism that the PCIe host sends the interrupt to the equipment.

Description

PCIe host-to-device interrupt sending method and system
Technical Field
The present application relates to the field of integrated circuit technologies, and in particular, to a method and a system for sending an interrupt from a PCIe host to a device.
Background
The PCIe bus has become the most important interconnect bus protocol in the fields of consumer, server, and industrial applications by virtue of its low cost, low latency, simple structure, and easy expansion. Interrupt mechanisms are often used between multiple cores in a heterogeneous system as synchronization signals on both sides, so that the flow and calculation of data are controlled. PCIe introduces an MSI interruption mechanism, and an MSI transaction packet is also a special Memory write data packet, so that the characteristic of Memory consistency of a PCIe protocol is fully utilized, and the transmission sequence (Order) between an interruption transaction part and a common data packet is ensured. In the PCIe architecture system, a tree structure with an RC (host) as a center is used, so in the protocol formulation, only a mechanism for an EP (device side) to send an interrupt to the RC (host) side is provided.
Disclosure of Invention
In order to solve the defects of the prior art, the present application aims to provide an interrupt sending method and system from a PCIe host to a device, where when an interrupt transaction layer packet sent by the PCIe host is received, an interrupt is directly generated to an interrupt controller, so as to implement interrupt sending from the PCIe host to the device.
In order to achieve the above object, the PCIe host-to-device interrupt sending method provided in the present application includes:
receiving an interrupt transaction layer data packet by the PCIe device;
judging whether the interrupt transaction layer data packet is matched with a reserved address space in a base address register or not;
if the interrupt transaction layer data packet is matched with the reserved address space in the base address register, transmitting PCIe host interrupt request confirmation information to an interrupt generation module of PCIe equipment;
an interrupt generating module of the PCIe equipment generates a general interrupt request message of the PCIe equipment according to the interrupt request confirmation information of the PCIe host and sends the general interrupt request message to an interrupt controller;
an interrupt handling response procedure of the PCIe host is executed.
Further, the step of determining whether the interrupt transaction layer packet matches the reserved address space in the base address register further includes:
judging whether the address bit in the interrupt transaction layer data packet is matched with the reserved address space of the base address register;
analyzing data bits in the data packet of the interrupt transaction layer into MSI vector numbers;
and judging whether the length in the interrupt transaction layer data packet is 1.
Further, the base address register is a BAR0 register of the PCIe device.
Further, the determining whether the address bit in the interrupt transaction layer packet matches the reserved address space of the base address register further includes: and judging that the address field of the address bit in the interrupt transaction layer data packet is matched with the length of the reserved address space of the BAR0 register.
Further, the PCIe device, including but not limited to 16 functions, each function supports 64 MSI vectors.
To achieve the above object, the present application also provides a PCIe host-to-device interrupt sending system, including,
the PCIe host is used for sending an interrupt transaction layer data packet to the PCIe equipment;
and the PCIe equipment is used for matching the interrupt transaction layer data packet with the base address register, and directly entering a PCIe host interrupt processing response program when judging that the interrupt transaction layer data packet is the MSI interrupt sent by the PCIe host.
Further, the PCIe device includes:
the interrupt detection module is used for matching an interrupt transaction layer data packet with a base address register;
the base address register is used for providing a reserved address space for matching the interrupt transaction layer data packet;
the interrupt generation module is used for generating a universal interrupt request of PCIe equipment;
and the interrupt controller is used for controlling the CPU to execute the interrupt processing response program.
Further, the base address register is a BAR0 register of the PCIe device;
and the interrupt detection module is used for sending PCIe host interrupt request confirmation information to the interrupt generation module when confirming that the address field 63 of the address bit in the interrupt transaction layer data packet matches with the length of the reserved address space of the BAR0 register.
Further, the interrupt generation module generates a general interrupt request of PCIe devices and sends the general interrupt request to the interrupt controller control CPU to execute a PCIe host interrupt processing response program after receiving the PCIe host interrupt request acknowledgement information sent by the interrupt detection module.
To achieve the above object, the present application also provides a system chip including the PCIe host-to-device interrupt sending system described above.
To achieve the above object, the present application also provides an electronic device, including a memory and a processor, where the memory stores computer instructions, and the processor is configured to execute the instructions to execute the steps of the PCIe host-to-device interrupt sending method described above.
To achieve the above object, the present application also provides a computer readable storage medium having stored thereon computer instructions which, when executed, perform the steps of the PCIe host-to-device interrupt sending method described above.
Compared with the prior art, the interrupt sending method and system from the PCIe host to the equipment have the following technical effects:
after the PCIe equipment determines to receive the interrupt transaction layer transaction packet of the PCIe host, the PCIe equipment generates a general interrupt request and directly enters an interrupt processing response program of the PCIe host to the interrupt controller, and an interrupt mechanism of the PCIe host to send an interrupt to the PCIe equipment is realized.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application.
Drawings
The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
FIG. 1 is a flow diagram of a PCIe host-to-device interrupt sending method according to the present application;
FIG. 2 is a schematic diagram of a PCIe host-to-device interrupt delivery system architecture according to the present application;
FIG. 3 is a schematic diagram of an interrupt transaction layer packet (MSI TLP) structure according to the present application;
fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
Embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided for a more thorough and complete understanding of the present application. It should be understood that the drawings and embodiments of the present application are for illustration purposes only and are not intended to limit the scope of the present application.
It should be understood that the various steps recited in the method embodiments of the present application may be performed in a different order and/or in parallel. Moreover, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the present application is not limited in this respect.
The term "include" and variations thereof as used herein are open-ended, i.e., "including but not limited to". The term "based on" is "based, at least in part, on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Relevant definitions for other terms will be given in the following description.
It is noted that references to "a" or "an" modification in this application are intended to be illustrative rather than limiting, and those skilled in the art will appreciate that references to "one or more" are intended to be exemplary unless the context clearly indicates otherwise. "plurality" is to be understood as two or more.
In an embodiment of the present application, a PCIe host-to-device interrupt sending method includes: the PCIe device receives an interrupt transaction layer data packet; judging whether the interrupt transaction layer data packet is matched with a reserved address space in a base address register or not; if the interrupt transaction layer data packet is matched with the reserved address space in the base address register, transmitting PCIe host interrupt request confirmation information to an interrupt generation module; the interrupt generation module generates a general interrupt request according to the interrupt request confirmation information and sends the general interrupt request to an interrupt controller; an interrupt handling response procedure of the PCIe host is executed.
Data transmission between the PCIe host and the equipment or between the PCIe equipment and the equipment is performed in a Packet form from a transaction layer at a sending end to a transaction layer at a receiving end. Based on the type, destination address and other related attributes of the upper Layer (software Layer or application Layer) Request (Request), the requests are packed to generate a TLP (Transaction Layer Packet). These TLPs then go down through the data link layer, the physical layer, and finally reach the destination device.
The TLP is composed of three parts, header, data, and CRC (optional). TLPs are Transaction layers that start at the sender and end at the receiver. Each TLP has a Header, as in humans, which terminates life without a head, so that TLPs can be used without hands and feet, but never without a head. And the transaction layer generates a TLP Header according to the request content of the upper layer. Header content includes information about the sender, the destination address (to whom the TLP is intended), the TLP type (such as Memory Read, memory Write, as mentioned earlier), the data length (if any), and the like.
Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings.
Example 1
Fig. 1 is a flowchart of a PCIe host-to-device interrupt sending method according to the present application, and the PCIe host-to-device interrupt sending method according to the present application will be described in detail below with reference to fig. 1.
First, in step 101, the PCIe device receives an interrupt transaction layer packet sent by the PCIe host.
In this embodiment of the application, the interrupt Transaction Layer Packet (TLP) sent by the PCIe host is a Memory Write Packet (Memory Write Packet), and may also be referred to as a post TLP (TLP not requiring reply)
At step 102, the interrupt transaction layer packet is matched to the base address register.
In the embodiment of the application, the PCIe device detects the received interrupt transaction layer packet, and determines whether the interrupt is an MSI interrupt sent by the PCIe host.
In the embodiment of the application, the PCIe device matches the received interrupt transaction layer Packet with the reserved address Space in the base address register BAR0 Space, and if the interrupt transaction layer Packet is matched with the last address Space (special reserved address, size is customizable) in the base address register BAR0 Space, the received Packet is considered as the MSI interrupt sent by the PCIe host.
In the embodiment of the present application, the logic for detecting the MSI interrupt by the PCIe device is as follows:
the Address bit Address Field (addresses [ 63;
the Data bit Data Field (DATA [5 ] in Packet is analyzed as MSI vector number;
the Length in Packet must be 1.
In the embodiment of the present application, the PCIe device has 16 functions (functions), and each Function supports 64 MSI vectors).
At step 103, a generic interrupt request is generated and sent to the interrupt controller.
In the embodiment of the application, when the PCIe device judges that the received interrupt transaction layer packet is MSI interrupt sent by the PCIe host, a general interrupt request of the PCIe device is directly generated and sent to the interrupt controller.
At step 104, an interrupt handling response routine is executed.
In the embodiment of the application, the interrupt controller controls the CPU to directly execute the interrupt processing response program of the PCIe host according to the general interrupt request.
In the embodiment of the application, hardware parsing logic is added into a PCIe device controller, a special space Memory Write sent to a device BAR0 space is detected, and a detected interrupt signal is directly notified to an interrupt controller (such as PIC, GIC) module in a hard connection mode. Software can distinguish whether an interrupt source is an external PCIe host or an internal module of a device SoC without inquiring an internal state register of the interrupt controller, and the interrupt generation mode is more efficient and low in delay.
The application only relates to the access of a PCIe device Controller, thereby avoiding the access authority of opening an internal security-related module (such as a PIC-Programmable Interrupt Controller) and an internal bus (to PIC) on a host side, and being safer and more reliable.
The method can support the implementation of a plurality of MSI interrupt vectors, the number of the MSI interrupt vectors is almost unlimited (such as 2 x 16), and the number of the MSI interrupt vectors is flexible and configurable.
Example 2
Fig. 2 is a schematic structural diagram of a PCIe host-to-device interrupt sending system according to the present application, and as shown in fig. 2, the PCIe host-to-device interrupt sending system of the present application includes,
a PCIe host 10 for sending an interrupt transaction layer packet to the PCIe device 20.
In the embodiment of the present application, the interrupt transaction layer packet sent by the PCIe host is a packet that does not require to reply to the memory write data packet.
The PCIe device 20 is configured to detect the received interrupt transaction layer packet, generate a general interrupt request of the PCIe device when it is determined that the received interrupt transaction layer packet is the interrupt transaction layer packet sent by the PCIe host 10, and directly execute a PCIe host interrupt processing response program.
In this embodiment, the PCIe device 20 includes:
the interrupt detection module 21 is configured to detect a received interrupt transaction layer packet, and determine whether the packet is an MSI interrupt sent by the PCIe host.
In this embodiment of the present application, the interrupt detection module 21 matches the received interrupt transaction layer Packet with the reserved address Space in the base address register BAR0 Space, and if the interrupt transaction layer Packet matches the last address Space (the special reserved address, the size of which can be customized) in the base address register BAR0 Space, it is considered that the received Packet is the MSI interrupt sent by the PCIe host, and sends PCIe host interrupt request confirmation information to the interrupt generation module 23.
The logic to detect the MSI interrupt is as follows:
address Field in Packet (addresses [63 ];
the Data bit Data Field (DATA [5 ] 0) in the Packet is analyzed as MSI vector number;
the Length in Packet must be 1.
In the embodiment of the present application, the PCIe device includes, but is not limited to, 16 functions (functions), each Function supporting 64 MSI vectors), as shown in fig. 3.
And the base address register 22 is used for providing a reserved address space for matching the interrupt transaction layer data packet.
In this embodiment, the base address register 22 is a BAR0 register of the PCIe device, and the reserved address space is a last address space (a special reserved address, which may be self-defined in size).
The interrupt generating module 23 is configured to generate a general interrupt request of the PCIe device.
In this embodiment of the application, the interrupt generating module 23 generates a general interrupt request of the PCIe device and sends the general interrupt request to the interrupt controller 24 when receiving the PCIe host interrupt request acknowledgement information sent by the interrupt detecting module 21.
In this embodiment, the interrupt generating module 23 further forwards the received interrupt request of the internal module of the PCIe device sent by the general interrupt module 25 to the interrupt controller 24.
And an interrupt controller 24 for controlling the CPU to execute the interrupt processing response program.
In the embodiment of the present application, after receiving the general interrupt request sent by the interrupt generation module 23, the interrupt controller 24 controls the CPU26 to directly execute the interrupt processing response program.
In the embodiment of the present application, the general interrupt request includes an interrupt and an interrupt vector number.
A system for PCIe host-to-device interrupt delivery adds interrupt resolution hardware logic in the PCIe device and directly generates interrupts to an interrupt controller. After receiving the corresponding interrupt and the interrupt vector number, the software directly enters an interrupt processing response program of the PCIe host.
The PCIe host only needs to have access to the BAR0 space within the controller of the PCIe device. The PCIe device SoC avoids developing an internal core bus and a core security module, and avoids potential security threats.
Implementation of multiple MSI interrupt vectors can be supported and there is little restriction on the number of MSI interrupt vectors (e.g., 65536). The number of MSI interrupt vectors is flexible and configurable.
Example 3
In an embodiment of the present application, a system chip is further provided, where the system chip includes an interrupt sending system from a PCIe host to a device in the foregoing embodiment, and an interrupt sending mechanism from the PCIe host to the device is implemented.
Example 4
In an embodiment of the present application, there is further provided an electronic device, and fig. 4 is a schematic structural diagram of the electronic device according to an embodiment of the present application, as shown in fig. 4, the electronic device of the present application includes a processor 401 and a memory 402, where,
the processor 401 employs the onboard chip of the above-described embodiment.
The memory 402 stores a computer program that, when read and executed by the processor 401, performs the steps in the PCIe host-to-device interrupt sending method embodiment as described above.
Example 5
In an embodiment of the present application, there is further provided a computer-readable storage medium having stored therein a computer program, wherein the computer program is configured to, when executed, perform the steps in the PCIe host-to-device interrupt sending method embodiment as described above.
It should be noted that the storage medium (computer-readable medium) described above in the present application may be a computer-readable signal medium or a non-transitory computer-readable storage medium or any combination of the two. The non-transitory computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the above. More specific examples of the non-transitory computer readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
In embodiments of the application, a non-transitory computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In this application, however, a computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a non-transitory computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: electrical wires, optical cables, RF (radio frequency), etc., or any suitable combination of the foregoing.
The computer readable medium may be embodied in the electronic device; or may exist separately without being assembled into the electronic device.
Computer program code for carrying out operations for aspects of the present application may be written in any combination of one or more programming languages, including but not limited to an object oriented programming language such as Java, smalltalk, C + +, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server.
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The units described in the embodiments of the present application may be implemented by software or hardware. Where the name of an element does not in some cases constitute a limitation on the element itself.
The functions described herein above may be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), system on a chip (Soc), complex Programmable Logic Devices (CPLDs), and the like.
Further, while operations are depicted in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order. Under certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while several specific implementation details are included in the above discussion, these should not be construed as limitations on the scope of this application. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination.
Those of ordinary skill in the art will understand that: although the present application has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described in the foregoing embodiments, or equivalents may be substituted for elements thereof. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims (12)

1. A PCIe host-to-device interrupt sending method, comprising:
the PCIe device receives an interrupt transaction layer data packet;
judging whether the interrupt transaction layer data packet is matched with a reserved address space in a base address register or not;
if the interrupt transaction layer data packet is matched with the reserved address space in the base address register, transmitting PCIe host interrupt request confirmation information to an interrupt generation module of PCIe equipment;
an interrupt generating module of the PCIe equipment generates a general interrupt request message of the PCIe equipment according to the interrupt request confirmation information of the PCIe host and sends the general interrupt request message to an interrupt controller;
an interrupt handling response procedure of the PCIe host is executed.
2. The PCIe host-to-device interrupt sending method of claim 1, wherein the step of determining whether the interrupt transaction layer packet matches a reserved address space in a base address register further comprises:
judging whether the address bit in the interrupt transaction layer data packet is matched with the reserved address space of the base address register;
analyzing data bits in the interrupt transaction layer data packet into MSI vector numbers;
and judging whether the length in the interrupt transaction layer data packet is 1.
3. The PCIe host-to-device interrupt sending method of claim 2, wherein the base address register is a BAR0 register of a PCIe device.
4. The method of claim 3, wherein the determining whether the address bits in the interrupt transaction layer packet match the reserved address space of the base address register further comprises: and judging that the address field of the address bit in the interrupt transaction layer data packet is matched with the length of the reserved address space of the BAR0 register.
5. The PCIe host-to-device interrupt sending method of claim 1, wherein the PCIe device, including but not limited to 16 functions, each function supports 64 MSI vectors.
6. A PCIe host-to-device interrupt forwarding system, comprising:
the PCIe host is used for sending an interrupt transaction layer data packet to the PCIe equipment;
and the PCIe equipment is used for matching the interrupt transaction layer data packet with the base address register, and directly entering a PCIe host interrupt processing response program when judging that the interrupt transaction layer data packet is the MSI interrupt sent by the PCIe host.
7. The PCIe host-to-device interrupt sending system of claim 6, wherein the PCIe device comprises:
the interrupt detection module is used for matching an interrupt transaction layer data packet with a base address register;
the base address register is used for providing a reserved address space for matching the interrupt transaction layer data packet;
the interrupt generating module is used for generating a universal interrupt request of PCIe equipment;
and the interrupt controller is used for controlling the CPU to execute the interrupt processing response program.
8. The PCIe host-to-device interrupt Transmit System of claim 7,
the base address register is a BAR0 register of PCIe equipment;
and the interrupt detection module is used for sending PCIe host interrupt request confirmation information to the interrupt generation module when confirming that the address field 63 of the address bit in the interrupt transaction layer data packet matches with the length of the reserved address space of the BAR0 register.
9. The PCIe host-to-device interrupt Transmit System of claim 8,
and the interrupt generation module generates a general interrupt request of PCIe equipment and sends the general interrupt request to the interrupt controller to control the CPU to execute a PCIe host interrupt processing response program after receiving the PCIe host interrupt request confirmation information sent by the interrupt detection module.
10. A system chip comprising the PCIe host-to-device interrupt sending system of any one of claims 6 to 9.
11. An electronic device comprising a memory and a processor, wherein the memory has stored therein computer instructions, the processor being configured to execute the instructions to perform the steps of the PCIe host-to-device interrupt sending method of any one of claims 1-5.
12. A computer readable storage medium having stored thereon computer instructions which, when executed, perform the steps of the PCIe host-to-device interrupt transmit method as recited in any one of claims 1 to 5.
CN202211268879.9A 2022-10-17 2022-10-17 PCIe host-to-device interrupt sending method and system Pending CN115328830A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211268879.9A CN115328830A (en) 2022-10-17 2022-10-17 PCIe host-to-device interrupt sending method and system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211268879.9A CN115328830A (en) 2022-10-17 2022-10-17 PCIe host-to-device interrupt sending method and system

Publications (1)

Publication Number Publication Date
CN115328830A true CN115328830A (en) 2022-11-11

Family

ID=83915317

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211268879.9A Pending CN115328830A (en) 2022-10-17 2022-10-17 PCIe host-to-device interrupt sending method and system

Country Status (1)

Country Link
CN (1) CN115328830A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116301266A (en) * 2023-03-03 2023-06-23 无锡众星微***技术有限公司 PCIe (peripheral component interconnect express) equipment in-band resetting method and device based on security authentication

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110399324A (en) * 2019-06-28 2019-11-01 苏州浪潮智能科技有限公司 It interrupts converter and interrupts conversion method
CN114185705A (en) * 2022-02-17 2022-03-15 南京芯驰半导体科技有限公司 Multi-core heterogeneous synchronization system and method based on PCIe

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110399324A (en) * 2019-06-28 2019-11-01 苏州浪潮智能科技有限公司 It interrupts converter and interrupts conversion method
CN114185705A (en) * 2022-02-17 2022-03-15 南京芯驰半导体科技有限公司 Multi-core heterogeneous synchronization system and method based on PCIe

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116301266A (en) * 2023-03-03 2023-06-23 无锡众星微***技术有限公司 PCIe (peripheral component interconnect express) equipment in-band resetting method and device based on security authentication
CN116301266B (en) * 2023-03-03 2023-11-17 无锡众星微***技术有限公司 PCIe (peripheral component interconnect express) equipment in-band resetting method and device based on security authentication

Similar Documents

Publication Publication Date Title
KR100666515B1 (en) Store and forward switch device, system and method
US5978865A (en) System for performing DMA transfers where an interrupt request signal is generated based on the value of the last of a plurality of data bits transmitted
US20110055439A1 (en) Bus bridge from processor local bus to advanced extensible interface
US5958024A (en) System having a receive data register for storing at least nine data bits of frame and status bits indicating the status of asynchronous serial receiver
US9525734B2 (en) Hybrid remote direct memory access
KR20200102951A (en) Extended mode (xm) bus mode change, configuration register accesses and broadcast / multi-cast transactions to devices on a xm bus
CN111930676A (en) Method, device, system and storage medium for communication among multiple processors
JP2003132037A (en) System and method for low overhead message passing between domains in partitioned server
CN115328830A (en) PCIe host-to-device interrupt sending method and system
US7058743B2 (en) Method and device for dynamic interrupt target selection
JP2022123826A (en) Data processor and data processing system
US8521943B2 (en) Data transmission system and method of reading data
EP0525736B1 (en) Data storing system for a communication control circuit
US10949095B2 (en) Method, network adapters and computer program product using network adapter memory to service data requests
US20040039835A1 (en) Method and apparatus for transferring general purpose control information between processors
JP2015216450A (en) Information processing apparatus, information processing system and relay program
CN114443525A (en) Data processing system, method, electronic equipment and storage medium
CN113157510B (en) Method and device for testing transaction ordering rule of expansion bus of high-speed serial computer
CN117170704B (en) Remote upgrading method and device based on hardware IIC
US7073007B1 (en) Interrupt efficiency across expansion busses
JP2018164235A (en) Communication terminal and communication control method
JP2005275452A (en) Data transfer control system
WO2020196958A1 (en) Efficient transmission restoration method and system according to network state conversion
CN112825529A (en) Method, system, equipment and storage medium for data transmission of edge computing node
JP2016085495A (en) Test support method and test support device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20221111

RJ01 Rejection of invention patent application after publication