CN115328264A

CN115328264A - Amplifying circuit, linear voltage stabilizing circuit and electronic device

Info

Publication number: CN115328264A
Application number: CN202110509967.2A
Authority: CN
Inventors: 杜宇; 邵力
Original assignee: Zhaoyi Innovation Technology Group Co ltd; Xi'an Geyi Anchuang Integrated Circuit Co ltd
Current assignee: Zhaoyi Innovation Technology Group Co ltd; Xi'an Geyi Anchuang Integrated Circuit Co ltd
Priority date: 2021-05-11
Filing date: 2021-05-11
Publication date: 2022-11-11

Abstract

The invention discloses an amplifying circuit, a linear voltage stabilizing circuit and an electronic device. The invention relates to a linear voltage stabilizing circuit, wherein an error amplifier of the linear voltage stabilizing circuit comprises a first biasing unit and a second biasing unit. In the starting stage of the linear voltage stabilizing circuit, the first bias unit and the second bias unit jointly provide bias current for two input geminate transistors of the error amplification module, so that the response adjustment speed of the error amplification module is increased; when the output voltage of the linear voltage stabilizing circuit is adjusted to be close to the target value, the second bias unit is controlled to stop providing the bias current, and the power consumption of the linear voltage stabilizing circuit during normal operation is further reduced.

Description

Amplifying circuit, linear voltage stabilizing circuit and electronic device

Technical Field

The invention relates to the technical field of electronic circuits, in particular to an amplifying circuit, a linear voltage stabilizing circuit and an electronic device, wherein the amplifying circuit can improve the target voltage establishing speed and save power consumption.

Background

With the development and progress of consumer electronics, higher requirements are also put on electronic systems. In an electronic system, power supply from a peripheral power supply to the inside of a chip needs to realize voltage reduction or enhance the stability of the power supply through relevant modules inside the chip. The Low Dropout linear Regulator (LDO) has the advantages of small area, low power consumption, simple scheme, and the like, and is widely applied to electronic systems. The LDO is essentially characterized in that a stable voltage generated by a band gap reference and a negative feedback control loop are utilized to obtain an output voltage which basically does not change along with the environment, and meanwhile, the LDO can provide larger loading capacity.

With the increasing complexity of the on-chip circuit, the power supply voltage is gradually reduced, and the performance requirement of the linear voltage stabilizing circuit is continuously improved. In an actual LDO circuit design, since a long time is required for the bias voltage to build up, the response speed of the error amplifier is affected, which results in a long time required for the output voltage to stabilize to the target value, and the speed of building up the LDO is affected. Performance-based considerations the error amplifier typically requires a large bias current, which results in large power consumption of the LDO itself.

Disclosure of Invention

The present invention is directed to an amplifying circuit, a linear voltage regulator circuit, and an electronic device, which can increase the speed of establishing a target voltage of the linear voltage regulator circuit and reduce power consumption.

To achieve the above object, the present invention provides an amplifying circuit. The amplifying circuit includes: the device comprises a first input pipe, a second input pipe, a first biasing unit and a second biasing unit. The first bias unit and the second bias unit jointly provide bias current for the first input tube and the second input tube at a first time, the second bias unit stops providing the bias current at a second time, and the first bias unit continues to provide the bias current for the first input tube and the second input tube.

In some embodiments, the first bias unit comprises a current source.

To achieve the above objective, the present invention provides a linear voltage regulator circuit. The linear voltage stabilizing circuit comprises: the device comprises an adjusting tube, a feedback unit, an error amplification module and a second bias unit. The error amplification module comprises a first input tube, a second input tube and a first bias unit. In a starting stage of the linear voltage stabilizing circuit, the first bias unit and the second bias unit jointly provide bias current for the first input tube and the second input tube, and the second bias unit stops providing the bias current when the output voltage of the linear voltage stabilizing circuit is established to a target value.

In some embodiments, the first bias unit is a current source.

In some embodiments, the second bias unit includes a transistor for generating a bias current; in the starting stage of the linear voltage stabilizing circuit, the grid electrode of the transistor receives a second bias voltage to generate a bias current; the transistor is turned off when the output voltage builds to a target value.

In some embodiments, the second bias unit comprises: transistor, electric capacity, first switch and second switch. The transistor is used for generating a bias current. The capacitor and the second switch are connected in parallel at the grid and the source of the transistor. The first switch is disposed between a gate of the transistor and a power supply voltage terminal. Before the starting stage of the linear voltage stabilizing circuit, the first switch is switched on, the second switch is switched off, and the capacitor is charged; in the starting stage of the linear voltage stabilizing circuit, the first switch is switched off, and the second switch is switched off; when the output voltage is established to a target value, the first switch is turned off, and the second switch is turned on.

In some embodiments, during a startup phase of the linear voltage regulation circuit, the transistor operates in a saturation region.

In some embodiments, the second bias unit comprises: the current source, the current mirror, the third switch and the fourth switch; an input terminal of the current mirror receives the current provided by the current source via the third switch; the fourth switch is arranged between the grid electrode of the output tube of the current mirror and the public voltage end. In the starting stage of the linear voltage stabilizing circuit, the third switch is turned on, and the fourth switch is turned off; when the output voltage is established to a target value, the third switch is switched off, and the fourth switch is switched on.

To achieve the above object, the present invention provides an electronic device including the linear voltage regulator circuit.

In some embodiments, the electronic device is a non-volatile memory.

The error amplifier of the linear voltage stabilizing circuit adopts the first bias unit and the second bias unit as the bias. In the starting stage of the linear voltage stabilizing circuit, the first bias unit and the second bias unit jointly provide bias current for the two input tubes of the error amplification module, so that the response adjustment speed of the error amplification module is improved; when the output voltage of the linear voltage stabilizing circuit is adjusted to be close to the target value, the second biasing unit is controlled to stop providing the biasing current, and the power consumption of the linear voltage stabilizing circuit during normal operation is further reduced.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a circuit diagram of a conventional amplifier;

FIG. 2 is a circuit diagram of an amplifying circuit according to an embodiment of the present invention;

FIG. 3 is a circuit diagram of an amplifying circuit according to another embodiment of the present invention;

FIG. 4 is a circuit diagram of a linear voltage regulating circuit according to an embodiment of the present invention;

FIG. 5 is a timing diagram of the linear voltage regulator circuit of FIG. 4;

FIG. 6 is a circuit diagram of a second biasing unit according to another embodiment of the present invention;

FIG. 7 is a circuit diagram of a second biasing unit according to another embodiment of the present invention;

FIG. 8 is a block diagram of an electronic device according to the present invention.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar components or components having the same or similar functions throughout. The terms "first," "second," "third," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the objects so described are interchangeable under appropriate circumstances. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover a non-exclusive inclusion.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "connected" and "connected" are to be interpreted broadly, e.g., electrically connected or capable of communicating with each other; they may be directly connected or indirectly connected through intervening media, or may be connected through the use of two elements or the interaction of two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

Fig. 1 is a circuit diagram of a conventional amplifier. The existing amplifier generally includes a pair of input transistors MN1 and MN2, and a current source 11. Current source 11 provides bias current to input pair transistors MN1 and MN 2. An exemplary current source 11 includes a transistor MN3 and a transistor MN4, the gate and drain of the transistor MN3 are both connected to a bias voltage Vbias, the gate of the transistor MN4 is connected to the gate of the transistor MN3, and the bias voltage Vbias causes the transistor MN4 to operate in a saturation region. The response speed of the amplifier depends on the magnitude of the bias current and the speed of the current source setup. If the bias current is too small or the settling time of the bias voltage Vbias is long, the response speed of the amplifier is low. If the bias current is increased, the power consumption of the amplifying circuit is increased.

Fig. 2 is a circuit diagram of an amplifying circuit according to an embodiment of the invention. As shown in fig. 2, the amplifying circuit 10 of the present embodiment includes: a first input pipe MN1, a second input pipe MN2, a first biasing unit 11, and a second biasing unit 12. At a first time, the first bias unit 11 and the second bias unit 12 jointly provide bias current for the first input tube MN1 and the second input tube MN 2; at a second time, the second biasing unit 12 stops providing the bias current, and the first biasing unit 11 continues to provide the bias current for the first input tube MN1 and the second input tube MN 2. In some embodiments, the first bias unit 11 is, for example, a current source, and the first time is a setup time of the current source. The set-up time of the current source is the time after the current source is powered on until the rated current is stably supplied. At the setup time of the first bias unit 11, the first bias unit 11 and the second bias unit 12 together provide a bias current for the first input tube MN1 and the second input tube MN 2. After the first bias unit 11 can stably supply the rated current, the second bias unit 12 stops supplying the bias current, and the first bias unit 11 continues supplying the bias current. The first bias unit 11 is, for example, a main bias unit, and the second bias unit 12 is, for example, an auxiliary bias unit.

Specifically, the first input tube MN1 and the second input tube MN2 of the amplifying circuit 10 are differential input pair tubes. The gate of the first input tube MN1 and the gate of the second input tube MN2 receive a differential input voltage. Alternatively, as shown in fig. 2, the gate of the first input tube MN1 receives the input voltage Vin, the gate of the second input tube M2 receives the reference voltage Vref, and the amplifying circuit 10 serves as a comparator. In this embodiment, the first input tube MN1 and the second input tube MN2 both use NMOS tubes. The gate of the first input tube MN1 receives an input voltage Vin, the drain thereof is electrically connected to the node Q1, and the source thereof is electrically connected to the node Q2. The gate of the second input transistor MN2 receives a reference voltage Vref, the drain thereof is electrically connected to an output node Q3, and the source thereof is electrically connected to the node Q2. The first bias unit 11 and the second bias unit 12 are connected in parallel between a node Q2 and a common voltage terminal VSS.

In this embodiment, the amplifying circuit 10 further includes a current mirror 13, and the current mirror 13 is used for copying the current of the first input tube MN 1. When the current of the first input tube MN1 is larger than the current of the second input tube MN2, the output node Q3 is at a high level; when the current of the first input tube MN1 is smaller than the current of the second input tube MN2, the output node Q3 is at a low level. Specifically, in the present embodiment, the current mirror 13 includes a first PMOS transistor MP1 and a second PMOS transistor MP2. The gate and the drain of the first PMOS transistor MP1 are electrically connected to the node Q1, and the source thereof is electrically connected to the power voltage terminal VCC. The gate of the second PMOS transistor MP2 is electrically connected to the node Q1, the source thereof is electrically connected to the power voltage terminal VCC, and the drain thereof is electrically connected to the output node Q3.

In the present embodiment, the first bias unit 11 includes a first current source; the first current source receives a bias voltage Vbias and generates a bias current supplied to the first input tube MN1 and the second input tube MN 2. In this embodiment, the first current source includes a transistor MN3 and a transistor MN4. Specifically, the transistors MN3 and MN4 both use NMOS transistors. The gate and the drain of the transistor MN3 are connected to the supply terminal of the bias voltage Vbias, and the source of the transistor MN3 is electrically connected to the common voltage terminal VSS. A gate of the transistor MN4 is electrically connected to the gate of the transistor MN3, a source of the transistor MN4 is electrically connected to the common voltage terminal VSS, and a drain of the transistor MN4 is electrically connected to the node Q2. The bias voltage Vbias operates the transistor MN4 in a saturation region to generate a bias current. Optionally, a resistor is further disposed between the drain of the transistor MN3 and the supply terminal of the bias voltage Vbias. It should be noted that, in other embodiments, the first bias unit 11 may include a current source and a current mirror, and the current mirror mirrors the current generated by the current source to the node Q2.

In some embodiments, the second bias unit 12 employs a current source configured to stably supply a rated current before the first time, i.e., the second bias unit 12 is already established before the first time. The second bias unit 12 provides a bias current to the first input tube MN1 and the second input tube MN2 at a first time, and stops providing the bias current at a second time. The control signal for the current source of the second biasing unit 12 may be provided by a controller.

In some embodiments, the second biasing unit 12 includes a transistor disposed between the node Q2 and the common voltage terminal VSS, a gate of the transistor receiving the control signal. Under the action of the control signal, the transistor works in a saturation region at the first time to provide bias current for the first input tube MN1 and the second input tube MN2, and the transistor is cut off at the second time.

Fig. 3 is a circuit diagram of an amplifying circuit according to another embodiment of the invention. In the embodiment shown in fig. 3, the second biasing unit 12 includes a transistor MN5 disposed between the node Q2 and the common voltage terminal VSS. The transistor MN5 is, for example, an NMOS, and the drain of the transistor MN5 is connected to the node Q2. The second biasing unit 12 further includes: a capacitor C, a switch SW1 and a switch SW2. The capacitor C and the switch SW2 are connected in parallel between the gate and the source of the transistor MN5. The switch SW1 is provided between the gate of the transistor MN5 and the power supply voltage terminal VCC. Before the first time, the switch SW1 is turned on, the switch SW2 is turned off, the capacitor C is charged, and the potential of the gate of the transistor MN5 rises. By controlling the time when the switch SW1 is turned on, the potential of the gate of the transistor MN5 can be controlled to rise to a predetermined potential. For example, the potential of the gate of the transistor MN5 can be controlled to the power supply voltage VCC. In a first time, the first bias unit 11 starts to operate and supplies current, the switch SW1 and the switch SW2 are both turned off, and the capacitor C maintains the gate and the source of the transistor MN5 at a predetermined voltage difference. At the second time, the switch SW1 is turned off, the switch SW2 is turned on, the capacitor C is discharged, the transistor MN5 is turned off, and the first bias unit 11 alone provides bias current for the first input tube MN1 and the second input tube MN 2. By adding the second biasing unit 12, the second biasing unit 12 provides a biasing current within the setup time of the first biasing unit 11, improving the response speed of the amplifying circuit.

The present invention further provides a linear voltage stabilizing circuit, which includes the amplifying circuit 10.

Please refer to fig. 4, which is a circuit diagram of a linear voltage regulator circuit according to an embodiment of the present invention. As shown in FIG. 4, the linear voltage regulating circuit 20 of the present embodiment includes: an error amplifying module 21, an adjusting tube MP0 and a feedback unit 25. The output terminal of the linear voltage regulator circuit 20 is connected to the load capacitor CL and the load resistor RL.

The feedback unit 25 is configured to receive the output voltage Vout and generate a feedback voltage Vfb proportional to the output voltage Vout, and provide the feedback voltage Vfb to the error amplifying module 21. The error amplifying module 21 is configured to receive a feedback voltage Vfb proportional to the output voltage Vout, compare the feedback voltage Vfb with a reference voltage Vref, amplify a difference obtained by the comparison, and output an error amplification result to the gate of the adjusting transistor MP 0. The adjusting tube MP0 responds to the error amplification result applied to its gate, and finally stabilizes the output voltage Vout at a target value.

Specifically, the feedback unit 25 may be composed of a resistor R1 and a resistor R2 connected in series. One end of the resistor R1 is connected to the output voltage Vout, and one end of the resistor R2 is electrically connected to the common voltage terminal VSS. The connection end of the resistor R1 and the resistor R2 serves as a feedback output end FB of the feedback unit 25, and outputs a feedback voltage Vfb proportional to the output voltage Vout.

The error amplifying module 21 includes a first input tube MN1, a second input tube MN2, a first bias unit, and a current mirror composed of a transistor MP1 and a transistor MP2. The first input tube MN1 and the second input tube MN2 are differential input pair tubes. In this embodiment, the first input tube MN1 and the second input tube MN2 both use NMOS tubes. The gate of the first input transistor MN1 receives the feedback voltage Vfb, and the drain thereof is electrically connected to the node Q1. The gate of the second input transistor MN2 is for receiving a reference voltage Vref, and the drain thereof is electrically connected to an output node Q3. The source of the first input tube MN1 and the source of the second input tube MN2 are commonly electrically connected to the node Q2. The output node Q3 is connected with the grid electrode of the adjusting tube MP 0. The current mirror composed of the transistor MP1 and the transistor MP2 is used to copy the current of the first input transistor MN 1. In the embodiment shown in fig. 4, both the transistor MP1 and the transistor MP2 are PMOS. The gate of the transistor MP1 is electrically connected to the node Q1, the source thereof is electrically connected to the power supply voltage terminal VCC, and the drain thereof is electrically connected to the node Q1. The gate of the transistor MP2 is electrically connected to the node Q1, the source thereof is electrically connected to the power supply voltage terminal VCC, and the drain thereof is electrically connected to the output node Q3.

The first bias unit is, for example, a current source I. The current source I receives the first bias voltage Vbias1 and generates a bias current, which is directed from the node Q2 to the common voltage terminal VSS, to be supplied to the node Q2. The current source I includes a transistor MN3 and a transistor MN4. Specifically, the transistors MN3 and MN4 both use NMOS transistors. The gate of the transistor MN3 is shorted to the drain thereof for receiving the first bias voltage Vbias1, and the source thereof is electrically connected to the common voltage terminal VSS. The gate of the transistor MN4 is electrically connected to the gate of the transistor MN3, the source thereof is electrically connected to the common voltage terminal VSS, and the drain thereof is electrically connected to the node Q2. When the first bias voltage Vbias1 is provided to the current source I, the linear voltage stabilizing circuit starts to start. It should be noted that, in other embodiments, the error amplifying module 21 may also include a first current source I and a current mirror, and the current mirror mirrors the current generated by the current source I to the node Q2.

The linear voltage regulating circuit 20 further comprises a second biasing unit 23. In a start-up phase of the linear voltage stabilizing circuit 20, the first bias unit and the second bias unit 23 together provide a bias current for the first input tube MN1 and the second input tube MN 2. The second biasing unit 23 stops supplying the bias current when the output voltage Vout of the linear voltage regulating circuit is established to a target value. The target value of the output voltage Vout is the voltage of the linear voltage stabilizing circuit for supplying power to the outside.

As shown in fig. 4, in the present embodiment, the second biasing unit 23 includes: a transistor MN5, a capacitor C, a first switch SW1 and a second switch SW2. The transistor MN5 is disposed between the node Q2 and the common voltage terminal VSS. The capacitor C and the second switch SW2 are connected in parallel between the gate of the transistor MN5 and the common voltage terminal VSS. A first end of the capacitor C and a first end of the second switch SW2 are electrically connected to the gate of the transistor MN5, and a second end of the capacitor C and a second end of the second switch SW2 are electrically connected to the common voltage terminal VSS. The first switch SW1 is disposed between the first terminal of the capacitor C and the power supply voltage terminal VCC.

FIG. 5 is a timing diagram of the linear voltage regulating circuit of the present embodiment. As shown in FIG. 5, before the linear voltage regulating circuit is started, the control signal turns on the first switch SW1, turns off the second switch SW2, and charges the capacitor C so that the potential of the gate of the transistor MN5 rises to a predetermined potential, for example VCC. The predetermined potential causes the transistor MN5 to operate in a saturation region, for example, so that the transistor MN5 can supply a stable bias current. After the linear voltage stabilizing circuit 20 is enabled, the first time T1 and the second time T2 are entered in sequence. The first time T1 is a startup phase of the linear voltage regulating circuit 20. In some embodiments, the first time T1 is a setup time of the linear voltage regulating circuit 20, and the setup time of the linear voltage regulating circuit 20 is a time required from a startup of the linear voltage regulating circuit 20 until an output voltage of the linear voltage regulating circuit 20 is set up to a target value. At a first time T1, the control signal turns off the first switch SW1, and the second switch SW2 continues to be turned off. At a first time T1, the capacitor C maintains the gate of the transistor MN5 at a predetermined potential, and the transistor MN5 provides a bias current. At the beginning of the first time T1, the first bias voltage Vbias1 is provided to a first bias unit, i.e. a current source I. At the end of the first time T1, the output voltage of the linear voltage regulating circuit 20 builds to a target value and the second time T2 begins. At a second time T2, the second bias unit 23 stops providing the bias current, and the current source I continues to provide the bias current. The control signal causes the first switch SW1 to be continuously turned off, the second switch SW2 to be turned on, the capacitor C to discharge, the potential of the gate of the transistor MN5 to be VSS, and the transistor MN5 to be turned off. The first switch SW1 and the second switch SW2 may be electronic switches or transistors, and the transistors may also be MOS transistors, triodes, or other transistors with switching properties.

Fig. 6 is a circuit diagram of a second bias unit according to another embodiment of the invention. As shown in fig. 6, the second biasing unit 23 includes a transistor MN5. In this embodiment, the transistor MN5 is an NMOS transistor, and one end of the transistor MN5 is electrically connected to the node Q2, and the other end is electrically connected to the common voltage terminal VSS. In other embodiments, the transistor MN5 may also be a transistor in other forms, such as a PMOS transistor, and the manner of connecting the transistor to the circuit is adaptively adjusted. A first time T1, a second bias voltage Vbias2 is supplied to the gate of transistor MN 5; at the second time T2, the supply of the second bias voltage Vbias2 to the gate of transistor MN5 is stopped. In the stage of establishing the target value of the output voltage of the linear voltage stabilizing circuit, the second bias unit 23 is additionally arranged, so that the target value of the output voltage of the linear voltage stabilizing circuit is quickly established. After the target value of the output voltage of the linear voltage stabilizing circuit is established, the second bias unit 23 does not provide bias current any more, and the power consumption of the linear voltage stabilizing circuit is reduced. In some embodiments, the second bias unit 23 further includes a resistor R5, and the resistor R5 is electrically connected between the source of the transistor MN5 and the common voltage terminal VSS, and is used for adjusting the current flowing through the transistor MN5.

Fig. 7 is a circuit diagram of a second bias unit according to another embodiment of the present invention. As shown in fig. 7, the second bias unit 23 includes a current source Ibias and a current mirror. At a first time T1, bias current generated by a current source Ibias is provided to a node Q2 through a current mirror; at a second time T2, the bias current generated by the current source Ibias stops being provided to the node Q2. The current mirror includes, for example, transistors MN6 and MN7, and the second bias unit 23 further includes a third switch SW3 and a fourth switch SW4. The control signals of the third switch SW3 and the fourth switch SW4 may be provided by a controller. A third switch SW3 is arranged between the input of the current mirror and the output of the current source Ibias. The input of the current mirror receives the current provided by the current source Ibias via the third switch SW 3. The fourth switch SW4 is disposed between the gate of the output tube MN7 of the current mirror and the common voltage terminal VSS. At a first time T1, the third switch SW3 is turned on, the fourth switch SW4 is turned off, and the current mirror mirrors the current provided by the current source Ibias to the node Q2. After the output voltage Vout is established to the target value, i.e., at the second time T2, the third switch SW3 is turned off and the fourth switch SW4 is turned on. The third switch SW3 and the fourth switch SW4 may be electronic switches or transistors, and the transistors may also be MOS transistors, triodes, or other transistors with switching properties.

The linear voltage stabilizing circuit is additionally provided with a second biasing unit on the basis of the original circuit; in the starting stage of the linear voltage stabilizing circuit, the first bias unit and the second bias unit jointly provide bias current for the two input tubes of the error amplification module, so that the response speed of the error amplification module is improved; when the output voltage of the linear voltage stabilizing circuit is adjusted to be close to the target value, the second bias unit is controlled to stop providing the bias current, and the power consumption of the linear voltage stabilizing circuit during normal operation is further reduced.

In the foregoing embodiments, the descriptions of different embodiments have different emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments. The embodiments described above are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, those skilled in the art can obtain all other embodiments without making creative efforts, and except for the design of the embodiments consistent with the embodiments of the present invention mentioned in the embodiments of the present invention, the design is within the protection scope of the present invention.

Based on the same inventive concept, the invention also provides an electronic device.

Please refer to fig. 8, which is a schematic diagram of an electronic device according to an embodiment of the present invention. The electronic device 80 includes a linear voltage regulator circuit 81. The electronic device 80 further includes a controller for generating the switching control signals required for the linear voltage regulating circuit 81. The linear regulator 81 is, for example, the linear regulator of the above embodiments, and the description thereof is omitted. Therefore, the electronic device 80 can also provide bias current for the two input tubes of the error amplification module through the first bias unit and the second bias unit together at the start stage of the linear voltage stabilizing circuit, so that the response adjustment speed of the error amplification module is increased; when the output voltage of the linear voltage stabilizing circuit is adjusted to be close to the target value, the second bias unit is controlled to stop providing the bias current, and the power consumption of the linear voltage stabilizing circuit during normal operation is further reduced.

The electronic device 80 is, for example, a nonvolatile memory or a volatile memory. Non-volatile memory refers to a type of memory that retains data after power is removed, i.e., the stored data is not lost after power is removed. Examples of the nonvolatile Memory include a Flash Memory (Flash Memory), a phase change random access Memory (PRAM), a Magnetic Random Access Memory (MRAM), and a Resistive Random Access Memory (RRAM). The flash memory includes, for example, NOR flash memory (NOR flash memory) and NAND flash memory (NAND flash memory). Volatile memory includes, for example, dynamic Random Access Memory (DRAM), static Random Access Memory (SRAM).

It will be appreciated that for clarity purposes, embodiments of the invention have been described above with reference to a single processing logic. However, the inventive concept may equally be implemented by means of a plurality of different functional units and processors to provide the signal processing functions. Thus, references to specific functional units are only to be seen as references to suitable means for providing the described functionality rather than indicative of a strict logical or physical structure or organization.

The above description of the embodiments is only for helping understanding the technical solution of the present invention and its core idea; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims

1. An amplification circuit, comprising: the device comprises a first input pipe, a second input pipe, a first biasing unit and a second biasing unit;

the first bias unit and the second bias unit jointly provide bias current for the first input tube and the second input tube at a first time, the second bias unit stops providing the bias current at a second time, and the first bias unit continues to provide the bias current for the first input tube and the second input tube.

2. The amplification circuit of claim 1, wherein the first bias unit comprises a current source.

3. A linear voltage regulator circuit, comprising:

an adjusting tube;

a feedback unit;

an error amplification module comprising a first input tube, a second input tube, and a first bias unit; and

a second bias unit for biasing the second bias unit,

in a starting stage of the linear voltage stabilizing circuit, the first biasing unit and the second biasing unit jointly provide a biasing current for the first input tube and the second input tube, and when an output voltage of the linear voltage stabilizing circuit is established to a target value, the second biasing unit stops providing the biasing current.

4. The linear voltage regulation circuit of claim 3 wherein the first bias unit is a current source.

5. The linear voltage regulating circuit of claim 3, wherein the second biasing unit includes a transistor for generating a bias current; in the starting stage of the linear voltage stabilizing circuit, the grid electrode of the transistor receives a second bias voltage to generate bias current; the transistor is turned off when the output voltage builds to a target value.

6. The linear voltage regulation circuit of claim 3 wherein the second biasing unit comprises: a transistor, a capacitor, a first switch and a second switch; the transistor is used for generating bias current, and the capacitor and the second switch are connected in parallel at the grid and the source of the transistor; the first switch is arranged between the grid electrode of the transistor and a power supply voltage end;

before the starting stage of the linear voltage stabilizing circuit, the first switch is switched on, the second switch is switched off, and the capacitor is charged; in the starting stage of the linear voltage stabilizing circuit, the first switch is switched off, and the second switch is switched off; when the output voltage is established to a target value, the first switch is turned off, and the second switch is turned on.

7. The linear voltage regulating circuit of claim 3, wherein said transistor operates in saturation during a startup phase of said linear voltage regulating circuit.

8. The linear voltage regulating circuit of claim 3, wherein the second biasing unit includes: the current source, the current mirror, the third switch and the fourth switch; an input terminal of the current mirror receives the current provided by the current source via the third switch; the fourth switch is arranged between the grid electrode of the output tube of the current mirror and the common voltage end;

in a starting stage of the linear voltage stabilizing circuit, the third switch is turned on, and the fourth switch is turned off; when the output voltage is established to a target value, the third switch is turned off, and the fourth switch is turned on.

9. An electronic device, characterized in that the electronic device comprises a linear voltage regulating circuit according to any of claims 3 to 8.

10. The electronic device of claim 9, wherein the electronic device is a non-volatile memory.