CN115312000A

CN115312000A - Display panel and display device

Info

Publication number: CN115312000A
Application number: CN202211053553.4A
Authority: CN
Inventors: 张蒙蒙; 李玥
Original assignee: Wuhan Tianma Microelectronics Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2022-08-30
Filing date: 2022-08-30
Publication date: 2022-11-08

Abstract

The invention discloses a display panel and a display device, belonging to the technical field of display, wherein the display panel comprises a plurality of data lines, the display panel comprises a non-display area, and a multiplexing circuit of the non-display area comprises a plurality of multiplexing units; the multiplexing unit comprises a signal input end, a plurality of signal output ends, a plurality of shunt control ends and a plurality of switch transistors, the grid of each switch transistor is connected with the shunt control end, the shunt control end is connected with a shunt control signal, the shunt control signal comprises an enable signal, a non-enable signal and at least one transition signal, and the value of the transition signal is between the value of the enable signal and the value of the non-enable signal; at least one transition signal is included in the process of converting the non-enable signal into the enable signal, and at least one transition signal is included in the process of converting the enable signal into the non-enable signal. The display device comprises the display panel. The invention can save panel power consumption, improve screen occupation ratio and realize narrow frame design.

Description

Display panel and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.

Background

Organic Light Emitting Diodes (OLEDs) are one of the hot spots in the research field of flat panel displays, and compared with liquid crystal displays, OLEDs have excellent characteristics of self-luminescence, low energy consumption, wide viewing angle, rich colors, fast response, etc. at present, in the display fields of mobile phones, PDAs, digital cameras, etc., OLEDs have begun to replace the conventional LCD display screens, and OLEDs are considered as the next generation display technology with great potential.

Along with full screen display screen is more and more received consumer's favor, the market is also higher and higher to the screen ratio requirement of display module assembly, and therefore the frame of display screen also requires more and more narrowly. However, the narrow-frame display screen in the prior art often has the problem that the power consumption is too high, and the display quality is influenced.

Therefore, it is an urgent technical problem for those skilled in the art to provide a display panel and a display device that can save panel power consumption, improve screen occupation ratio, and realize a narrow bezel design.

Disclosure of Invention

In view of this, the invention provides a display panel and a display device, so as to solve the problem that the narrow-bezel display screen in the prior art is easily over-high in power consumption, which causes influence on display quality.

The invention discloses a display panel, comprising: the liquid crystal display panel comprises a plurality of sub-pixels, a plurality of scanning lines and a plurality of data lines, wherein the scanning lines and the data lines are crossed and insulated to define a region where the sub-pixels are located; the display panel comprises a non-display area, the non-display area comprises a multiplexing circuit, and the multiplexing circuit comprises a plurality of multiplexing units; the multiplexing unit comprises a signal input end, a plurality of signal output ends, a plurality of shunt control ends and a plurality of switch transistors, wherein the grid electrodes of the switch transistors are connected with the shunt control ends, the first poles of the switch transistors are connected with the signal input end, and the second poles of the switch transistors are connected with the signal output end; the signal input end is connected with a data voltage signal, and the signal output ends are electrically connected with the data lines in a one-to-one correspondence manner; the shunt control end is connected with a shunt control signal, the shunt control signal comprises an enable signal, a non-enable signal and at least one transition signal, and the value of the transition signal is between the value of the enable signal and the value of the non-enable signal; at least one transition signal is included in the process of converting the non-enable signal into the enable signal, and at least one transition signal is included in the process of converting the enable signal into the non-enable signal.

Based on the same inventive concept, the invention also discloses a display device, which comprises the display panel.

Compared with the prior art, the display panel and the display device provided by the invention at least realize the following beneficial effects:

the non-display area of the display surface of the present invention includes a multiplexing circuit for supplying a data voltage signal to each data line in the display area. The multiplexing circuit comprises a plurality of multiplexing units, namely multiplexers, and is used for decomposing a data voltage signal of a signal input end into a plurality of signal channels and transmitting the signal channels to a plurality of data lines in the display area simultaneously or in a time-sharing manner, so that the number of data signal transmission lines connected with the signal input end in the non-display area is favorably reduced, the layout space of the non-display area is favorably reduced, the frame of the display panel is reduced, and the narrow-frame design is realized. In the display panel of the invention, the shunt control signal connected to the shunt control terminal is further provided to include not only the enable signal and the disable signal, but also at least one transition signal during at least one period of controlling the on and off of the switching transistor, wherein a value of the transition signal is between a value of the enable signal and a value of the disable signal, that is, the transition signal can be understood as a transition signal between a high level signal and a low level signal of the shunt control signal, so that when the shunt control signal is switched from the disable signal to the enable signal, switching to the transition signal is performed first, or preparing to convert the disable signal to a transition signal close to the enable signal in advance, and then switching from the transition signal to a required enable signal is performed, which is beneficial to further reducing the driving power consumption of the shunt control terminal during the switching transistor is switched from the off state to the on state. Similarly, in the process of converting the enable signal into the disable signal, when the shunt control signal is switched from the enable signal to the disable signal, the shunt control signal is switched to the transition signal first, and it can also be understood that the shunt control signal is prepared to be a transition signal which is close to the disable signal in advance, and then the shunt control signal is switched to the required disable signal from the transition signal, which is beneficial to further reducing the driving power consumption of the shunt control end in the process of converting the switch transistor from the on state to the off state, so that the screen occupation ratio can be improved, and when the narrow-frame design is realized, the power consumption of the whole display panel can be saved.

Of course, it is not necessary for any product in which the present invention is practiced to specifically achieve all of the above-described technical effects simultaneously.

Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments of the invention, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.

Fig. 1 is a schematic plan view of a display panel according to an embodiment of the present invention;

FIG. 2 is an enlarged partial schematic view of the area Q1 of FIG. 1;

FIG. 3 is a timing diagram of the shunt control signals of FIG. 2;

FIG. 4 is a schematic diagram of another planar structure of a display panel according to an embodiment of the present invention;

FIG. 5 is an enlarged partial schematic view of the area Q2 of FIG. 4;

FIG. 6 is a timing diagram of the shunt control signals of FIG. 5;

FIG. 7 is a timing diagram of a shunt control signal of FIG. 6;

fig. 8 is a schematic structural view of the switching transistor in this embodiment when it is formed over a substrate of a display panel;

FIG. 9 is another timing diagram of the shunt control signals of FIG. 5;

FIG. 10 is another timing diagram of the shunt control signals of FIG. 5;

fig. 11 is a schematic diagram of a connection structure of circuit modules in a sub-pixel provided in this embodiment;

FIG. 12 is a schematic diagram of the connection structure of the circuit of FIG. 11;

fig. 13 is a schematic plan view of a display device according to an embodiment of the present invention.

Detailed Description

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless it is specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

Referring to fig. 1 to fig. 3 in combination, fig. 1 is a schematic plan view of a display panel according to an embodiment of the present invention, fig. 2 is a schematic partial enlarged view of a region Q1 in fig. 1, fig. 3 is a timing diagram of a branch control signal in fig. 2, and the display panel 000 according to the embodiment includes: the pixel structure comprises a plurality of sub-pixels P, a plurality of scanning lines G and a plurality of data lines S, wherein the scanning lines G and the data lines S are crossed and insulated to define the area where the sub-pixels P are located;

the display panel 000 includes a non-display area NA including a multiplexing circuit 10, the multiplexing circuit 10 including a plurality of multiplexing units 101;

the multiplexing unit 101 comprises a signal input end 101A, a plurality of signal output ends 101B, a plurality of shunt control ends 101C and a plurality of switch transistors 101T, wherein the gate of the switch transistor 101T is connected with the shunt control end 101C, the first pole of the switch transistor 101T is connected with the signal input end 101A, and the second pole of the switch transistor 101T is connected with the signal output end 101B; the signal input end 101A is connected with a data voltage signal Vdata, and the signal output ends 101B are electrically connected with the data lines S in a one-to-one correspondence manner;

the shunt control terminal 101C is connected to the shunt control signal CKH, which includes an enable signal CKHA, a non-enable signal CKHB, and at least one transition signal CKHC, where the value of the transition signal CKHC is between the value of the enable signal CKHA and the value of the non-enable signal CKHB;

at least one transition signal CKHC is included in the process of converting the non-enable signal CKHB into the enable signal CKHA, and at least one transition signal CKHC is included in the process of converting the enable signal CKHA into the non-enable signal CKHB.

Specifically, the non-display area NA of the display panel 000 of the present embodiment includes a multiplexing circuit 10, and the multiplexing circuit 10 is configured to provide the data voltage signal Vdata to each data line S in the display area AA. In the prior art, with the requirement of high resolution of the display panel 000, the number of the sub-pixels P in the display panel 000 is increasing, and the number of the signal lines such as the data lines S is also increasing, so that the frame of the display panel 000 with high resolution needs more and more space for arranging some structures (such as the structure of the pads connected to the signal lines to provide driving signals for the signal lines), and further, it is difficult to implement narrow frame design. The present embodiment provides the multiplexing circuit 10 in the non-display area NA, and the multiplexing circuit 10 includes a plurality of multiplexing units 101, i.e., a multiplexer (Demultiplexer) 101, for dividing one signal into a plurality of signal channels. Optionally, each multiplexing unit 101 includes a signal input end 101A, a plurality of signal output ends 101B, a plurality of shunt control ends 101C, and a plurality of switch transistors 101T, where the number of shunt control ends 101C, the number of signal output ends 101B, and the number of switch transistors 101T included in each multiplexing unit 101 may be equal. The gate of the switch transistor 101T is connected to the shunt control terminal 101C, the shunt control signal CKH connected to the shunt control terminal 101C controls the switch transistor 101T to be turned on or off, if the switch transistor 101T is a P-type transistor, the shunt control signal CKH provides a low-level (e.g., negative-value voltage) signal to the gate of the switch transistor 101T, and the switch transistor 101T is in a conducting state, and if the switch transistor 101T is an N-type transistor, the shunt control signal CKH provides a high-level (e.g., positive-value voltage) signal to the gate of the switch transistor 101T, and the switch transistor 101T is in a conducting state. The first pole of the switching transistor 101T of each multiplexing unit 101 of the present embodiment is connected to one signal input terminal 101A, and when the switching transistor 101T is in an on state, transmission can be conducted between the signal input terminal 101A connected to the first pole of the switching transistor 101T and the signal output terminal 101B connected to the second pole. Since the signal input terminal 101A of the present embodiment is connected to the data voltage signal Vdata (optionally, the data voltage signal Vdata may be provided by a driving chip bound in the non-display area NA, not shown in the drawings), and the signal output terminals 101B are electrically connected to the data lines S in a one-to-one correspondence manner, when the switching transistor 101T is turned on, the data voltage signal Vdata provided by one signal input terminal 101A included in each multiplexing unit 101 may be transmitted to a plurality of data lines S connected to a plurality of corresponding signal output terminals 101B, so as to provide the data driving signal to the sub-pixel P through the data line S, thereby achieving the light emitting display effect of the sub-pixel P. Because one signal input end 101A of each multiplexing unit 101 corresponds to the plurality of signal output ends 101B through the plurality of switching transistors 101T, the data voltage signal Vdata of one signal input end 101A can be decomposed into a plurality of signal channels, and transmitted to the plurality of data lines S in the display area AA simultaneously or in a time-sharing manner, which is beneficial to reducing the number of data signal transmission lines connected with the signal input end 101A in the non-display area NA, and is further beneficial to reducing the layout space of the non-display area NA, reducing the frame of the display panel 000, and realizing a narrow frame design.

It can be understood that, in the present embodiment, the larger the number of the signal output terminals 101B corresponding to one signal input terminal 101A of each multiplexing unit 101 is, the more the reduction of the size of the frame can be achieved, and the narrower frame design is achieved, in fig. 2 of the present embodiment, an example is only illustrated in which one signal input terminal 101A of each multiplexing unit 101 corresponds to three signal output terminals 101B through three switching transistors 101T, for example, if the three switching transistors 101T are 101T1, 101T2, and 101T3, the shunt control terminals 101C connected to the gates of the three switching transistors 101T are 101C1, 101C2, and 101C3, respectively, the shunt control terminal 101C1 is connected to the shunt control signal CKH1, the shunt control terminal 101C2 is connected to the shunt control signal CKH2, and the shunt control terminal 101C3 is connected to the shunt control signal CKH3, where the shunt control signal CKH1, the shunt control signal CKH2, and the shunt control signal CKH3 include the enable signal CKHA, the non-enable signal, the at least one transition signal, and when the embodiment is implemented, the more the number of the signal output terminals 101A corresponding to each multiplexing unit 101A can be also not limited.

It can be understood that, when the display panel 000 is an oled display panel, the layout of the signal lines in the display panel 000 is complex, and at this time, one sub-pixel row may correspond to a plurality of scan lines G, and the area where the sub-pixel P is located may be an area defined by one scan line G and the data line S.

In each multiplexing unit 101 in this embodiment, the gate of the switching transistor 101T needs to be connected to the shunt control terminal 101C, and a shunt control signal CKH for controlling whether the switching transistor 101T is turned on or off is supplied through the shunt control terminal 101C. In the whole process of controlling the on and off of the switch transistor 101T, the shunt control signal CKH in the prior art only has two states of high level and low level, and as the size of the display panel becomes larger and larger, the resolution becomes higher and higher, in order to ensure the narrow-frame design, the number of the signal output terminals 101B corresponding to one signal input terminal 101A of each multiplexing unit 101 also becomes larger and larger, at this time, the shunt control signal CKH only having two states of high level and low level is continuously used to control the on and off of the switch transistor 101T, which may cause the power consumption of the multiplexing circuit 10 to be very large, and further affect the overall display quality of the display panel 000.

In order to solve the above problem, in the display panel 000 of the embodiment, the shunt control signal CKH connected to the shunt control terminal 101C is set to include not only the enable signal CKHA and the disable signal CKHB but also at least one transition signal CKHC during at least one period of controlling the on and off of the switching transistor 101T, wherein the value of the transition signal CKHC is between the value of the enable signal CKHA and the value of the disable signal CKHB; it can be understood that the shunt control signal CKH is an enable signal CKHA, which indicates that the value of the enable signal CKHA can turn on the switch transistor 101T controlled by the shunt control terminal 101C, and the shunt control signal CKH is a non-enable signal CKHB, which indicates that the value of the non-enable signal CKHB can turn off the switch transistor 101T controlled by the shunt control terminal 101C; if the switch transistor 101T is an N-type transistor, the enable signal CKHA can be understood as a high level signal, and the disable signal CKHB can be understood as a low level signal. In this embodiment, the shunt control signal CKH further includes at least one transition signal CKHC during at least one period of controlling the on and off of the switch transistor 101T, and the value of the transition signal CKHC is between the value of the enable signal CKHA and the value of the disable signal CKHB, that is, the transition signal CKHC can be understood as a transition signal between the high level signal and the low level signal of the shunt control signal CKH, and optionally, as shown in fig. 3, in the process of converting the disable signal CKHB to the enable signal CKHA, that is, during the period T1, in the process of converting the switch transistor 101T from the off state to the on state, at least one transition signal CKHC is included, so that when the shunt control signal CKH is converted from the disable signal CKHB to the enable signal CKHA, the transition signal CKHC is first switched, or the transition signal CKHC is prepared to convert the disable signal CKHB to the shunt signal CKHC close to the enable signal CKHA in advance, and then the transition signal CKHC is switched from the transition signal CKHC to the enable signal CKHC, which is favorable for further reducing the power consumption of the drive terminal during the process of converting the switch transistor 101T from the off state to the on state. Similarly, in the process of converting the enable signal CKHA into the disable signal CKHB, that is, in the process of converting the switching transistor 101T from the on state to the off state during T2, at least one transition signal CKHC is also included, so that when the shunt control signal CKH is converted from the enable signal CKHA to the disable signal CKHB, the shunt control signal CKH is first switched to the transition signal CKHC, and it can also be understood that the shunt control signal CKHA is prepared to be converted into the transition signal CKHC close to the disable signal CKHB in advance, and then switched from the transition signal CKHC to the required disable signal CKHB, which is beneficial to further reducing the driving power consumption of the shunt control terminal 101C in the process of converting the switching transistor 101T from the on state to the off state, thereby improving the duty ratio, realizing the narrow-frame design, and saving the power consumption of the entire display panel 000.

It can be understood that, in this embodiment, specific voltage values of the enable signal CKHA, the non-enable signal CKHB, and the transition signal CKHC included in the shunt control signal CKH are not specifically limited, and only a short transition signal CKHC process is required to be performed in the conversion process of the enable signal CKHA and the non-enable signal CKHB, and the value of the transition signal CKHC is located between the value of the enable signal CKHA and the value of the non-enable signal CKHB.

It should be noted that the display panel 000 provided in this embodiment may be an organic light emitting diode display panel, and the structure of the display panel is only exemplarily shown in the drawing of this embodiment, and in a specific implementation, the structure of the display panel 000 includes but is not limited to this, and may also include other structures capable of implementing a display function, which can be specifically understood with reference to the structure of the organic light emitting diode display panel in the related art, and this embodiment is not described herein again.

In some optional embodiments, please refer to fig. 4-6 in combination, fig. 4 is a schematic diagram of another plane structure of a display panel according to an embodiment of the present invention, fig. 5 is a schematic diagram of a portion of a Q2 region in fig. 4, fig. 6 is a timing diagram of the shunt control signal in fig. 5, in this embodiment, the multiplexing unit 101 includes a signal input terminal 101A, M signal output terminals 101B, M shunt control terminals 101C, and M switching transistors 101T; wherein M is more than or equal to 6.

This embodiment explains that the multiplexing circuit 10 is provided in the non-display area NA, the multiplexing circuit 10 includes a plurality of multiplexing units 101, and the multiplexing units 101 can decompose one signal into at least 6 signal channels. That is, the multiplexing unit 101 includes a signal input terminal 101A, M signal output terminals 101B, M shunt control terminals 101C, and M switching transistors 101T; wherein M is more than or equal to 6. In this embodiment, the signal input terminal 101A is connected to a data voltage signal Vdata (optionally, the data voltage signal Vdata may be provided by a driving chip bound in the non-display area NA, not shown in the figure), and the signal output terminals 101B are electrically connected to the data lines S in a one-to-one correspondence manner, so that when the switching transistor 101T is turned on, the data voltage signal Vdata provided by one signal input terminal 101A included in each multiplexing unit 101 may be transmitted to at least 6 data lines S connected to at least 6 corresponding signal output terminals 101B, and then a data driving signal is provided to the sub-pixel P through the data line S, thereby achieving a light emitting display effect of the sub-pixel P. Because one signal input end 101A of each multiplexing unit 101 corresponds to at least 6 signal output ends 101B through at least 6 switching transistors 101T, the data voltage signal Vdata of one signal input end 101A can be decomposed into at least 6 signal channels, and simultaneously or time-divisionally transmitted to at least 6 data lines S in the display area AA, which is beneficial to further reducing the number of data signal transmission lines connected with the signal input end 101A in the non-display area NA, and further reducing the frame of the display panel 000, thereby realizing a narrower frame design.

It can be understood that, when a narrower frame is implemented, the multiplexing unit 101 of the multiplexing circuit 10 needs to decompose a signal into at least 6 signal channels, and further the number of the shunt control terminals 101C needs to be at least 6, and further when the multiplexing circuit 10 is driven to operate, the driving power consumption of the shunt control terminal 101C is further increased in the process of switching the switch transistor 101T from the off state to the on state, therefore, the shunt control signal CKH set in this embodiment includes at least one transition signal CKHC in the process of controlling at least one period of on and off of the switch transistor 101T, and the value of the transition signal CKHC is between the value of the enable signal CKHA and the value of the non-enable signal CKHB, so as to better reduce the power consumption in the design of the narrower frame, and further, when a narrower frame is implemented, full-screen display is implemented as much as possible, and the power consumption of the panel is saved.

It should be noted that, in the drawings in this embodiment, only the multiplexing unit 101 includes one signal input end 101A, 6 signal output ends 101B, 6 shunt control ends 101C, and 6 switching transistors 101T, that is, the multiplexing unit 101 decomposes a signal into at least 6 signal channels for example, in specific implementation, the multiplexing unit 101 may also be configured to decompose a signal into a structure with more signal channels, which is not described in detail herein in this embodiment.

In some alternative embodiments, please refer to fig. 4-6 and 7 in combination, fig. 7 is a timing diagram of a shunt control signal in fig. 6, in this embodiment, the shunt control signal CKH includes two adjacent non-enable signals CKHB, an interval time between the two adjacent non-enable signals CKHB is d, and a holding time of the enable signal CKHA between the two adjacent non-enable signals CKHB is b;

at least two transition signals CKHC are included between two adjacent non-enable signals CKHB, and are respectively a first transition signal CKHC1 and a second transition signal CKHC2;

between two adjacent non-enable signals CKHB, the sustain time of the first transition signal CKHC1 is a, the sustain time of the second transition signal CKHC2 is c, and d-b = a + c.

This embodiment explains that, during at least one period of the on and off control of the switching transistor 101T, the time interval between two adjacent non-enable signals CKHB is d, that is, the time interval from one non-enable signal CKHB to the next is d, and optionally, the time unit of d may be in the order of microseconds, that is, the time interval between two adjacent non-enable signals CKHB is very short in the shunt control signal CKH connected to the shunt control terminal 101C of the multiplexing unit 101. The sustain time of the enable signal CKHA between two adjacent non-enable signals CKHB is b, and b is less than d. Since at least one transition signal CKHC is included in the process of converting the non-enable signal CKHB into the enable signal CKHA and at least one transition signal CKHC is included in the process of converting the enable signal CKHA into the non-enable signal CKHB, at least two transition signals CKHC are included between two adjacent non-enable signals CKHB, and the at least two transition signals CKHC may be named as a first transition signal CKHC1 and a second transition signal CKHC2. If the holding time of the first transition signal CKHC1 is a and the holding time of the second transition signal CKHC2 is c between two adjacent non-enable signals CKHB, d-b = a + c needs to be ensured, that is, the sum of the holding time a of the first transition signal CKHC1, the holding time c of the second transition signal CKHC2 and the holding time b of the enable signal CKHA is the interval time d of the two adjacent non-enable signals CKHB, so that the interval time d of the two adjacent non-enable signals CKHB can be ensured, the holding time of the transition signal CKHC is all times except the holding time of the enable signal CKHA, and the interval time of the two adjacent non-enable signals CKHB can be used as much as possible to set the transition signal CKHC while ensuring that the switching transistor 101T is fully turned on by enough holding time of the enable signal CKHA, thereby saving panel power consumption to the maximum extent.

In some alternative embodiments, please refer to fig. 4-7 in combination, in this embodiment, the sustain time a of the first transition signal CKHC1 is equal to the sustain time c of the second transition signal CKHC2 between two adjacent non-enable signals CKHB, i.e. a = c.

The present embodiment explains that the shunt control signal CKH connected between two adjacent non-enable signals CKHB, i.e., the shunt control terminal 101C of the multiplexing unit 101, includes at least two transition signals CKHC in the process of controlling the turn-off of the switching transistor 101T to the next turn-off, and the at least two transition signals CKHC may be named as a first transition signal CKHC1 and a second transition signal CKHC2, the first transition signal CKHC1 may be in the process of converting the non-enable signal CKHB into the enable signal CKHA, and the second transition signal CKHC2 may be in the process of converting the enable signal CKHA into the non-enable signal CKHB. The present embodiment is disposed between two adjacent non-enable signals CKHB, the holding time a of the first transition signal CKHC1 is equal to the holding time c of the second transition signal CKHC2, so that the holding time a of the first transition signal CKHC1 is equal to the holding time c of the second transition signal CKHC2 as much as possible, and further, when the shunt control signal CKH is switched from the non-enable signal CKHB to the enable signal CKHA, the shunt control signal CKH is switched to the first transition signal CKHC1 first, or when the shunt control signal CKH is switched from the enable signal CKHA to the first transition signal CKHC1 close to the enable signal CKHA in advance, the shunt control signal CKH is switched to the second transition signal CKHC2 first, or when the shunt control signal CKH is switched from the enable signal CKHA to the non-enable signal CKHB, the shunt control signal CKH is switched to the second transition signal CKHC2 first, or when the shunt control signal CKH is switched from the enable signal CKHA to the non-enable signal CKHA to the enable signal CKHA in advance, the power consumption of the shunt control signal CKH is switched to the non-enable signal CKHC2, and the power consumption of the shunt control signal CKHC is also reduced from the second transition signal CKHC2 to the non-enable signal CKHC, so that the power consumption of the second transition signal CKHC is equalized, and the power consumption of the non-enable signal CKHC is also reduced.

In some alternative embodiments, please refer to fig. 4-7 and fig. 8 in combination, fig. 8 is a schematic structural diagram of a switch transistor in this embodiment when it is fabricated on a substrate of a display panel, in this embodiment,

wherein n is included in the display panel 000The number of scanning lines G, W/L, is the width-to-length ratio of the channel region of the switching transistor 101T.

Optionally, the scan lines G, the data lines S, the sub-pixels P, the multiplexing circuits 10, and other structures in the display panel 000 may all be disposed on the substrate 00 (not filled in the figure), and the switch transistor 101T further includes a first gate 101TG, a first source 101TS, and a first drain 101TD;

the length of the channel region of the switching transistor 101T along the first direction X is L, the width of the channel region of the switching transistor 101T along the second direction Y is W, and the width-to-length ratio of the channel region of the switching transistor 101T is W/L; in a direction parallel to the plane of the display panel 000, a direction in which the first source 101TS points to the first drain 101TD is a first direction X, and the second direction Y intersects with the first direction X.

This embodiment explains that the time for which the transition signal CKHC in the shunt control signal CKH is maintained can be set according to parameters such as the size of the display panel 000, the number of rows of the sub-pixels P included in the display panel 000, and the size of the switching transistor 101T in the multiplexing unit 101. Specifically, the total holding time of the transition signal CKHC between two adjacent non-enable signals CKHB, i.e. the sum a + c of the holding time a of the first transition signal CKHC1 and the holding time c of the second transition signal CKH2 is less than or equal to

Where n is the number of scanning lines G included in the display panel 000, i.e., the number of rows of the sub-pixels P included in the display panel 000, and W/L is the width-to-length ratio of the channel region of the switching transistor 101T in the multiplexing unit 101. As shown in fig. 8, when the multiplexing circuit 10 including the multiplexing units 101 is fabricated on the substrate 00 of the display panel 000, the switching transistor 101T further includes a first gate 101TG, a first source 101TS, a first drain 101TD, and an active portion 101TP, and the channel region 101T0 of the switching transistor 101T is understood as the intersection of the first gate 101TG of the switching transistor 101T and the active portion 101TP of the switching transistor 101TIn the overlap region, the channel region 101T0 of the switching transistor 101T has a length L in the first direction X, the channel region 101T0 of the switching transistor 101T has a width W in the second direction Y, and the channel region of the switching transistor 101T has a width-to-length ratio W/L. The embodiment sets the time for maintaining the transition signal CKHC in the shunting control signal CKH according to the parameters of the size of the display panel 000, the number of rows of the sub-pixels P included in the display panel 000, and the size of the switching transistor 101T in the multiplexing unit 101, and ensures that the sum a + c of the time a for maintaining the first transition signal CKHC1 and the time c for maintaining the second transition signal CKH2 is less than or equal to

Within the range of (1), the problem that the power consumption of the panel cannot be effectively saved due to the fact that the data voltage signal Vdata cannot be sufficiently and accurately written into the sub-pixel P by the data line S because the time for maintaining the transition signal CKHC is too long and the time for maintaining the transition signal CKHC is not sufficient and the time for maintaining the enable signal CKHA between two adjacent non-enable signals CKHB is not sufficient can be avoided. Therefore, in the embodiment, for the limitation of the sum of the time a for maintaining the first transition signal CKHC1 and the time c for maintaining the second transition signal CKH2, it is ensured that the time for maintaining the enable signal CKHA is sufficient, the data voltage signal Vdata can be accurately written into the sub-pixel P by the data line S with sufficient time, the display quality of the display panel is ensured, and the power consumption can be effectively saved, so that the balance between the display quality and the power consumption can be improved.

Optionally, since the multiplexing circuit 10 is connected to the data line S, the multiplexing circuit 10 needs to load the resistance of the data line S, and assuming that the resistance R of the data line S connected to one sub-pixel P is about 2 (Ω), the capacitance C is about 30 (fF), and the sub-pixels P in the display panel 000 are n rows, the total resistance R of the data line S corresponding to one column of sub-pixels P is 2n (Ω), and the total capacitance C is 30n (fF);

the on-resistance of the switching transistor 101T having a channel region width-to-length ratio W/L of 1 is about 2 × 10 ⁵ (Ω) the switching transistor 101T has a size of W/L and a resistance of 2 × 10 ⁵ (Ω) /(W/L), although the signal input terminal 101A of the multiplexing circuit 10 needs to be connected to the bonding pad through a data signal transmission line (i.e., a fan-out lead) to provide the data voltage signal Vdata, the length of the data signal transmission line is generally short, the resistance is small, and the resistance is small and negligible compared to the switching transistor 101T. Therefore, the total resistance of the switching transistor 101T and the data line S corresponding to a column of sub-pixels P is 2n +2 × 10 ⁵ /(W/L) (Ω), total capacitance of 30n (fF), i.e., 30n × 10 ^-15 (F) .1. The The time constant is total resistance × total capacitance = [2n +2 × 10 ] when the column of sub-pixels P is charged through the multiplexing circuit 10 ⁵ /(W/L)]×30n×10 ^-15 。

Since the multiplexing circuit 10 of this embodiment charges the sub-pixel P by the data line S, when the voltage on the data line S reaches 99% of the target voltage, the charging is sufficient, and the time constant corresponding to the time required is 5 times, that is, the time b required for maintaining the enable signal CKHA between two adjacent non-enable signals CKHB at least satisfies:

it is understood that in a typical wearable display panel 000, the number of rows n of sub-pixels P in the display panel 000 is typically less than 500, and the value of 2n is relative to the value of n

Can be ignored, the above formula

May be approximately equal to 3n × 10 ^-8 /(W/L)(s), i.e. 0.03 n/(W/L) (us), so that it is at least necessary for b to be greater than or equal to

Due to adjacent two negativesBetween the energy signals CKHB, the sum of the holding time a of the first transition signal CKHC1 and the holding time c of the second transition signal CKHC2 is a + c = d-b, then

Therefore, the sum of the maintaining time of the transition signal CKHC in the shunting control signal CKH can be properly set according to the number of the scanning lines G included in the display panel 000, that is, the number n of the rows of the sub-pixels P included in the display panel 000, and the width-to-length ratio W/L of the channel region of the switching transistor 101T in the multiplexing unit 101, so as to ensure that the maintaining time of the enable signal CKHA is sufficient, ensure that the data voltage signal Vdata can be accurately written into the sub-pixels P in sufficient time by the data line S, ensure the display quality of the display panel, and effectively save power consumption, and ensure the balance between the display quality and the power consumption.

In some alternative embodiments, please refer to fig. 4, fig. 5 and fig. 9 in combination, fig. 9 is another timing diagram of the shunting control signal in fig. 5, in which the embodiment includes at least two transition signals CKHC in the process of converting the non-enable signal CKHB into the enable signal CKHA, and the transition signals CKHC include a third transition signal CKHC3 and a fourth transition signal CKHC4;

the method comprises the steps that at least two transition signals CKHC are included in the process of converting an enable signal CKHA into a non-enable signal CKHB, and the transition signals CKHC5 and CKHC6 are respectively a fifth transition signal CKHC5 and a sixth transition signal CKHC6;

the value of the fourth transition signal CKHC4 is closer to the value of the enable signal CKHA than the value of the third transition signal CKH3, and the value of the sixth transition signal CKHC6 is closer to the value of the enable signal CKHA than the value of the fifth transition signal CKHC 5.

This embodiment explains that the shunt control signal CKH connected between two adjacent non-enable signals CKHB, i.e. the shunt control terminal 101C of the multiplexing unit 101, includes four transition signals CKHC in the process from the cut-off of the control switch transistor 101T to the next cut-off, wherein the process of converting the non-enable signal CKHB into the enable signal CKHA may include two transition signals CKHC, and respectively include a third transition signal CKHC3 and a fourth transition signal CKHC4, and the process of converting the enable signal CKHA into the non-enable signal CKHB may include two transition signals CKHC, and respectively include a fifth transition signal CKHC5 and a sixth transition signal CKHC6, wherein the value of the fourth transition signal CKHC4 is closer to the value of the enable signal CKHA than the value of the third transition signal CKH3, i.e. the process of converting the non-enable signal CKHB into the enable signal CKHA, the non-enable signal CKHB is first switched into the third transition signal CKH3, then switched into the fourth transition signal CKH 4, and then switched into the enable signal CKHC; in the process of converting the enable signal CKHA into the disable signal CKHB, the enable signal CKHA is first switched to the sixth transition signal CKHC6, then to the fifth transition signal CKHC5, and finally to the disable signal CKHB. In this embodiment, when the non-enable signal CKHB and the enable signal CKHA are set to be switched, transition is performed through the plurality of transition signals CKHC with different values, so that the maintaining signal of the transition signal CKHC can be ensured to be long enough, power consumption is further saved, and meanwhile, switching between the non-enable signal CKHB and the enable signal CKHA can be more relaxed, thereby avoiding the problem of reducing display quality caused by abrupt change of signal switching.

In some alternative embodiments, please refer to fig. 4, fig. 5 and fig. 10 in combination, fig. 10 is another timing diagram of the shunting control signals in fig. 5, in this embodiment, between two adjacent non-enable signals CKHB:

the sustain time a1 of the fourth transition signal CKHC4 is greater than the sustain time a2 of the third transition signal CKHC3, and the sustain time c1 of the sixth transition signal CKHC6 is greater than the sustain time c2 of the fifth transition signal CKHC 5.

The present embodiment explains that when the shunt control signal CKH connected between two adjacent non-enabling signals CKHB, i.e. the shunt control terminal 101C of the multiplexing unit 101, includes at least four transition signals CKHC during the process from turning off of the control switch transistor 101T to turning off next, and the non-enabling signal CKH is converted into the enabling signal CKHA including at least two transition signals CKHC of the third transition signal CKHC3 and the fourth transition signal CKHC4, and the enabling signal CKHA is converted into the non-enabling signal CKHB including at least two transition signals CKHC of the fifth transition signal CKHC5 and the sixth transition signal CKHC6, the sustain time a1 of the fourth transition signal CKHC4 is greater than the sustain time a2 of the third transition signal CKHC3, the sustain time C1 of the sixth transition signal CKHC6 is greater than the sustain time C2 of the fifth transition signal CKHC5, i.e. the transition signal CKHC is closer to the enable signal CKHA (the on-voltage of the control switch transistor 101T), and the transition signal CKHC6 is closer to the on-data signal CKHA, the data signal CKHA can be switched to the enable signal CKHA 4 when the transition signal CKHC is switched to the data signal CKHA, and the data signal CKHA 6, the data of the data switch is switched to the data signal CKHA 4, therefore, the charging time of the data line S can be approximately understood when the shunt control signal CKH is the sixth transition signal CKHC6 or the fourth transition signal CKHC4, so that the power consumption can be saved, the charging time can be further ensured, and the display quality can be improved.

It is understood that when the shunt control signal CKH in this embodiment is the sixth transition signal CKHC6 or the fourth transition signal CKHC4, it can be understood that the switching transistor 101T is already close to or approximately in the on state, although the on current may be only slightly smaller, but it still has the effect of charging the data line S with the data voltage signal Vdata during this time period.

In some alternative embodiments, with continued reference to fig. 4, 5 and 10, in the present embodiment, the value of the transition signal CKHC is not equal to Vdata- | Vth |, where Vdata is the data voltage signal and | Vth | is the threshold voltage of the switching transistor 101T.

This embodiment explains that, in the shunt control signal CKH accessed by the shunt control terminal 101C of the multiplexing circuit 10, the value of the transient signal CKH for saving panel power consumption that can be set can avoid Vdata- | Vth |, that is, the value of the transient signal CKHC is not equal to the difference between the data voltage signal Vdata and the threshold voltage | Vth | of the switching transistor 101T, so as to avoid that when the value of the transient signal CKH is equal to Vdata- | Vth |, the switching transistor 101T is in a critical on state, so that some switching transistors 101T in the multiplexing circuit 10 are turned on, and some switching transistors 101T are turned off, resulting in the difference of charging effects. Therefore, the value of the transition signal CKHC is not equal to Vdata- | Vth | in this embodiment, so that the charging uniformity of each multiplexing unit 101 can be ensured in the conversion process between the non-enable signal CKHB and the enable signal CKHA, the charging time on each data line S is further equalized as much as possible, and the display uniformity of different display panels 000 is improved.

In some optional embodiments, please refer to fig. 4, fig. 5, fig. 10 and fig. 11 in combination, fig. 11 is a schematic diagram of a circuit module connection structure in a sub-pixel provided in this embodiment, the sub-pixel P includes a pixel circuit 20 and a light emitting element 30 electrically connected, the pixel circuit 20 includes a driving transistor DT, a first light emitting control module 201, a second light emitting control module 202, a first reset module 203, a second reset module 204, a threshold compensation module 205 and a data writing module 206;

a first end of the first light emission control module 201 is electrically connected to the first power signal line PVDD, and a second end of the first light emission control module 201 is electrically connected to the first pole of the driving transistor DT;

a first terminal of the second light emission control module 202 is electrically connected to the second terminal of the driving transistor DT, and a second terminal of the second light emission control module 202 is electrically connected to the light emitting element 30;

a first end of the first reset module 203 is electrically connected to the first reset signal line REF1, and a second end of the first reset module 203 is electrically connected to the gate of the driving transistor DT;

a first end of the second reset module 204 is electrically connected to the second reset signal line REF2, and a second end of the second reset module 204 is electrically connected to the light emitting element 30;

a first terminal of the threshold compensation module 205 is electrically connected to the gate of the driving transistor DT, and a second terminal of the threshold compensation module 205 is electrically connected to the second pole of the driving transistor DT;

a first terminal of the data writing block 206 is connected to the data line S, and a second terminal of the data writing block 206 is connected to the first electrode of the driving transistor DT.

Alternatively, as shown in fig. 11 and 12, fig. 12 is a schematic diagram of a connection structure of the circuit in fig. 11, the first lighting control module 201 includes a first transistor M1, a gate of the first transistor M1 is electrically connected to the first lighting control signal line EM1, a source of the first transistor M1 is electrically connected to the first power signal line PVDD, and a drain of the first transistor M1 is electrically connected to the first pole of the driving transistor DT;

the second light emission control module 202 includes a second transistor M2, a gate of the second transistor M2 is electrically connected to the second light emission control signal line EM2, a source of the second transistor M2 is electrically connected to the second pole of the driving transistor DT, and a drain of the second transistor M2 is electrically connected to the anode of the light emitting element 30;

the data writing module 206 includes a third transistor M3, a gate of the third transistor M3 is electrically connected to the first scan signal line G1, a source of the third transistor M3 is electrically connected to the data line S, and a drain of the third transistor M3 is electrically connected to the first electrode of the driving transistor DT;

the threshold compensation module 205 includes a fourth transistor M4, a gate of the fourth transistor M4 is electrically connected to the first scanning signal line G1, a source of the fourth transistor M4 is electrically connected to the gate of the driving transistor DT, and a drain of the fourth transistor M4 is electrically connected to the second pole of the driving transistor DT;

the first reset module 203 includes a fifth transistor M5, a gate of the fifth transistor M5 is electrically connected to the second scan signal line G2, a source of the fifth transistor M5 is electrically connected to the first reset signal line REF1, and a drain of the fifth transistor M5 is electrically connected to the gate of the driving transistor DT;

the second reset module 204 includes a sixth transistor M6, a gate of the sixth transistor M6 is electrically connected to the second scan signal line G2, a source of the sixth transistor M6 is electrically connected to the second reset signal line REF2, and a drain of the sixth transistor M6 is electrically connected to the anode of the light emitting element 30; the cathode of the optional light emitting element 30 is connected to the second power signal line PVEE.

The present embodiment exemplifies an electrical connection structure of the pixel circuit 20 and the light emitting element 30 included in the sub-pixel P of the display panel 000, wherein the data writing module 206 includes a third transistor M3, a gate of the third transistor M3 is electrically connected to the first scanning signal line G1, a source of the third transistor M3 is electrically connected to the data line S, a drain of the third transistor M3 is electrically connected to the first pole of the driving transistor DT, and when the third transistor M3 is turned on under the control of the first scanning signal supplied by the first scanning signal line G1, the data voltage signal Vdata on the data line S can be transmitted to the driving transistor DT. The threshold compensation module 205 includes a fourth transistor M4, a gate of the fourth transistor M4 is electrically connected to the first scanning signal line G1, a source of the fourth transistor M4 is electrically connected to a gate of the driving transistor DT, a drain of the fourth transistor M4 is electrically connected to the second pole of the driving transistor DT, and the fourth transistor M4 can perform threshold compensation on the driving transistor DT when turned on under the control of the first scanning signal supplied from the first scanning signal line G1.

The first emission control module 201 includes a first transistor M1, a gate of the first transistor M1 is electrically connected to the first emission control signal line EM1, a source of the first transistor M1 is electrically connected to the first power signal line PVDD, a drain of the first transistor M1 is electrically connected to the first pole of the driving transistor DT, the second emission control module 202 includes a second transistor M2, a gate of the second transistor M2 is electrically connected to the second emission control signal line EM2, a source of the second transistor M2 is electrically connected to the second pole of the driving transistor DT, a drain of the second transistor M2 is electrically connected to the anode of the light emitting element 30, the first emission control signal line EM1 and the second emission control signal line EM2 may be connected together using the same emission control signal line, the first transistor M1 is turned on under the control of the emission control signal fed from the first emission control signal line EM1, the second transistor M2 is turned on under the control of the emission control signal fed from the second emission control signal line EM2, the first power signal line PVDD and the second power signal line PVEE are formed as an emission control circuit 30.

Optionally, a storage capacitor Cst may be further included between the gate of the driving transistor DT and the first power signal line PVDD in this embodiment, one end of the storage capacitor Cst is connected to the first power signal line PVDD, the other end of the storage capacitor Cst is connected to the gate of the driving transistor DT, and the storage capacitor Cst is used to stabilize the potential of the gate of the driving transistor DT, which is beneficial for the driving transistor DT to keep conducting.

The working process of the pixel circuit 20 and the light emitting element 20 electrically connected in the sub-pixel P illustrated in this embodiment may be:

in the initial reset phase, the fifth transistor M5 of the first reset module 203 and the sixth transistor M6 of the second reset module 204 are turned on, the rest of the transistors are turned off, the gate potential of the driving transistor DT is the first reset signal provided by the first reset signal line REF1, and the gate of the driving transistor DT is reset, so that the turning on of the driving transistor DT during threshold compensation can be facilitated. The anode potential of the light emitting element 30 is the second reset signal provided by the second reset signal line REF2, and the anode of the light emitting element 30 is reset, so that the anode of the light emitting element 30 is initialized, thereby improving the residual of the previous frame data signal, improving the image sticking phenomenon, and improving the display effect of the display panel 000. Optionally, the values of the first reset signal provided by the first reset signal line REF1 and the second reset signal provided by the second reset signal line REF2 may be the same or different, and in specific implementation, the values may be set according to actual requirements.

In the data writing and threshold capturing phase, the third transistor M3 of the data writing module 206, the fourth transistor M4 of the threshold compensation module 205, and the driving transistor DT are turned on, the remaining transistors are turned off, the first electrode of the driving transistor DT is the data voltage signal Vdata fed by the data line S, and the second electrode of the gate electrode of the driving transistor DT and the driving transistor DT is Vdata- | Vth |, where | Vth | is the threshold voltage of the driving transistor DT.

In the light emitting stage, the first transistor M1 of the first light emitting control module 201, the second transistor M2 of the second light emitting control module 202, and the driving transistor DT are turned on, the other transistors are turned off, the first voltage signal Vpvdd of the first power signal line PVDD is transmitted to the driving transistor DT, the driving transistor DT generates a driving current, and the light emitting element 30 is driven to emit light to drive the light emitting element to emit lightThe first electrode of the driving transistor DT is at a voltage level Vpvdd of the first voltage signal provided by the first power signal line PVDD, the gate of the driving transistor DT is at a voltage level Vdata- | Vth |, and the second electrode of the driving transistor DT is at a voltage level Vpvee + Voled, wherein Vpvee is the second voltage signal provided by the second power signal line PVEE and can be at a negative voltage level, voled is the corresponding voltage on the light emitting element 30, and the light emitting current Id = k (Vgs- | Vth |) ² ＝k(Vpvdd-Vdata-|Vth|) ² (ii) a Wherein the constant k is related to the performance of the driving transistor DT itself.

It should be noted that the transistors included in the pixel circuit 20 in this embodiment are all exemplified by P-type transistors, and in some other alternative embodiments, N-type transistors may be used, or a part of the transistors may be N-type transistors, and a part of the transistors may be P-type transistors. When the transistor is selected as a P-type transistor, the P-type transistor is turned on when the gate thereof is at a low potential, that is, when the transistor is selected as an N-type transistor, the N-type transistor is turned on when the gate thereof is at a high potential, that is, the transistor is turned on.

It should be understood that the drawings of the present embodiment are only for illustrating the electrical connection structure between the pixel circuit 20 and the light emitting element 30 included in the sub-pixel P of the display panel 000, and in practical implementation, the circuit structure in the sub-pixel P includes but is not limited thereto, and other implementation structures may also be adopted, which is not limited in the present embodiment.

In some alternative embodiments, please refer to fig. 13, where fig. 13 is a schematic plane structure diagram of a display device according to an embodiment of the present invention, and the display device 111 according to the embodiment includes the display panel 000 according to the above embodiment of the present invention. The embodiment of fig. 13 is only an example of a mobile phone, and the display device 111 is described, it is understood that the display device 111 provided in the embodiment of the present invention may be another display device 111 having a display function, such as a computer, a television, and a vehicle-mounted display device, and the present invention is not limited thereto. The display device 111 provided in the embodiment of the present invention has the beneficial effects of the display panel 000 provided in the embodiment of the present invention, and specific reference may be made to the specific description of the display panel 000 in the above embodiments, which is not described herein again.

As can be seen from the above embodiments, the display panel and the display device provided by the present invention at least achieve the following beneficial effects:

Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A display panel, comprising: the pixel structure comprises a plurality of sub-pixels, a plurality of scanning lines and a plurality of data lines, wherein the scanning lines and the data lines are crossed and insulated to define the area where the sub-pixels are located;

the display panel comprises a non-display area, the non-display area comprises a multiplexing circuit, and the multiplexing circuit comprises a plurality of multiplexing units;

the multiplexing unit comprises a signal input end, a plurality of signal output ends, a plurality of shunt control ends and a plurality of switch transistors, wherein the grid electrode of each switch transistor is connected with the shunt control end, the first pole of each switch transistor is connected with the signal input end, and the second pole of each switch transistor is connected with the signal output end; the signal input end is connected with a data voltage signal, and the signal output ends are electrically connected with the data lines in a one-to-one correspondence manner;

the shunt control end is connected with a shunt control signal, the shunt control signal comprises an enable signal, a non-enable signal and at least one transition signal, and the value of the transition signal is between the value of the enable signal and the value of the non-enable signal;

at least one of the transition signals is included in a process of converting the non-enable signal into the enable signal, and at least one of the transition signals is included in a process of converting the enable signal into the non-enable signal.

2. The display panel according to claim 1,

the multiplexing unit comprises a signal input end, M signal output ends, M shunt control ends and M switch transistors; wherein M is more than or equal to 6.

3. The display panel according to claim 1, wherein the shunt control signal comprises two adjacent non-enable signals, an interval time of the two adjacent non-enable signals is d, and a sustain time of the enable signal between the two adjacent non-enable signals is b;

at least two transition signals are included between two adjacent non-enabling signals, and are respectively a first transition signal and a second transition signal;

between two adjacent non-enable signals, the holding time of the first transition signal is a, the holding time of the second transition signal is c, and d-b = a + c.

4. A display panel as claimed in claim 3 characterized in that a = c.

5. The display panel according to claim 3,

wherein n is the number of the scan lines included in the display panel, and W/L is a width-to-length ratio of a channel region of the switching transistor.

6. The display panel according to claim 1,

the process of converting the non-enabling signal into the enabling signal comprises at least two transition signals which are respectively a third transition signal and a fourth transition signal;

the process of converting the enabling signal into the non-enabling signal comprises at least two transition signals which are respectively a fifth transition signal and a sixth transition signal;

the value of the fourth transition signal is closer to the value of the enable signal than the value of the third transition signal, and the value of the sixth transition signal is closer to the value of the enable signal than the value of the fifth transition signal.

7. The display panel according to claim 6, wherein between adjacent two of the disable signals:

the holding time of the fourth transition signal is longer than that of the third transition signal, and the holding time of the sixth transition signal is longer than that of the fifth transition signal.

8. The display panel according to claim 1, wherein the transition signal has a value not equal to Vdata- | Vth |, wherein Vdata is the data voltage signal and | Vth | is a threshold voltage of the switching transistor.

9. The display panel according to claim 1, wherein the sub-pixel includes a pixel circuit and a light emitting element which are electrically connected, the pixel circuit including a driving transistor, a first light emission control module, a second light emission control module, a first reset module, a second reset module, a threshold compensation module, and a data write module;

a first end of the first light emitting control module is electrically connected with the first power signal line, and a second end of the first light emitting control module is electrically connected with the first pole of the driving transistor;

a first end of the second light-emitting control module is electrically connected with the second pole of the driving transistor, and a second end of the second light-emitting control module is electrically connected with the light-emitting element;

the first end of the first reset module is electrically connected with a first reset signal line, and the second end of the first reset module is electrically connected with the grid electrode of the driving transistor;

a first end of the second reset module is electrically connected with a second reset signal line, and a second end of the second reset module is electrically connected with the light-emitting element;

a first end of the threshold compensation module is electrically connected with the grid electrode of the driving transistor, and a second end of the threshold compensation module is electrically connected with the second pole of the driving transistor;

the first end of the data writing module is connected with the data line, and the second end of the data writing module is connected with the first pole of the driving transistor.

10. The display panel according to claim 9,

the first light emission control module includes a first transistor, a gate of which is electrically connected to a first light emission control signal line, a source of which is electrically connected to the first power signal line, and a drain of which is electrically connected to a first pole of the driving transistor;

the second light emission control module includes a second transistor, a gate of the second transistor is electrically connected to a second light emission control signal line, a source of the second transistor is electrically connected to the second electrode of the driving transistor, and a drain of the second transistor is electrically connected to the anode of the light emitting element;

the data writing module comprises a third transistor, wherein the grid electrode of the third transistor is electrically connected with a first scanning signal line, the source electrode of the third transistor is electrically connected with the data line, and the drain electrode of the third transistor is electrically connected with the first electrode of the driving transistor;

the threshold compensation module comprises a fourth transistor, wherein the grid electrode of the fourth transistor is electrically connected with the first scanning signal line, the source electrode of the fourth transistor is electrically connected with the grid electrode of the driving transistor, and the drain electrode of the fourth transistor is electrically connected with the second pole of the driving transistor;

the first reset module comprises a fifth transistor, the grid electrode of the fifth transistor is electrically connected with the second scanning signal line, the source electrode of the fifth transistor is electrically connected with the first reset signal line, and the drain electrode of the fifth transistor is electrically connected with the grid electrode of the driving transistor;

the second reset module includes a sixth transistor, a gate of the sixth transistor is electrically connected to the second scan signal line, a source of the sixth transistor is electrically connected to the second reset signal line, and a drain of the sixth transistor is electrically connected to an anode of the light emitting element.

11. A display device characterized by comprising the display panel according to any one of claims 1 to 10.