CN115309679A - BMS slave control address allocation method, BMS master control module and BMS slave control module - Google Patents

BMS slave control address allocation method, BMS master control module and BMS slave control module Download PDF

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CN115309679A
CN115309679A CN202210922451.5A CN202210922451A CN115309679A CN 115309679 A CN115309679 A CN 115309679A CN 202210922451 A CN202210922451 A CN 202210922451A CN 115309679 A CN115309679 A CN 115309679A
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bms
address
slave
module
signal
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孙君起
田云芳
曹勇
杨大鹏
孙阳
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China Aviation Lithium Battery Co Ltd
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    • G06—COMPUTING; CALCULATING OR COUNTING
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    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
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    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • B60L58/00—Methods or circuit arrangements for monitoring or controlling batteries or fuel cells, specially adapted for electric vehicles
    • B60L58/10—Methods or circuit arrangements for monitoring or controlling batteries or fuel cells, specially adapted for electric vehicles for monitoring or controlling batteries
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M10/00—Secondary cells; Manufacture thereof
    • H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells

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Abstract

The invention belongs to the technical field of battery management systems, and particularly relates to a BMS slave control address allocation method, a BMS master control module and a BMS slave control module. The BMS slave control address allocation method comprises the following steps: the BMS master control module simultaneously sends periodic signals and self-defined address signals to a first BMS slave control module; when the first BMS slave control module receives the first level mutation time of the periodic signals, the values of the custom address signals at the level mutation times of the periodic signals with the set number are continuously read as the addresses of the corresponding slave control modules; and after the first BMS slave module address is set, processing the self-defined address signal to obtain the address for setting the next slave module, and sending the periodic signal and the processed self-defined address signal to the next BMS slave module. By the address allocation method, the problem that the address setting is influenced by the error of the sending and receiving signals when only the address signal is sent is avoided, and the accuracy of setting the slave control address is improved.

Description

BMS slave control address allocation method, BMS master control module and BMS slave control module
Technical Field
The invention belongs to the technical field of battery management systems, and particularly relates to a BMS slave control address allocation method, a BMS master control module and a BMS slave control module.
Background
The Battery Management System (BMS) is seen from the topological structure, and is divided into two types of centralized type and distributed type according to different project requirements, and the centralized type BMS collects all electric cores uniformly by one BMS hardware, is suitable for the scene with few electric cores, generally commonly appears in the scene with low capacity, low total pressure and small Battery System volume, along with the continuous development of passenger car power Battery System to the direction of high capacity, high total pressure and large volume, mainly adopts the BMS of distributed type structure on plug-in hybrid and pure electric vehicle type, and the distributed type BMS structure is managed to the group Battery by a master control and a plurality of slave control component systems. In order to realize the communication of the master module and the slave module, different addresses need to be set for each slave control.
There are three common address setting schemes for the BMS slave: 1. the slave control module solidifies the address through burning software, and each module is matched with the address before loading; 2. the hardware design stage solidifies the address, the software automatically identifies the address through the peripheral circuit of the single chip, each address corresponds to a hardware design; 3. and the slave control module performs address allocation through the CAN network and specific information. For the first scheme, the defect is that the module address is fixed, and the module has no universality; for the second scheme, the defects are that the hardware version is multiple, and the management and control are complex; with the third scheme, the defect is that the allocated address cannot be corresponded to the actual physical connection by address allocation. Therefore, the address setting schemes of the three BMS slave control modules have the problems of complex circuit, low universality, complex work engineering and low efficiency.
In order to solve the above problems, the prior art discloses a method and a system for automatically allocating BMS addresses by setting a scheme for automatically allocating BMS slave modules, for example, chinese patent publication No. CN112193125A, which realizes automatic allocation of BMS addresses from a first BMS slave to a third BMS slave by additionally providing a PWM output line and a PWM input line between adjacent BMS slaves, and simultaneously, each BMS slave processes an input first PWM signal to generate a second PWM signal for output, and writes slave plate numbers one by one in each BMS slave in a serial manner, thereby realizing battery pack system integration. However, the problem of inaccurate allocation caused by the influence of PWM sending and receiving errors exists, and the allocated addresses are allocated based on different proportions of PWM modulation, so that the duty ratio resolution is limited to a certain extent, and the number of slave control settings is also limited to a certain extent. Based on the analysis, the prior art still has the problems of inaccurate slave control address allocation and low universality.
Disclosure of Invention
The invention aims to provide a BMS slave control address allocation method, a BMS master control module and a BMS slave control module, which are used for solving the problem of inaccurate slave control address allocation in the BMS slave control address allocation in the prior art.
In order to solve the technical problem, the invention provides a BMS slave control address allocation method, which comprises the following steps:
1) When the conditions of BMS slave control address allocation are met, the BMS master control module simultaneously sends periodic signals and self-defined address signals to a first BMS slave control module;
2) When the first BMS slave control module receives the periodic signal and the self-defined address signal, the first BMS slave control module carries out address setting; the address setting of the first BMS slave module specifically includes: continuously reading the values of the custom address signals at the sudden change time of the periodic signal levels with the set number as the addresses of the corresponding slave control modules;
3) After the first BMS slave control module is completely set, the first BMS slave control module processes the self-defined address signal to obtain the address of the next slave control module, and the first BMS slave control module sends the periodic signal and the processed self-defined address signal to the next BMS slave control module.
The beneficial effects are as follows: by respectively setting the periodic signal and the user-defined address signal and acquiring the value of the user-defined address signal as the slave control address according to the periodic signal, the problem that the address setting is influenced by the error of the sending and receiving signals when only the address signal is sent is avoided, and the accuracy of setting the slave control address is improved.
Further, the self-defined address signal is a PWM signal; the low level of the PWM signal indicates an address bit having a value of 0, and the high level of the PWM signal indicates an address bit having a value of 1. The self-defined address signal is set to be PWM, the high level and the low level of the PWM signal are used for representing the value of the address bit, the slave control address is set in a digital transmission mode, the slave control address distribution process is not based on duty ratio, and the condition that the slave control number is limited due to the fact that the duty ratio resolution ratio is limited and accurate data can be identified by utilizing the slave control address distributed by the duty ratio under the condition that the duty ratio resolution ratio is met is avoided.
Further, the periodic signal is a square wave signal, and the signal representing one address bit in the PWM signal corresponds to one period of the square wave signal.
Further, in step 2), if the BMS slave control module detects that the first level abrupt change time of the periodic signal is a rising edge abrupt change, continuously reading PWM values at the falling edge abrupt change times of the square wave signals of a set number from the first falling edge abrupt change time of the square wave signals as addresses of the corresponding slave control modules; and if the BMS slave control module detects that the first level sudden change moment of the periodic signal is a falling edge sudden change, continuously reading PWM values at the rising edge sudden change moments of the square wave signals of a set number from the first rising edge sudden change moment of the square wave signals as addresses of the corresponding slave control modules.
Further, in the step 2), if the address setting fails, the BMS slave control module sends setting failure information to the BMS master control module through the CAN message, and the BMS master control module stops address allocation; the address setting failure is: when the setting error times of the same BMS slave module address exceed the set times, the setting of the BMS slave module address fails; the BMS slave module address setting error comprises unreasonable address set by the BMS slave module. In the address allocation process, the BMS slave control module sends the setting failure information to the BMS master control module, the BMS master control module can accurately determine slave control serial numbers with failed address setting, and stop address allocation in time, the problem that the accuracy of addresses allocated subsequently is low due to address allocation after one BMS slave control address setting fails is solved, the error rate of the whole BMS slave control is reduced, the error probability of the times is set for each slave control through master control, the condition that the address setting is wrong due to accidental factors is avoided, the success rate of the allocation of each slave control address is improved, the success rate of the allocation of the whole slave control address is improved, the address data has corresponding rules, for example, if the range of the address data is 0000-0111, but if the set address is 1000, the set address is unreasonable at the moment.
Further, before the BMS main control module stops address allocation, judging the setting error times of the BMS slave module block address, and when the setting error times of the BMS slave module block address exceeds the set times, stopping the address allocation of the BMS main control module; otherwise, the BMS slave control module sends periodic signals and self-defined address signals again.
Further, before the BMS slave module sends the periodic signal and the custom address signal again, it waits for a preset time interval. By setting the idle time interval, data interleaving caused by continuous data sending is avoided, data stability is enhanced, the condition that the obtained data is inaccurate is avoided, data transmission is not affected, the data accuracy is improved, and the accuracy of address allocation is ensured.
Further, after the last BMS slave control module address is set, the address set by the BMS slave control module is sent to the BMS main control module, the BMS main control module judges whether the received address is correct according to the number of the BMS slave control modules, if the received address is correct, all the BMS slave control addresses are set successfully, and the normal working mode is entered. And final judgment is carried out through the master control module, and the fact that the setting of the slave control address of the BMS is correct when the BMS enters a normal working mode is ensured.
Further, in step 1), the conditions for BMS slave address assignment include: the BMS slave control number is not consistent with the BMS slave control number stored in the BMS master control or the BMS slave control address is not unique. By carrying out address allocation when the conditions are met, the process of carrying out address allocation again on the system with the address allocation completed is avoided, the time for the system with the address allocation completed to enter normal work is further reduced, and the problems of energy waste and time waste caused by allocation errors after allocation are avoided.
In order to solve the technical problem, the invention also provides a BMS master control module which simultaneously sends periodic signals and self-defined address signals to a first BMS slave control module when the conditions of the BMS slave control address distribution are met; the periodic signal and the custom address signal are used for setting the address of the BMS slave control module after being received by the first BMS slave control module: and continuously reading the values of the custom address signals at the abrupt change time of the periodic signal levels with the set number as the addresses of the corresponding slave control modules.
The BMS master control module has the advantages that the BMS master control module sends the periodic signals and the self-defined address signals to the BMS slave control module together, so that the BMS master control module can set addresses according to the two signals, the problem that the addresses are influenced by errors of sending and receiving signals when only the address signals are sent is avoided, and the accuracy of setting the slave control addresses is improved.
Further, the self-defining signal is a PWM signal; the low level of the PWM signal represents an address bit having a value of 0, and the high level of the PWM signal represents an address bit having a value of 1. The self-defined address signal is set to be PWM, the high level and the low level of the PWM signal are used for representing the value of the address bit, the slave control address is set in a digital transmission mode, the slave control address distribution process is not based on the duty ratio, and the condition that the slave control number is limited due to the fact that the duty ratio resolution ratio is limited because the slave control address is distributed by the duty ratio and accurate data can be identified under the condition that the duty ratio resolution ratio is met is avoided.
Further, the periodic signal is a square wave signal, and the PWM signal indicates that a time interval occupied by one address bit data corresponds to one period of the square wave signal.
Further, if the setting of the BMS slave module address fails, receiving a setting failure message sent by the BMS slave module through a CAN message, and stopping address allocation; the address setting failure is: when the setting error times of the same BMS slave module address exceed the set times, the setting of the BMS slave module address fails; the BMS slave module address setting error comprises unreasonable address set by the BMS slave module. When the address setting fails, the process of stopping address allocation is controlled through the BMS main control module, after the BMS slave control address setting fails, address allocation is continued, the problem of low address accuracy of follow-up allocation is caused, the error rate of the whole BMS slave control is reduced, the error probability of the number of times is set for each slave control through the main control, the condition of error in address setting caused by accidental factors is avoided, the success rate of allocation of each slave control address is improved, the success rate of allocation of the whole slave control address is improved, address data has corresponding rules, for example, the range of the address data is 0000-0111, but when 1000 addresses are set, the set addresses are unreasonable at the moment.
Further, before the BMS main control module stops address allocation, judging the setting error times of the BMS slave module block address, and stopping address allocation when the setting error times of the BMS slave module block address exceeds the set times; otherwise, the BMS slave control module sends periodic signals and self-defined address signals again.
Further, before the BMS slave module sends the periodic signal and the custom address signal again, it waits for a preset time interval. By setting the idle time interval, data staggering caused by continuous data sending is avoided, data stability is enhanced, the condition that the obtained data are inaccurate is avoided, data transmission is not affected, the data accuracy is improved, and the accuracy of address allocation is ensured.
And further, after the last BMS slave module address is set, receiving the address set by the BMS slave module, judging whether the received address data is correct according to the number of the BMS slave modules, if so, successfully setting all the BMS slave module addresses, and entering a normal working mode. And the final judgment is carried out through the main control module, and the setting of the BMS slave control address is correct when the BMS enters a normal working mode.
Further, the conditions of the BMS slave address allocation include: the BMS slave control number is not consistent with the BMS slave control number stored in the BMS master control or the BMS slave control address is not unique. When the conditions are met, the BMS master control module starts the address allocation process, the process of performing address allocation on the system with the completed address allocation is avoided, the time for the system with the completed address allocation to enter normal work is further reduced, and the problems that energy is wasted and time is wasted due to allocation errors are solved.
In order to solve the technical problem, the invention also provides a BMS slave control module which carries out address setting according to the received periodic signal and the self-defined address signal; the address setting specifically includes: continuously reading the values of the custom address signals at the abrupt change time of the periodic signal levels with a set number as the addresses of the corresponding slave control modules;
after the address setting is finished, processing the self-defined address signal to obtain the address of the next slave control module; and sending the periodic signal and the processed custom address signal to the next BMS slave control module.
The BMS slave control module has the advantages that the BMS slave control module receives the periodic signals and the self-defined address signals, and the value of the self-defined address signals is obtained according to the periodic signals and is used as the slave control address, so that the problem that the address setting is influenced by the error of the sending and receiving signals when only the address signals are sent is avoided, and the accuracy of setting the slave control address is improved.
Further, the self-defining signal is a PWM signal; the low level of the PWM signal indicates an address bit having a value of 0, and the high level of the PWM signal indicates an address bit having a value of 1. The self-defined address signal is set to be PWM, the high level and the low level of the PWM signal are used for representing the value of the address bit, the slave control address is set in a digital transmission mode, the slave control address distribution process is not based on the duty ratio, and the condition that the slave control number is limited due to the fact that the duty ratio resolution ratio is limited because the slave control address is distributed by the duty ratio and accurate data can be identified under the condition that the duty ratio resolution ratio is met is avoided.
Further, the periodic signal is a square wave signal, and the signal representing one address bit in the PWM signal corresponds to one period of the square wave signal.
Further, if it is detected that the first level abrupt change time of the periodic signal is a rising edge abrupt change, continuously reading PWM values at the falling edge abrupt change times of the square wave signals in a set number from the first falling edge abrupt change time of the square wave signals as addresses of corresponding slave control modules; and if the first level abrupt change moment of the periodic signal is detected to be a falling edge abrupt change, continuously reading PWM values at the rising edge abrupt change moments of the square wave signals of a set number from the first rising edge abrupt change moment of the square wave signals as addresses of corresponding slave control modules.
Further, if the address setting fails, sending setting failure information to the BMS main control module through the CAN message, and stopping address allocation by the BMS main control module; the address setting failure is: when the error setting times of the slave module address of the same BMS exceed the set times, the setting of the slave module address of the BMS fails; the BMS slave module address setting error comprises unreasonable address set by the BMS slave module. When the address setting fails, the process of stopping address allocation is controlled by the BMS master control module, the problem that the accuracy of subsequently allocated addresses is low due to the fact that address allocation continues after the setting of one BMS slave control address fails is avoided, the error rate of the whole BMS slave control is further reduced, the error probability of the number of times is set for each slave control through the master control, the situation that address setting errors are caused due to accidental factors is avoided, the success rate of the allocation of each slave control address is improved, the success rate of the allocation of the whole slave control address is further improved, address data have corresponding rules, for example, if the range of the address data is 0000-0111, but if the set address is 1000, the set address is unreasonable at the moment.
And further, the address set by the last BMS slave control module is sent to the BMS master control module so that the BMS master control module can judge whether the received address data is correct according to the number of the BMS slave control modules, and if the address data is correct, all the BMS slave control addresses are successfully set to enter a normal working mode. Periodic signals and custom address signals corresponding to the last BMS slave control module are sent to the BMS master control module through the last BMS slave control module, the accuracy of address data is judged by the BMS master control module, namely, final judgment is carried out through the master control module, and it is ensured that when a normal working mode is entered, the setting of the BMS slave control address is correct.
Drawings
Fig. 1 is a block diagram of a BMS slave address allocation method, a BMS master control module, and an allocation system of the BMS slave control module according to the present invention;
fig. 2 is a BMS address allocation data timing diagram of the BMS slave control address allocation method, the BMS master control module, and the BMS slave control module according to the present invention;
fig. 3 is a power-on flow chart of the BMS slave control address allocation method, the BMS master control module and the BMS slave control module according to the present invention;
fig. 4 is a flow chart of the address allocation of the BMS slave control address allocation method, the BMS master control module and the BMS slave control module according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clear, the present invention is further described in detail with reference to the accompanying drawings and embodiments.
The embodiment of the BMS slave control address allocation method comprises the following steps:
the distributed BMS architecture manages the battery pack by a master control and a plurality of slave control forming systems, different addresses need to be set for each slave control in order to realize communication between the master and the slave modules, and in order to realize automatic allocation of BMS slave module addresses and improve allocation accuracy, the following BMS slave control address allocation method processes are designed:
as shown in fig. 1, there are one BMS master control module and n BMS slave control modules, wherein the connection manner of the BMS master control and the BMS slave control is: the DO1 port of the BMS master control is connected with the DI1 port of the BMS slave control 1 and used for transmitting the PWM1 signal (namely, the periodic signal) sent by the BMS master control to the BMS slave control 1, and the DO2 port of the BMS master control is connected with the DI2 port of the BMS slave control 1 and used for transmitting the PWM2 signal (namely, the self-defined address signal) sent by the BMS master control to the BMS slave control 1; the DO1 port of the BMS slave 1 is connected with the DI1 port of the BMS slave 2, and is used for transmitting the PWM1 signal sent by the BMS slave 1 to the BMS slave 2, the DO2 port of the BMS slave 1 is connected with the DI2 port of the BMS slave 2, and is used for transmitting the PWM2 signal sent by the BMS slave 1 to the BMS slave 1; like the connection mode of the BMS slave 1 and the BMS slave 2, the BMS slave 1, the BMS slave 2 and the BMS slave 3, \8230, the BMS slave n are sequentially connected; the DO1 port of the BMS slave controller n is connected with the DI1 port of the BMS master controller and used for transmitting the PWM1 signal sent by the BMS slave controller n to the BMS master controller, and the DO2 port of the BMS slave controller n is connected with the DI2 port of the BMS master controller and used for transmitting the PWM2 signal sent by the BMS slave controller n to the BMS master controller; in addition, each BMS slave control is connected with the BMS master control through a CAN bus and used for sending CAN messages to the BMS master control by the BMS slave control. Based on the line connection, the BMS slave control address allocation method comprises the following steps:
1. as shown in fig. 3, after power is on, all BMS slave control data are called up and measured by the BMS master control CAN messages, the BMS master control judges whether the BMS slave control addresses are unique through the slave control addresses, and simultaneously judges whether the number of the BMS slave controls is consistent with the number of the system set slave controls, and when the slave control addresses are unique and consistent, the BMS master control enters a normal working mode. Otherwise, the BMS master controller sends PWM1 and PWM2 signals to the BMS slave controller 1, and the BMS slave controller enters a slave controller address allocation mode. Through after the electricity is gone up, carry out the process of whether need carry out the slave accuse address allocation earlier (judge whether satisfy the condition that BMS slave accuse address allocation promptly), and just carry out the allocation of BMS slave accuse address when needs, through when satisfying the condition, just carry out address allocation, avoid carrying out the process of address allocation once more to the system that address allocation was accomplished, and then reduced the time that the system that has accomplished address allocation got into normal work, and when avoiding once more allocating after having allocated, cause the energy waste, and once more allocate the problem that the mistake caused the waste of time. As another embodiment, the slave address may be directly allocated after power-on.
2. When the conditions of slave address allocation of the BMS are met, an address allocation flow is entered, as shown in fig. 4, the BMS master DO1 outputs a PWM1 signal of 1kHz, the DO2 outputs a PWM2 signal of 8-bit data indicating a set address (transmission data bits are not limited to 8 bits and can be extended according to practical applications), and the time interval of PWM2 transmitting the 1-bit address bit data corresponds to one cycle of the PWM1 signal (i.e., if the PWM2 address transmission is binary transmission, the time for the PWM2 to transmit 1-bit information is 0.001 s), for example, as shown in fig. 2, when the PWM1 and PWM2 are in a high level state and the address is set, the PWM1 changes from the high level to the low level first and the PWM2 starts to output the address data (as other embodiments, when the PWM1 and PWM2 can also be in a low level state when the address is not set, when the address is set, the PWM1 changes from the low level to the high level first and the PWM2 starts to output the address data; when the address is set, the PWM1 and PWM2 changes from the high level to the high level first and the low level (or the high level) first and the PWM2 changes to the high level) and the address data (the PWM1 and the high level) and the PWM 2) simultaneously, and the address 1 and the PWM2 starts to output the address data).
3. The BMS slave control 1 acquires an address according to the PWM1 signal and the PWM2 signal respectively received by the DI1 port and the DI2 port, and the address acquisition method comprises the following steps: the BMS slave controller 1 starts to acquire address data after receiving a first level mutation moment of a PWM1 signal, reads a PWM2 value from a first falling edge mutation moment of the PWM1 if the first level mutation is a rising edge mutation, and continuously reads a set number of PWM2 values at the falling edge moments of the PWM1 as the address of the BMS slave controller 1; and if the first level mutation is a falling edge mutation, reading the value of PWM2 from the first rising edge mutation moment of PWM1, and continuously reading the values of PWM2 at the rising edge moments of PWM1 with set number as the address of the BMS slave controller 1. For example, if the signal received by the BMS slave 1 is the signal shown in fig. 2, the data of PWM2 is read at the time of the rising edge of PWM1, and 8 data are sequentially read as the addresses of the BMS slave 1, that is, if the values of consecutive 8 PWM2 read by the BMS slave 1 when PWM1 is the rising edge are 0101000, the slave 1 sets its own address to 0x50, that is, decimal 80.
4. And after the address is acquired, setting the address, judging whether the address is successfully set, if the setting of the BMS slave controller 1 is successful, continuously processing the signal by the BMS slave controller 1, and transmitting a new signal to the BMS slave controller 2. The signal processing process comprises the following steps: and adding a set value x to the acquired address data to form new address data, and setting the new address data as corresponding PWM1 signals and PWM2 signals. In the embodiment, in consideration of the universality of address allocation, if x is set to 1, namely, set to the minimum increment value, the number of addresses set in this way is larger, the universality is stronger, and as other real-time ways, x can be set to any value which can meet the number of slave controllers of the BMS.
If the BMS slave controller 1 fails to set the address, the BMS slave controller 1 outputs the address setting failure information to the BMS master controller through the CAN, and the BMS master controller stops address allocation and enters an error state. In the address distribution process, the BMS slave control module sends the setting failure information to the BMS master control module, so that the BMS master control module can accurately determine the slave control sequence number of the address setting failure and stop address distribution in time, the problem of low address accuracy of follow-up distribution caused by address distribution after the failure of setting of a BMS slave control address is avoided, and the error rate of the whole BMS slave control is reduced. In the embodiment, the contingency of address setting errors is also considered, namely, after the address setting failure of the slave control 1 of the BMS is that the number of times of address setting errors of the slave control 1 of the BMS exceeds the set number of times, the address setting failure is judged, after the address setting failure of the slave control 1 of the BMS, whether the number of times of the setting errors exceeds the set number of times (for example, 3 times) is judged, when the number of times of the errors does not exceed 3 times, the BMS master control continues to send a PWM1 signal and a PWM2 signal to the slave control 1 of the BMS, the BMS slave control 1 continues the address acquisition process, and when the number of times of address failure of the slave control 1 of the BMS is 4 times, the address setting failure of the slave control 1 of the BMS is stopped, and the BMS master control stops address allocation and enters an error state. The master control allocates the address to each slave control for 3 error opportunities, namely 4 opportunities to each slave control, so that the success rate of allocation of each slave control address is improved, and the success rate of allocation of the whole slave control address is further improved. In order to ensure the success rate of the slave address allocation of the BMS, when the same BMS is slave-controlled to transmit signals for multiple times, after a set idle time interval T (for example, at least one cycle time of PWM1, i.e., 0.001ms, and considering the communication channel utilization rate, the idle time interval is set to any value from one cycle time of PWM1 to a set number (i.e., 8) of cycle times), the BMS slave-control continues to transmit the PWM1 signal and the PWM2 signal.
5. The BMS receives the PWM1 signal and the PWM2 signal from the DI1 port and the DI2 port from the slave 2, and performs the same address acquisition as the BMS receives from the slave 1 (if the signal received from the slave 1 by the BMS is the signal shown in fig. 2, after the BMS successfully acquires the address from the slave 2, the address is 0x51, that is, decimal 81), and determines whether the address setting is successful, and if the setting is successful, processes the signal and transmits the processed signal to the BMS slave 3, and each BMS slave sequentially performs the signal reception, address acquisition, and address setting success, and if the setting is successful, processes the signal and transmits the processed signal until the BMS slave n processes the signal, and transmits the processed PWM1 and PWM2 to the BMS master.
In order to ensure the correctness of setting of the slave control address of the BMS, the BMS master control further performs final judgment, the BMS master control module performs address acquisition after receiving the PWM2 signal and the PWM1 signal, and judges whether a difference value between the acquired address and the sent address is equal to n × x, if so, the setting of the slave control address of the BMS succeeds, and if not, the setting of the slave control address of the BMS fails, for example, the PWM1 signal and the PWM2 signal sent by the BMS master control are as shown in fig. 2, a set value x =1, and the number n =5 of the slave control of the BMS, the BMS slave control address from 1 address to 5 address sequentially: 80. 81, 82, 83, 84, the data received by the BMS master is 85, 85-80=1 × 5, so if the data received by the BMS master is 85, the BMS slave completes the address allocation, the master and the slave stop outputting the addresses, and the system enters a normal operation mode.
The process of distributing the slave control addresses of the BMS by using the PWM1 signal and the PWM2 signal avoids the problem that the address setting is influenced by the error of the sending and receiving signals when only the address signal is sent, the accuracy of the address setting is improved, the address is set in the form of data transmission of an I/O port, the stability of the address distribution is improved, the slave control addresses can be automatically distributed according to the wiring sequence (physical position) without human participation, the address signal PWM2 is subjected to set value increasing processing through the method, the duty ratio of the PWM2 signal is not changed, the condition that the number of the slave control addresses is limited by the address distribution due to the limitation of the duty ratio resolution is avoided, the universality of the address distribution is improved, namely, the automatic distribution of the slave control addresses is realized until the nth BMS slave control module finishes the set processing (namely the last first BMS slave control module finishes the address distribution), and the distribution accuracy and the universality are high.
BMS master control module embodiment:
as shown in fig. 1, the BMS slave module of the present invention includes: the controller comprises a DO1 port, a DO2 port, a DI1 port and a DI2 port, wherein the DO1 port of the BMS master control is connected with the DI1 port of the BMS slave control 1 and is used for transmitting a PWM1 signal sent by the BMS master control to the BMS slave control 1, the DO2 port of the BMS master control is connected with the DI2 port of the BMS slave control 1 and is used for transmitting a PWM2 signal sent by the BMS master control to the BMS slave control 1; the DO1 port of the BMS slave controller n is connected with the DI1 port of the BMS master controller and used for transmitting the PWM1 signal sent by the BMS slave controller n to the BMS master controller, and the DO2 port of the BMS slave controller n is connected with the DI2 port of the BMS master controller and used for transmitting the PWM2 signal sent by the BMS slave controller n to the BMS master controller; the BMS slave control module further comprises a signal processor, in addition, each BMS slave control is connected with the BMS master control through a CAN bus and used for the BMS slave control to send CAN messages to the BMS master control, the BMS master control module based on the setting is used for realizing the process of the BMS slave control address allocation method, the process of the BMS slave control address allocation method is clear enough in the embodiment of the BMS slave control address allocation method, and the description is omitted.
BMS slave control module embodiment:
as shown in fig. 1, the BMS slave module of the present invention includes: the system comprises a DO1 port, a DO2 port, a DI1 port and a DI2 port, wherein the DO1 port of the BMS master control is connected with the DI1 port of the BMS slave control 1, the DO2 port of the BMS master control is connected with the DI2 port of the BMS slave control 1 and used for transmitting a PWM1 signal sent by the BMS master control to the BMS slave control 1, and the DO2 port of the BMS master control is connected with the DI2 port of the BMS slave control 1 and used for transmitting a PWM2 signal sent by the BMS master control to the BMS slave control 1; the DO1 port of the BMS slave 1 is connected with the DI1 port of the BMS slave 2, and is used for transmitting the PWM1 signal sent by the BMS slave 1 to the BMS slave 2, the DO2 port of the BMS slave 1 is connected with the DI2 port of the BMS slave 2, and is used for transmitting the PWM2 signal sent by the BMS slave 1 to the BMS slave 1; like the connection mode of the BMS slave 1 and the BMS slave 2, the BMS slave 1, the BMS slave 2 and the BMS slave 3, \8230, the BMS slave n are sequentially connected; the DO1 port of the BMS slave controller n is connected with the DI1 port of the BMS master controller and used for transmitting the PWM1 signal sent by the BMS slave controller n to the BMS master controller, and the DO2 port of the BMS slave controller n is connected with the DI2 port of the BMS master controller and used for transmitting the PWM2 signal sent by the BMS slave controller n to the BMS master controller; in addition, each BMS slave control is connected with the BMS master control through a CAN bus for the BMS slave control to send a CAN message to the BMS master control, the BMS slave control module further comprises a signal processor, the BMS slave control module based on the setting is used for realizing the process of the BMS slave control address allocation method, the process of the BMS slave control address allocation method is clear enough in the embodiment of the BMS slave control address allocation method, and the description is omitted here.
The above description is only a preferred embodiment of the present invention, and not intended to limit the present invention, the scope of the present invention is defined by the appended claims, and all structural changes that can be made by using the contents of the description and the drawings of the present invention are intended to be embraced therein.

Claims (23)

1. A BMS slave control address allocation method is characterized by comprising the following steps:
1) When the conditions of BMS slave control address allocation are met, the BMS master control module simultaneously sends periodic signals and self-defined address signals to a first BMS slave control module;
2) When the first BMS slave control module receives the periodic signal and the self-defined address signal, the first BMS slave control module carries out address setting; the address setting of the first BMS slave module specifically includes: continuously reading the values of the custom address signals at the sudden change time of the periodic signal levels with the set number as the addresses of the corresponding slave control modules;
3) After the first BMS slave control module is completely set, the first BMS slave control module processes the self-defined address signal to obtain the address of the next slave control module, and the first BMS slave control module sends the periodic signal and the processed self-defined address signal to the next BMS slave control module.
2. The BMS slave address allocation method according to claim 1, characterized in that the custom address signal is a PWM signal; the low level of the PWM signal indicates an address bit having a value of 0, and the high level of the PWM signal indicates an address bit having a value of 1.
3. The BMS slave address allocation method according to claim 2, characterized in that said periodic signal is a square wave signal and the signal representing one address bit in the PWM signal corresponds to one period of the square wave signal.
4. The BMS slave address allocation method according to claim 3, wherein in step 2), if the BMS slave module detects that the first level abrupt change time of the periodic signal is a rising edge abrupt change, continuously reading PWM values at the falling edge abrupt change times of the square wave signals of a set number from the first falling edge abrupt change time of the square wave signals as the address of the corresponding slave module; and if the BMS slave control module detects that the first level abrupt change moment of the periodic signal is a falling edge abrupt change, continuously reading PWM values at the abrupt change moments of the rising edges of the square wave signals of a set number from the first rising edge abrupt change moment of the square wave signals as addresses of the corresponding slave control modules.
5. The BMS slave address allocation method according to claim 1, wherein in step 2), if the address setting fails, the BMS slave control module sends setting failure information to the BMS master control module through a CAN message, and the BMS master control module stops address allocation; the address setting failure is: when the setting error times of the same BMS slave module address exceed the set times, the setting of the BMS slave module address fails; the BMS slave module address setting error comprises unreasonable address set by the BMS slave module.
6. The BMS slave address allocation method according to claim 5, wherein before the BMS master control module stops address allocation, the BMS slave module address setting error times are judged, and when the BMS slave module address setting error times exceed the set times, the BMS master control module stops address allocation; otherwise, the BMS slave control module sends periodic signals and self-defined address signals again.
7. The BMS slave address allocation method according to claim 6, wherein said sending the periodic signal and the custom address signal again to the BMS slave module comprises waiting for a preset time interval.
8. The BMS slave address allocation method according to claim 1, wherein after the last BMS slave module address is set, the address set by the BMS slave module is transmitted to the BMS master control module, the BMS master control module determines whether the received address is correct according to the number of the BMS slave modules, if so, the setting of all BMS slave module addresses is successful, and the BMS master control module enters the normal operation mode.
9. The BMS slave address allocation method according to claim 1, characterized in that in step 1), the conditions for BMS slave address allocation include: the BMS slave control number is not consistent with the BMS slave control number stored in the BMS master control or the BMS slave control address is not unique.
10. The BMS master control module is characterized in that when the condition of BMS slave control address allocation is met, a periodic signal and a self-defined address signal are simultaneously sent to a first BMS slave control module; the periodic signal and the custom address signal are used for setting the address of the BMS slave control module after being received by the first BMS slave control module: and continuously reading the values of the custom address signals at the abrupt change time of the periodic signal levels with the set number as the addresses of the corresponding slave control modules.
11. The BMS host control module of claim 10, wherein the custom signal is a PWM signal; the low level of the PWM signal indicates an address bit having a value of 0, and the high level of the PWM signal indicates an address bit having a value of 1.
12. The BMS control module according to claim 11, wherein the periodic signal is a square wave signal, and wherein the signal representing an address bit in the PWM signal corresponds to one period of the square wave signal.
13. The BMS management module according to claim 10, wherein if the BMS slave module fails to perform the setting, the receiving BMS slave module sends a setting failure message through the CAN message, and stops the address allocation; the address setting failure is: when the setting error times of the same BMS slave module address exceed the set times, the setting of the BMS slave module address fails; the BMS slave module address setting error comprises unreasonable address set by the BMS slave module.
14. The BMS control module according to claim 13, wherein the BMS control module determines a BMS slave module block address setting error number before stopping the address allocation, and stops the address allocation when the BMS slave module block address setting error number exceeds the set number; otherwise, the slave control module of the BMS sends periodic signals and self-defined address signals again.
15. The BMS master control module according to claim 14, wherein said sending the periodic signals and the custom address signals again to this BMS slave control module comprises waiting a preset time interval.
16. The BMS controlling module according to claim 10, wherein when the last BMS slave module block address is set, the address set by the BMS slave module is received, and whether the received address is correct is determined according to the number of the BMS slave modules, and if so, all the BMS slave module block addresses are successfully set, and the normal operation mode is entered.
17. The BMS master control module according to claim 10, wherein the conditions of the BMS slave address allocation include: the BMS slave control number is not consistent with the BMS slave control number stored in the BMS master control or the BMS slave control address is not unique.
18. A BMS slave module is characterized in that address setting is carried out according to received periodic signals and self-defined address signals; the address setting specifically includes: continuously reading the values of the custom address signals at the abrupt change time of the periodic signal levels with a set number as the addresses of the corresponding slave control modules;
after the address setting is finished, processing the self-defined address signal to obtain the address of the next slave control module; and sending the periodic signal and the processed custom address signal to the next BMS slave control module.
19. The BMS slave module according to claim 18, characterized in that the custom signal is a PWM signal; the low level of the PWM signal indicates an address bit having a value of 0, and the high level of the PWM signal indicates an address bit having a value of 1.
20. The BMS slave module according to claim 19, characterized in that the periodic signal is a square wave signal and the signal representing one address bit in the PWM signal corresponds to one period of the square wave signal.
21. The BMS slave module according to claim 20, characterized in that if it is detected that the first level transition moment of the periodic signal is a rising edge transition, the PWM values at the falling edge transition moments of a set number of square signals are read continuously from the first falling edge transition moment of the square signals as the addresses of the corresponding slave modules; and if the first level abrupt change moment of the periodic signal is detected to be a falling edge abrupt change, continuously reading PWM values at the rising edge abrupt change moments of the square wave signals of a set number from the first rising edge abrupt change moment of the square wave signals as addresses of corresponding slave control modules.
22. The BMS slave module according to claim 18, characterized in that if the address setup fails, a setup failure message is sent to the BMS master module via the CAN message, and the BMS master module stops the address assignment; the address setting failure is: when the setting error times of the same BMS slave module address exceed the set times, the setting of the BMS slave module address fails; the BMS slave module address setting error comprises unreasonable address set by the BMS slave module.
23. The BMS slave module according to claim 18, wherein the address set by the last BMS slave module is sent to the BMS master module for the BMS master module to determine whether the received address is correct according to the number of the BMS slave modules, and if so, all the BMS slave addresses are successfully set to enter the normal operation mode.
CN202210922451.5A 2022-08-02 2022-08-02 BMS slave control address allocation method, BMS master control module and BMS slave control module Pending CN115309679A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116916374A (en) * 2023-09-13 2023-10-20 羿动新能源科技有限公司 Wireless BMS channel quality evaluation method and system for power battery

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116916374A (en) * 2023-09-13 2023-10-20 羿动新能源科技有限公司 Wireless BMS channel quality evaluation method and system for power battery
CN116916374B (en) * 2023-09-13 2024-01-26 羿动新能源科技有限公司 Wireless BMS channel quality evaluation method and system for power battery

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