CN115296785A - Scrambler synchronization method and device and electronic equipment - Google Patents
Scrambler synchronization method and device and electronic equipment Download PDFInfo
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- CN115296785A CN115296785A CN202211225343.9A CN202211225343A CN115296785A CN 115296785 A CN115296785 A CN 115296785A CN 202211225343 A CN202211225343 A CN 202211225343A CN 115296785 A CN115296785 A CN 115296785A
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Abstract
The invention provides a scrambler synchronization method, a scrambler synchronization device and electronic equipment, wherein an original 3-element code stream is generated by preprocessing a collected analog signal, and the characteristics of the collected analog signal can be better represented by the original 3-element code stream; demultiplexing the original 3-element code stream to generate 4 demultiplexed 3-element code streams, reducing the rate of the original 3-element code stream through demultiplexing, and obtaining 4 demultiplexed 3-element code streams to facilitate subsequent scrambler locking judgment; performing scrambler locking judgment according to the 3-element code stream after the 4 kinds of demultiplexing; in the scrambler locking judgment, the locking judgment is simultaneously carried out on the 3-element code streams after the 4 kinds of demultiplexing, under the condition that any 3-element code stream locking judgment is successful, the scrambler synchronization is determined to be completed, and the 3-element code streams after the 4 kinds of demultiplexing do not need to be separately tried in sequence, so that the quick synchronization of the scrambler is realized.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a scrambler synchronization method, device and electronic device.
Background
Before a 100base-T1 PHY chip can communicate, a communication link needs to be established between the chips.
The first step of establishing a communication link by a 100base-T1 PHY chip is to synchronize a local scrambler, and then processes such as link synchronization judgment, chip state machine skip, data receiving/sending and the like are carried out, so how to realize fast synchronization of the scrambler is the direction of the current key research.
Disclosure of Invention
The invention provides a scrambler synchronization method, a scrambler synchronization device and electronic equipment, which are used for solving the problem of slow synchronization of scramblers and realizing quick synchronization of scramblers.
The invention provides a scrambler synchronization method, which comprises the following steps:
preprocessing the collected analog signals to generate an original 3-element code stream;
demultiplexing the original 3-element code stream to generate 4 demultiplexed 3-element code streams;
performing scrambler locking judgment according to the 3-element code stream after the 4 kinds of demultiplexing;
and in the scrambler locking judgment, simultaneously performing locking judgment on the 3-element code streams subjected to demultiplexing of 4 kinds, and determining that scrambler synchronization is completed under the condition that any locking judgment is successful.
According to the scrambler synchronization method provided by the present invention, the demultiplexing the original 3-bit code stream to generate 4 demultiplexed 3-bit code streams includes:
and carrying out parallel demultiplexing on the original 3-element code stream, and simultaneously generating 4 demultiplexed 3-element code streams.
According to the scrambler synchronization method provided by the invention, the scrambler locking judgment according to the 4 demultiplexed 3-bit code streams comprises the following steps:
performing parallel demapping on the 3-element code streams after the 4 kinds of demultiplexing to obtain corresponding 4 kinds of demapping bit streams;
and performing scrambler locking judgment according to the 4 demapping bit streams.
According to the scrambler synchronization method provided by the invention, in scrambler locking judgment, 4 demultiplexed 3-bit code streams are simultaneously subjected to locking judgment, and under the condition that any locking judgment is successful, scrambler synchronization is determined to be completed, and the method comprises the following steps:
performing 4 scrambler lock determinations simultaneously based on the 4 demapping bit streams;
and under the condition that the locking judgment of any scrambler is successful, stopping the locking judgment of the scrambler, and taking the demultiplexed 3-element code stream corresponding to the successful locking judgment of the scrambler as a synchronization result.
The invention also provides a scrambler synchronizing device, comprising:
the preprocessing module is used for preprocessing the acquired analog signals to generate an original 3-element code stream;
the demultiplexing module is used for demultiplexing the original 3-element code stream to generate 4 demultiplexed 3-element code streams;
the locking judgment module is used for carrying out scrambler locking judgment according to the 3-element code stream after the 4 kinds of demultiplexing; and in the scrambler locking judgment, simultaneously performing locking judgment on the 4 demultiplexed 3-element code streams, and determining to finish scrambler synchronization under the condition that any locking judgment is successful.
According to the scrambler synchronization device provided by the invention, the demultiplexing module is specifically used for carrying out parallel demultiplexing on the original 3-element code stream and generating 4 demultiplexed 3-element code streams at the same time.
According to the scrambler synchronization device provided by the invention, the locking judgment module comprises a plurality of demapping modules and a plurality of linear feedback shift register modules;
the multiple de-mapping modules are used for carrying out parallel de-mapping on the 3-element code streams subjected to the 4 kinds of de-multiplexing to obtain corresponding 4 kinds of de-mapping bit streams;
and the linear feedback shift register modules are used for carrying out scrambler locking judgment according to the 4 demapping bit streams.
According to the scrambler synchronization device provided by the invention, a plurality of linear feedback shift register modules are specifically used for simultaneously performing locking judgment on 4 scramblers based on the 4 demapping bit streams; and under the condition that the locking judgment of any scrambler is successful, stopping the locking judgment of the scrambler and taking the demultiplexed 3-element code stream corresponding to the successful locking judgment of the scrambler as a synchronization result.
The present invention also provides an electronic device, comprising a memory, a processor and a computer program stored in the memory and running on the processor, wherein the processor implements the steps of the scrambler synchronization method as described in any of the above when executing the computer program.
The invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the scrambler synchronization method as described in any of the above.
According to the scrambler synchronization method, the scrambler synchronization device and the electronic equipment, the acquired analog signals are preprocessed to generate the original 3-element code stream, and the characteristics of the acquired analog signals can be better represented through the original 3-element code stream; demultiplexing the original 3-bit code stream to generate 4 demultiplexed 3-bit code streams, and reducing the rate of the original 3-bit code stream through demultiplexing to obtain 4 demultiplexed 3-bit code streams so as to facilitate subsequent scrambler locking judgment; performing scrambler locking judgment according to the 3-element code stream after the 4 kinds of demultiplexing; in the scrambler locking judgment, the locking judgment is simultaneously carried out on the 3-element code streams after the 4 kinds of demultiplexing, and under the condition that any locking judgment is successful, the scrambler synchronization is determined to be completed, and the 3-element code streams after the 4 kinds of demultiplexing do not need to be sequentially and independently tried, so that the quick synchronization of the scrambler is realized.
Drawings
In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings needed for the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
Fig. 1 is a schematic flow chart of a scrambler synchronization method provided in the present invention;
FIG. 2 is a schematic diagram of a demultiplexing flow provided by the present invention;
FIG. 3 is a schematic diagram of a scrambler synchronization process provided in the present invention;
FIG. 4 is a second schematic diagram of the scrambler synchronization process provided in the present invention;
fig. 5 is a schematic structural diagram of a scrambler synchronizer provided in the present invention;
fig. 6 is a schematic structural diagram of an electronic device provided in the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The 100Base-T1 PHY chip is a Physical Layer (PHY) chip used in the civil vehicle-mounted field, and the transmitting part of the chip conforms to the IEEE Std 802.3bw (namely 100 Base-T1) standard. The physical layer of Ethernet communication is PHY chip, when two PHY chips communicate, firstly, the process of establishing link is needed, when the channel condition is in accordance with the requirement, the PHY chip judges that the current internal receiving state is in accordance with the condition of establishing link, the internal state machine carries out link locking state.
After a 100Base-T1 PHY chip is powered on, the first step of establishing a communication link by the chip is to synchronize a local scrambler, and then processes of link synchronization judgment, chip state machine jumping, data receiving/sending and the like are carried out. How to achieve scrambler fast synchronization is therefore the direction of current focus research.
To solve the above problem, the present invention provides a scrambler synchronization method, as shown in fig. 1, including:
s11, preprocessing the collected analog signals to generate an original 3-element code stream.
Specifically, the 100Base-T1 PHY chip performs preprocessing on a signal acquired in advance, wherein the preprocessing includes but is not limited to noise processing, filtering, signal hard judgment set according to preset conditions and the like, and generates an original 3-bit code stream (1D-PAM 3). The 3-element code stream comprises a plurality of 3-element codes, wherein the 3-element codes are code elements obtained based on a PAM3 coding method and correspond to three logic levels of-1, 0 and + 1.
In one example, the TA code stream and the TB code stream collected in a certain order may be preprocessed to generate an original 3-bit code stream (1D-PAM 3) with a processing clock of 66.67MHz and a transmission baud rate of 66.67 MHz.
And S12, demultiplexing the original 3-element code stream to generate 4 demultiplexed 3-element code streams.
Optionally, step S12 may specifically be:
s121, carrying out parallel demultiplexing on the original 3-element code stream, and simultaneously generating 4 demultiplexed 3-element code streams.
Specifically, the received 1D-PMA3 code with the baud rate of 66.67MHz is that the corresponding transmitting end PHY sequentially transmits the TA and TB code streams, and after receiving the TA and TB code streams, the corresponding sequence is restored to the RA and RB code streams, so that it is possible to complete synchronization of a local scrambler (LFSR).
As for the previous example, after receiving an original 3-bit code stream (1D-PAM 3) with a baud rate of 66.67MHz by a PCS layer (Physical Coding Sublayer) of a 100Base-T1 PHY chip, demultiplexing the original 3-bit code stream for subsequent local scrambler synchronization, demultiplexing the original 3-bit code stream (1D-PAM 3) with the baud rate of 66.67MHz at a reduced rate, and adjusting the original 3-bit code stream to 2 3-bit code streams (2D-PAM 3) with 33.33MHz, which are RA code stream and RB code stream, respectively, that is, the demultiplexed 3-bit code stream.
As shown in fig. 2, the original 3-ary code stream (1D-PAM 3) after TA and TB are processed is in one of two formats, i.e., format one and format two in the figure. When the original 3-element code stream (1D-PAM 3) is demultiplexed, four demultiplexed 3-element code streams are counted: the first result is a correct result, the RA code stream in the original 3-element code stream (1D-PAM 3) is correct to correspond to the TA code stream, and the RB code stream is correct to correspond to the TB code stream; the second result and the fourth result are error results, and dislocation occurs when TA code stream and/or TB code stream in original 3-element code stream (1D-PAM 3) are identified during demultiplexing; and the third result is also an error result, and the TA code stream in the original 3-bit code stream (1D-PAM 3) is corresponding to the RB code stream, the TB code stream is corresponding to the RA code stream, and opposite RA and RB code streams are generated.
And S13, carrying out scrambler locking judgment according to the 3-element code stream after the 4 kinds of demultiplexing.
Specifically, in the above example, the scrambler locking judgment may be performed according to the 3-bit code stream after the 4 kinds of demultiplexing. In one example, the scrambler lock judgment may be performed sequentially according to each demultiplexing result, that is, the demultiplexed 3-bit code stream.
And S14, in the scrambler locking judgment, simultaneously performing locking judgment on the 3-bit code stream after 4 kinds of demultiplexing, and determining to finish scrambler synchronization under the condition that any locking judgment is successful.
Specifically, as shown in the above example, when RA corresponds to TA and RB corresponds to TB, it is determined that the scrambler locking determination of the demultiplexed 3-bit code stream is successful, and at this time, scrambler synchronization is completed.
In the embodiment of the invention, the acquired analog signal is preprocessed to generate an original 3-element code stream, and the characteristics of the acquired analog signal can be better represented by the original 3-element code stream; demultiplexing the original 3-element code stream to generate 4 demultiplexed 3-element code streams, reducing the rate of the original 3-element code stream through demultiplexing, and obtaining 4 demultiplexed 3-element code streams to facilitate subsequent scrambler locking judgment; performing scrambler locking judgment according to the 3-element code stream after the 4 kinds of demultiplexing; in the scrambler locking judgment, the locking judgment is simultaneously carried out on the 3-element code streams after the 4 kinds of demultiplexing, and under the condition that any locking judgment is successful, the scrambler synchronization is determined to be completed, and the 3-element code streams after the 4 kinds of demultiplexing do not need to be sequentially and independently tried, so that the quick synchronization of the scrambler is realized.
According to the scrambler synchronization method provided by the present invention, step S13 specifically includes:
s131, parallel de-mapping is carried out on the 3-element code streams after the 4 de-multiplexing to obtain corresponding 4 de-mapping bit streams.
Wherein only the code stream after demapping can be received by the local scrambler.
Specifically, the 3-bit code stream after the 4 kinds of demultiplexing may be demapped, and mapping from three-level symbols to bits may be performed on the 3-bit code stream after the demultiplexing, so as to obtain a demapped bit stream.
And S132, performing scrambler locking judgment according to the 4 demapping bit streams.
In one example, as shown in fig. 3, the signal Rx _ data [7]Preprocessing to obtain an original 3-element code stream rx _ symb _ vector, specifically processing an original 3-element code stream (1D-PAM 3) with a clock of 66.67MHz and a baud rate of 66.67MHz, demultiplexing the original one path of the original 3-element code stream with 66.67MHz to generate two paths of demultiplexed 3-element code streams with the baud rate of 33.33MHz, namely 2D-PAM3, wherein the two paths of demultiplexed 3-element code streams comprise RA 1 RA 2 8230composed of RA n Code stream and RB 1 RB 2 RB of composition n The code stream has a processing clock frequency of 33.33MHz. De-mapping the 3-element code stream after de-multiplexing from three-level symbol to bit mapping to obtain a de-mapped bit stream Sd with the Baud rate of 33.33MHz n [2:0]Will demap the bitstream Sd n [0]And inputting the linear feedback shift register to perform scrambler locking judgment, and outputting a locking judgment result scr _ status.
Specifically, based on the example shown in fig. 2, when the original 3-bit code stream (1D-PAM 3) after TA and TB are processed is demultiplexed, four results may be generated in total, where the original 3-bit code stream is demultiplexed in parallel, and four demultiplexing results, that is, four demultiplexed 3-bit code streams are generated at the same time, and each demultiplexed 3-bit code stream is demapped at the same time, that is, the effect of parallel demapping is achieved, so that corresponding four demapping bit streams are obtained.
According to the scrambler synchronization method provided by the present invention, step S14 includes:
and S141, simultaneously performing locking judgment on 4 scramblers based on the 4 demapping bit streams.
And S142, under the condition that the locking judgment of any scrambler is successful, stopping the locking judgment of the scrambler, and taking the demultiplexed 3-element code stream successfully subjected to the locking judgment of the scrambler as a synchronization result.
Specifically, as described in the above example, scrambler locking judgment is performed on the obtained four demapped bit streams simultaneously, that is, parallel scrambler locking judgment is performed, and in the case that one scrambler is successfully locked and judged, all scrambler locking judgment is stopped, and the demultiplexed 3-bit code stream corresponding to scrambler locking judgment success is used as a synchronization result.
In one example, as shown in fig. 4, the signal Rx _ data [7]Preprocessing to obtain an original 3-element code stream rx _ symb _ vector, specifically an original 3-element code stream (1D-PAM 3) with a baud rate of 66.67MHz, demultiplexing the original 3-element code stream with the baud rate of 66.67MHz, reducing the rate of the code stream to two paths of 3-element code streams with the baud rate of 33.33MHz, and generating four demultiplexed 3-element code streams (2D-PAM 3) with the baud rate of 33.33MHz, wherein the four demultiplexed 3-element code streams are RA (random access memory) respectively n +RB n 、RB n +RA n+1 、RB n +RA n And RA n +RB n+1 The four demultiplexed 3-element code streams are subjected to demapping from three-level symbol to bit stream mapping simultaneously to obtain four demapped bit streams Sd of 33.33MHz n [2:0]De-mapping the four bit streams Sd n [0]Four Linear Feedback Shift Registers (LFSRs) of 1 to 4 are input to perform scrambler lock determination, and scrambler lock determination results scr _ status1, scr _ status2, scr _ status3, and scr _ status4 are output. Assuming that the result of scr _ status1 is successful, the scrambler lock determination of the linear feedback shift registers 2-4 is stopped, RA is applied n +RB n And the 3-element code stream (2D-PAM 3) after the demultiplexing of 33.33MHz is taken as a synchronization result, and the scrambler synchronization is completed.
In the embodiment of the invention, because the LFSR is a 33-order shift register, the three-level symbol-to-bit mapping only has limited 6 symbol mapping relations, and the required resources are less. The embodiment of the invention synchronously performs locking attempt on four code streams, so that a correct code stream sequence arrangement mode can be judged as long as one of 4 LFSRs reaches a synchronization condition, and then the synchronization process of all scramblers is closed, thereby reducing the power consumption of a chip. Under the condition of increasing few resources, the PHY receiving scrambler can be synchronized quickly, even if noise and error code interference exist, the repeated attempts are not needed, and the locking time of the PHY scrambler can be effectively reduced.
The scrambler synchronizing device provided by the present invention is described below, and the scrambler synchronizing device described below and the scrambler synchronizing method described above may be referred to in correspondence to each other. The modules of the scrambler synchronizer described below may be software modules in a computer, or may be independent physical modules, which is not limited to the above.
The present invention also provides a scrambler synchronization device, as shown in fig. 5, including:
the preprocessing module 51 is used for preprocessing the acquired analog signals to generate an original 3-element code stream;
the demultiplexing module 52 is configured to demultiplex the original 3-bit code stream to generate 4 demultiplexed 3-bit code streams;
a locking judgment module 53, configured to perform scrambler locking judgment according to the 3-bit code stream after the 4 kinds of demultiplexing; and in the scrambler locking judgment, simultaneously performing locking judgment on the 3-element code streams subjected to demultiplexing of 4 kinds, and determining that scrambler synchronization is completed under the condition that any locking judgment is successful.
In the embodiment of the invention, the acquired analog signal is preprocessed to generate an original 3-element code stream, and the characteristics of the acquired analog signal can be better represented through the original 3-element code stream; demultiplexing the original 3-bit code stream to generate 4 demultiplexed 3-bit code streams, and reducing the rate of the original 3-bit code stream through demultiplexing to obtain 4 demultiplexed 3-bit code streams so as to facilitate subsequent scrambler locking judgment; performing scrambler locking judgment according to the 3-element code stream after the 4 kinds of demultiplexing; in the scrambler locking judgment, the locking judgment is simultaneously carried out on the 3-element code streams after the 4 kinds of demultiplexing, and under the condition that any locking judgment is successful, the scrambler synchronization is determined to be completed, and the 3-element code streams after the 4 kinds of demultiplexing do not need to be sequentially and independently tried, so that the quick synchronization of the scrambler is realized.
According to the scrambler synchronization device provided by the present invention, the demultiplexing module 52 is specifically configured to perform parallel demultiplexing on the original 3-bit code stream, and generate 4 demultiplexed 3-bit code streams at the same time.
According to the scrambler synchronization device provided by the present invention, the locking judgment module 53 comprises a plurality of demapping modules 531 and a plurality of linear feedback shift register modules 532;
a plurality of demapping modules 531, configured to demap the 4 demultiplexed 3-bit code streams to obtain corresponding 4 demapped bit streams;
a plurality of linear feedback shift register modules 532 for performing scrambler lock determination according to the 4 demapped bit streams.
According to the scrambler synchronization device provided by the present invention, the plurality of linear feedback shift register modules 532 are specifically configured to perform 4 scrambler locking determinations simultaneously based on the 4 demapping bit streams; and under the condition that the locking judgment of any scrambler is successful, stopping the locking judgment of the scrambler, and taking the demultiplexed 3-element code stream corresponding to the successful locking judgment of the scrambler as a synchronization result.
Fig. 6 illustrates a physical structure diagram of an electronic device, which may include, as shown in fig. 6: a processor (processor) 610, a communication Interface (Communications Interface) 620, a memory (memory) 630 and a communication bus 640, wherein the processor 610, the communication Interface 620 and the memory 630 communicate with each other via the communication bus 640. The processor 610 may invoke logic instructions in the memory 630 to perform a scrambler synchronization method that includes: preprocessing the acquired signal to generate an original 3-element code stream; demultiplexing the original 3-bit code stream to generate a random demultiplexed 3-bit code stream; performing scrambler locking judgment according to the 3-element code stream after the 4 kinds of demultiplexing; and in the scrambler locking judgment, simultaneously performing locking judgment on the 4 demultiplexed 3-element code streams, and determining to finish scrambler synchronization under the condition that any locking judgment is successful.
In addition, the logic instructions in the memory 630 may be implemented in the form of software functional units and stored in a computer readable storage medium when the logic instructions are sold or used as independent products. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
In another aspect, the present invention also provides a computer program product, the computer program product comprising a computer program, the computer program being storable on a non-transitory computer-readable storage medium, the computer program, when executed by a processor, being capable of executing the scrambler synchronization method provided by the above methods, the method comprising:
preprocessing the collected analog signals to generate an original 3-element code stream; demultiplexing the original 3-element code stream to generate 4 demultiplexed 3-element code streams; performing scrambler locking judgment according to the 3-element code stream after the 4 kinds of demultiplexing; and in the scrambler locking judgment, simultaneously performing locking judgment on the 4 demultiplexed 3-element code streams, and determining to finish scrambler synchronization under the condition that any locking judgment is successful.
In yet another aspect, the present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored, the computer program, when being executed by a processor, is configured to perform the scrambler synchronization method provided by the above methods, the method including:
preprocessing the collected analog signals to generate an original 3-element code stream; demultiplexing the original 3-element code stream to generate 4 demultiplexed 3-element code streams; performing scrambler locking judgment according to the 3-element code stream after the 4 kinds of demultiplexing; and in the scrambler locking judgment, simultaneously performing locking judgment on the 4 demultiplexed 3-element code streams, and determining to finish scrambler synchronization under the condition that any locking judgment is successful.
The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one position, or may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, and not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A scrambler synchronization method, comprising:
preprocessing the collected analog signals to generate an original 3-element code stream;
demultiplexing the original 3-element code stream to generate 4 demultiplexed 3-element code streams;
performing scrambler locking judgment according to the 3-element code stream after the 4 kinds of demultiplexing;
and in the scrambler locking judgment, simultaneously performing locking judgment on the 3-element code streams subjected to demultiplexing of 4 kinds, and determining that scrambler synchronization is completed under the condition that any locking judgment is successful.
2. The scrambler synchronization method of claim 1, wherein the demultiplexing the original 3-bit code stream to generate 4 demultiplexed 3-bit code streams comprises:
and carrying out parallel demultiplexing on the original 3-element code stream, and simultaneously generating 4 demultiplexed 3-element code streams.
3. The method according to claim 1, wherein the performing scrambler locking judgment according to the 4 demultiplexed 3-symbol code streams comprises:
performing parallel de-mapping on the 4 de-multiplexed 3-bit code streams to obtain corresponding 4 de-mapped bit streams;
and carrying out scrambler locking judgment according to the 4 kinds of demapping bit streams.
4. The scrambler synchronization method of claim 3, wherein in scrambler lock judgment, lock judgment is performed on 4 demultiplexed 3-bit code streams at the same time, and when any lock judgment is successful, scrambler synchronization is determined to be completed, comprising:
performing 4 scrambler locking decisions simultaneously based on the 4 demapping bit streams;
and under the condition that the locking judgment of any scrambler is successful, stopping the locking judgment of the scrambler and taking the demultiplexed 3-element code stream corresponding to the successful locking judgment of the scrambler as a synchronization result.
5. A scrambler synchronization apparatus, comprising:
the preprocessing module is used for preprocessing the acquired analog signals to generate an original 3-element code stream;
the demultiplexing module is used for demultiplexing the original 3-element code stream to generate 4 demultiplexed 3-element code streams;
the locking judgment module is used for carrying out scrambler locking judgment according to the 3-element code stream after the 4 kinds of demultiplexing; and in the scrambler locking judgment, simultaneously performing locking judgment on the 3-element code streams subjected to demultiplexing of 4 kinds, and determining that scrambler synchronization is completed under the condition that any locking judgment is successful.
6. The scrambler synchronization device of claim 5, wherein the demultiplexing module is specifically configured to perform parallel demultiplexing on the original 3-bit code stream, and generate 4 demultiplexed 3-bit code streams at the same time.
7. The scrambler synchronization device of claim 5, wherein the lock determination module comprises a plurality of demapping modules and a plurality of linear feedback shift register modules;
the multiple de-mapping modules are used for performing parallel de-mapping on the 4 de-multiplexed 3-bit code streams to obtain corresponding 4 de-mapped bit streams;
and the linear feedback shift register modules are used for carrying out scrambler locking judgment according to the 4 demapping bit streams.
8. The scrambler synchronization device of claim 7, wherein a plurality of the linear feedback shift register modules are specifically configured to perform 4 scrambler lock decisions simultaneously based on the 4 demapping bit streams; and under the condition that the locking judgment of any scrambler is successful, stopping the locking judgment of the scrambler, and taking the demultiplexed 3-element code stream corresponding to the successful locking judgment of the scrambler as a synchronization result.
9. An electronic device comprising a memory, a processor and a computer program stored on the memory and run on the processor, wherein the processor when executing the computer program implements the steps of the scrambler synchronization method of any of claims 1 to 4.
10. A non-transitory computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the scrambler synchronization method of any one of claims 1 to 4.
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| CN202211225343.9A CN115296785B (en) | 2022-10-09 | 2022-10-09 | Scrambler synchronization method and device and electronic equipment |
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| CN202211225343.9A CN115296785B (en) | 2022-10-09 | 2022-10-09 | Scrambler synchronization method and device and electronic equipment |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070011534A1 (en) * | 2004-02-12 | 2007-01-11 | International Business Machines Corporation | Self-synchronising bit error analyser and circuit |
| CN103023594A (en) * | 2011-09-21 | 2013-04-03 | 中兴通讯股份有限公司 | Method for acquiring scrambler bitstream, synchronization bit scrambler and communication equipment |
| CN113115113A (en) * | 2021-03-17 | 2021-07-13 | Tcl华星光电技术有限公司 | Scrambling device and scrambling method |
| CN114760222A (en) * | 2022-06-13 | 2022-07-15 | 北京国科天迅科技有限公司 | Link disconnection detection method and device for 100base-T1 PHY chip |
| CN114844599A (en) * | 2022-06-30 | 2022-08-02 | 北京国科天迅科技有限公司 | Method and device for synchronizing scrambler |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070011534A1 (en) * | 2004-02-12 | 2007-01-11 | International Business Machines Corporation | Self-synchronising bit error analyser and circuit |
| CN103023594A (en) * | 2011-09-21 | 2013-04-03 | 中兴通讯股份有限公司 | Method for acquiring scrambler bitstream, synchronization bit scrambler and communication equipment |
| CN113115113A (en) * | 2021-03-17 | 2021-07-13 | Tcl华星光电技术有限公司 | Scrambling device and scrambling method |
| CN114760222A (en) * | 2022-06-13 | 2022-07-15 | 北京国科天迅科技有限公司 | Link disconnection detection method and device for 100base-T1 PHY chip |
| CN114844599A (en) * | 2022-06-30 | 2022-08-02 | 北京国科天迅科技有限公司 | Method and device for synchronizing scrambler |
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