CN115295500A

CN115295500A - Converter, electronic device and packaging method of converter

Info

Publication number: CN115295500A
Application number: CN202211187330.7A
Authority: CN
Inventors: 林逸程
Original assignee: Agco Microelectronics Shenzhen Co ltd
Current assignee: Agco Microelectronics Shenzhen Co ltd
Priority date: 2022-09-28
Filing date: 2022-09-28
Publication date: 2022-11-04

Abstract

The present disclosure provides a converter, an electronic device and a packaging method of the converter, which relates to the electronic technology field, wherein the converter comprises a substrate structure, including: a first insulating layer defining first and second spaces; first and second transistors embedded in the first and second spaces, respectively, and including a gate electrode, first and second electrodes; the first metal layer is positioned on one side of the first insulating layer and is connected to a first electrode of the first transistor and a second electrode of the second transistor, a first surface, away from the first metal layer, of the first insulating layer is provided with a first opening in one-to-one correspondence with a first group of electrodes, and the first group of electrodes comprise at least one of the second electrode of the first transistor, the first electrode of the second transistor and a grid electrode; and the first metal part is positioned in one first opening and is connected with the electrode corresponding to the first opening, and the area of the first opening is more than or equal to 50% of the area of the corresponding electrode. Therefore, the conduction and heat dissipation efficiency of the electrode of the transistor can be improved, and the conversion efficiency of the converter is improved.

Description

Converter, electronic device and packaging method of converter

Technical Field

The present disclosure relates to the field of electronic technologies, and in particular, to a converter, an electronic device, and a method for packaging the converter.

Background

In recent years, electronic products have been developed to be miniaturized. In this context, packages for various electronic components (e.g., converters) are also gradually tending to be miniaturized.

In the related art, in order to manufacture a miniaturized converter, a plurality of dies (Die) of the converter are stacked.

Disclosure of Invention

According to an aspect of an embodiment of the present disclosure, there is provided a converter including: a substrate structure comprising: a first insulating layer defining a first space and a second space spaced apart, a first transistor embedded in the first space, including a gate electrode, a first electrode, and a second electrode, a second transistor embedded in the second space, including a gate electrode, a first electrode, and a second electrode, and a first metal layer located at one side of the first insulating layer and connected to the first electrode of the first transistor and the second electrode of the second transistor, wherein the first insulating layer has a first surface remote from the first metal layer and a second surface close to the first metal layer, the first surface having one first opening in one-to-one correspondence with each electrode of a first group of electrodes including at least one of the second electrode of the first transistor, the first electrode of the second transistor, and the gate electrode of the second transistor; the substrate structure further includes: and the first metal part is positioned in the first opening and is connected with the electrode corresponding to the first opening, wherein the area of the first opening is more than or equal to 50% of the area of the corresponding electrode.

In some embodiments, the substrate structure further comprises a second insulating layer located on a side of the first metal layer away from the first insulating layer; the converter further comprises a control chip, wherein the control chip is located on one side, far away from the first metal layer, of the second insulating layer and is respectively connected to the grid electrode of the first transistor and the grid electrode of the second transistor.

In some embodiments, the area of the one first opening is greater than or equal to 90% of the area of the corresponding electrode.

In some embodiments, a line connecting the center point of the one first opening and the center point of the corresponding electrode is a first line, and the first line is perpendicular to the surface of the electrode corresponding to the one first opening, which is close to the one first opening.

In some embodiments, the first metal part includes: a first metal sublayer in contact with an electrode corresponding to the one first opening; and the second metal sublayer is positioned on one side, away from the electrode corresponding to the first opening, of the first metal sublayer.

In some embodiments, the second surface has at least one second opening in one-to-one correspondence with each electrode of a second set of electrodes, the second set of electrodes including at least one of a first electrode of the first transistor, a gate of the first transistor, and a second electrode of the second transistor; wherein the first metal layer includes: and the second metal part is positioned in the at least one second opening and is connected with the electrode corresponding to the at least one second opening.

In some embodiments, the at least one second opening is one second opening having an area greater than or equal to 50% of an area of the corresponding electrode.

In some embodiments, the area of the one second opening is greater than or equal to 90% of the area of the corresponding electrode.

In some embodiments, a line connecting the center point of the one second opening and the center point of the corresponding electrode is a second line perpendicular to the surface of the electrode corresponding to the one second opening near the one second opening.

In some embodiments, the first surface further has at least one third opening; the substrate structure further includes: a third metal part in the at least one third opening, connected with the first electrode of the first transistor and the second electrode of the second transistor via the first metal layer, the third metal part configured to be connected to an output terminal of the converter; wherein the first metal portion corresponding to the second electrode of the first transistor is configured to be connected to the input terminal of the converter, and the first metal portion corresponding to the first electrode of the second transistor is configured to be grounded.

In some embodiments, the second surface further has at least one fourth opening, the first metal layer further includes a fourth metal portion located in the at least one fourth opening, the substrate structure further includes a fifth metal portion extending in the first insulating layer, and the third metal portion is connected to the first metal layer via the fifth metal portion and the fourth metal portion in sequence.

In some embodiments, the first insulating layer includes a first insulating sublayer and a second insulating sublayer located at one side of the first insulating sublayer, the first insulating sublayer and the second insulating sublayer defining the first space and the second space.

In some embodiments, the second insulating layer has a third surface remote from the first metal layer, and an orthographic projection of the control chip on the third surface at least partially overlaps with an orthographic projection of at least one of the first transistor and the second transistor on the third surface.

In some embodiments, the substrate structure further comprises: and the sixth metal part is positioned on one side, far away from the first metal layer, of the second insulating layer, and is in contact with the control chip and configured to be grounded.

In some embodiments, the substrate structure further comprises: a seventh metal portion on a side of the second insulating layer away from the first metal layer, the seventh metal portion configured to be connected to an input of the converter; the converter further comprises: and the first capacitor is positioned on one side, far away from the first metal layer, of the second insulating layer, the first end of the first capacitor is connected to the sixth metal part, and the second end of the first capacitor is connected to the seventh metal part.

In some embodiments, the substrate structure further comprises: an eighth metal part including a first portion located on a side of the second insulating layer away from the first metal layer and a second portion extending in the second insulating layer, the first portion being connected to the gate of the first transistor via the second portion; wherein the control chip is connected to the gate of the first transistor via the eighth metal part.

In some embodiments, the converter further comprises: an electronic component located on a side of the control chip away from the substrate structure, including an inductor, a first end of the inductor being connected to a first electrode of the first transistor and a second electrode of the second transistor, a second end of the inductor being configured to be connected to an output of the converter.

In some embodiments, the electronic assembly further comprises: a second capacitor having a first end connected to the second end of the inductor, a second end of the second capacitor configured to be ground.

According to another aspect of the embodiments of the present disclosure, there is provided an electronic device including: a converter as in any of the above embodiments.

According to still another aspect of the embodiments of the present disclosure, there is provided a method for packaging a converter, including: providing a substrate structure comprising a first insulating layer, a first metal layer, a first transistor and a second transistor, the first and second transistors each comprising a gate, a first electrode and a second electrode, wherein the first insulating layer defines spaced apart first and second spaces, the first transistor being embedded in the first space and the second transistor being embedded in the second space, the first metal layer being located on one side of the first insulating layer and being connected to the first electrode of the first transistor and the second electrode of the second transistor; wherein the first insulating layer has a first surface remote from the first metal layer and a second surface close to the first metal layer, the first surface having one first opening in one-to-one correspondence with each electrode in a first group of electrodes including at least one of the second electrode of the first transistor, the first electrode of the second transistor, and the gate electrode of the second transistor; the substrate structure further comprises a first metal part which is located in the first opening and connected with the electrode corresponding to the first opening, wherein the area of the first opening is larger than or equal to 50% of the area of the corresponding electrode.

In some embodiments, the second surface has at least one second opening in one-to-one correspondence with each electrode of a second set of electrodes, the second set of electrodes including at least one of a first electrode of the first transistor, a gate of the first transistor, and a second electrode of the second transistor; the first metal layer comprises a second metal part which is positioned in the at least one second opening and is connected with the electrode corresponding to the at least one second opening.

In some embodiments, the substrate structure further comprises a second insulating layer located on a side of the first metal layer away from the first insulating layer; the method further comprises the following steps: and arranging a control chip on one side of the second insulating layer, which is far away from the first metal layer, wherein the control chip is respectively connected to the grid electrode of the first transistor and the grid electrode of the second transistor.

In some embodiments, providing a substrate structure comprises: forming an initial insulating layer covering the first transistor and the second transistor, wherein the initial insulating layer is provided with a first initial surface and a second initial surface; forming the one first opening on the first initial surface to obtain the first surface, and forming the first metal part filling the one first opening; forming the at least one second opening on the second initial surface to obtain the second surface, and forming the first metal layer filling the at least one second opening; and forming the second insulating layer on one side of the first metal layer far away from the first insulating layer.

In some embodiments, forming an initial insulating layer that encapsulates the first transistor and the second transistor comprises: fixing the first transistor and the second transistor at one side of a support in a spaced manner; forming a first initial insulating sub-layer on the one side of the support, the first initial insulating sub-layer having one of the first initial surface and the second initial surface; removing the support; and after removing the support, forming a second initial insulating sub-layer on a side of the first initial insulating sub-layer where the support was removed, the second initial insulating sub-layer having the other of the first initial surface and the second initial surface.

In some embodiments, the first initial insulating sublayer has the second initial surface; after forming the first metal layer, removing the support.

In some embodiments, the support is an adhesive tape.

In some embodiments, the first surface further has at least one third opening, the second surface further has at least one fourth opening, the substrate structure further comprises a third metal portion located in the at least one third opening, the first metal layer further comprises a fourth metal portion located in the at least one fourth opening, and the third metal portion is connected with the first metal layer via a fifth metal portion extending in the first insulating layer and the fourth metal portion in sequence; wherein the initial insulating layer further covers the fifth metal part.

In some embodiments, the substrate structure further comprises a sixth metal part and a seventh metal part located on a side of the second insulating layer away from the first metal layer, the sixth metal part being in contact with the control chip and configured to be grounded, the seventh metal part being configured to be connected to the input terminal of the converter; the method further comprises the following steps: and arranging a first capacitor on one side of the second insulating layer, which is far away from the first metal layer, wherein the first end of the first capacitor is connected to the sixth metal part, and the second end of the first capacitor is connected to the seventh metal part.

In some embodiments, the method further comprises: providing an electronic component on a side of the control chip remote from the substrate structure, the electronic component comprising an inductor, a first end of the inductor being connected to a first electrode of the first transistor and a second electrode of the second transistor, a second end of the inductor being configured to be connected to an output of the converter.

In some embodiments, the electronic component further comprises a second capacitor, a first end of the second capacitor connected to the second end of the inductor, a second end of the second capacitor configured to be grounded.

In the embodiments of the present disclosure, in one aspect, the first transistor and the second transistor are embedded in the first space and the second space defined by the first insulating layer of the substrate structure, respectively, which may prevent the first transistor and the second transistor from being positionally displaced during connection to the first metal layer. This makes it possible to reduce the pitch between the first transistor and the second transistor, thereby increasing the areas of the first transistor and the second transistor, and also makes it possible to reduce the pitch between the electrodes of the first transistor and the second transistor, thereby increasing the areas of the electrodes provided on the surfaces of the first transistor and the second transistor. On the other hand, the first surface of the first insulating layer has one first opening in one-to-one correspondence with each electrode in the first group of electrodes, and the area of the first opening is greater than or equal to 50% of the area of the corresponding electrode. Each of the first group of electrodes is connected to the first metal portion located in a corresponding one of the first openings to be connected to other components through the first metal portion. This can reduce the resistance of the first metal portion and promote heat dissipation of the first transistor and the second transistor. Therefore, under the condition that the area of the converter is constant, the conduction and heat dissipation efficiency of the electrodes of the first transistor and the second transistor can be improved, and the conversion efficiency of the converter can be improved.

Other features, aspects, and advantages of the present disclosure will become apparent from the following detailed description of exemplary embodiments thereof, which is to be read in connection with the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description, serve to explain the principles of the disclosure.

The present disclosure may be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

fig. 1 is a cross-sectional view of a transducer according to some embodiments of the present disclosure;

FIG. 2A is a cross-sectional view of a first metal portion according to some embodiments of the present disclosure;

fig. 2B is a top view of a converter according to some embodiments of the present disclosure;

FIG. 3 is a cross-sectional view of a transducer according to further embodiments of the present disclosure;

FIG. 4 is a cross-sectional view of a converter according to still further embodiments of the present disclosure;

FIG. 5 is a flow diagram of a method of packaging a converter according to some embodiments of the present disclosure;

FIG. 6 is a flow diagram of a method of packaging a converter according to further embodiments of the present disclosure;

FIG. 7 is a schematic flow chart of forming an initial insulating layer according to some embodiments of the present disclosure;

figures 8a to 8i are cross-sectional views of different stages of providing a substrate structure, according to some embodiments of the present disclosure;

fig. 9 is a flow chart schematic of a method of packaging a converter according to still further embodiments of the present disclosure.

It should be understood that the dimensions of the various parts shown in the figures are not necessarily drawn to scale. Further, the same or similar reference numerals denote the same or similar components.

Detailed Description

Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative and is in no way intended to limit the disclosure, its application, or uses. The present disclosure may be embodied in many different forms and is not limited to the embodiments described herein. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. It should be noted that: the relative arrangement of parts and steps, the composition of materials, numerical expressions and numerical values set forth in these embodiments are to be construed as merely illustrative, and not as limitative, unless specifically stated otherwise.

The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element preceding the word comprises the element listed after the word, and does not exclude the possibility that other elements may also be included. "upper", "lower", and the like are used only to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationship may also be changed accordingly.

In the present disclosure, when a specific component is described as being located between a first component and a second component, there may or may not be intervening components between the specific component and the first component or the second component. When it is described that a specific component is connected to other components, the specific component may be directly connected to the other components without having an intervening component, or may be directly connected to the other components without having an intervening component.

All terms (including technical or scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs unless specifically defined otherwise. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

In the related art, the conversion efficiency of the converter is low.

By way of analysis, in the related art, the dies are respectively disposed on both sides of the conductive member to realize the stacking of the dies. The conductive member may be, for example, a metal strip (e.g., a copper strip, also referred to as a copper sheet, i.e., a Cu Clip).

However, the transistor as a die is liable to be displaced in the process of being connected to the conductive member. For example, in order to connect the transistor to the conductive member, the transistor is brought into contact with melted solder; however, before the solder is solidified, the transistor may move arbitrarily due to the flow of the molten solder, and the transistor is likely to be displaced.

On the one hand, this results in a reduction in the area of the transistor. For example, since the transistors may be shifted in position during connection to the conductive members, different transistors are likely to contact each other. To avoid this phenomenon, it is necessary to increase the distance between different transistors, i.e., the area of the transistors is reduced in the case of a constant converter area.

On the other hand, this results in an increase in the spacing between the different electrodes of the transistor (e.g., the pads of the electrodes, i.e., diepads), which in turn results in a decrease in the area of the electrodes. For example, since a transistor may be positionally shifted during connection to a conductive member, if a pitch between a plurality of electrodes provided on the same surface of the transistor is small, the plurality of electrodes are likely to be undesirably connected due to the positional shift, that is, the plurality of electrodes are likely to be short-circuited. In order to avoid this phenomenon, it is necessary to increase the pitch between different electrodes of the transistors, that is, to reduce the area of the electrodes when the area of the transistors is constant.

Due to the above aspects, the conversion efficiency of the converter is low.

In view of this, the embodiments of the present disclosure provide the following solutions, which can improve the conversion efficiency of the converter.

Fig. 1 is a cross-sectional view of a converter according to some embodiments of the present disclosure.

As shown in fig. 1, the converter 100 includes a substrate structure 110. The substrate structure 110 may be, for example, a Printed Circuit Board (PCB).

The substrate structure 110 includes a first insulating layer 1110 defining first and second spaced-apart spaces. In some embodiments, the first insulating layer 1110 includes a plurality of sub-layers, for example, a first insulating sub-layer 1110a and a second insulating sub-layer 1110b on one side of the first insulating sub-layer 1110a. The first insulating sublayer 1110a and the second insulating sublayer 1110b collectively define a first space and a second space.

The substrate structure 110 further includes a first transistor 1120 embedded in the first space and a second transistor 1130 embedded in the second space. The first transistor 1120 and the second transistor 1130 each include a gate G, a first electrode E1, and a second electrode E2. In some embodiments, the gate G and the first electrode E1 of the transistor are spaced apart by a first insulating layer 1110. For example, the gate G of the first transistor 1120 and the first electrode E1 are spaced apart by a first insulating sublayer 1110a.

In some embodiments, at least one of the first Transistor 1120 and the second Transistor 1130 is a Field Effect Transistor (FET), such as a Junction Field Effect Transistor (JFET) or a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Taking a MOSFET as an example, at least one of the first transistor 1120 and the second transistor 1130 may be an N-type MOSFET or a P-type MOSFET.

In some embodiments, the first electrode E1 of the first transistor 1120 is a drain and the second electrode E2 is a source. In other embodiments, the first electrode E1 of the second transistor 1130 is a drain and the second electrode E2 is a source.

In some embodiments, the first electrode E1 of the first transistor 1120 is a source and the second electrode E2 is a drain. In other embodiments, the first electrode E1 of the second transistor 1130 is a source electrode and the second electrode E2 is a drain electrode. For example, since the area of the drain is larger than that of the source, the second electrode E2 as the drain is separately provided on one surface of the first transistor 1120 (the second transistor 1130), and the first electrode E1 as the source is provided on the other surface of the first transistor 1120 (the second transistor 1130) in common with the gate G.

Referring to fig. 1, the substrate structure 110 further includes a first metal layer 1140 positioned at one side of the first insulating layer 1110.

Here, the first metal layer 1140 is connected to the first electrode E1 of the first transistor 1120 and the second electrode E2 of the second transistor 1130. That is, the first electrode E1 of the first transistor 1120 and the second electrode E2 of the second transistor 1130 are connected via the first metal layer 1140.

Since the first transistor 1120 and the second transistor 1130 are embedded in the first space and the second space defined by the first insulating layer 1110, respectively, the first transistor 1120 and the second transistor 1130 are not shifted in position during connection with the first metal layer 1140 as a conductive member. On the one hand, this may reduce the spacing between the first transistor 1120 and the second transistor 1130, which may in turn increase the area of the first transistor 1120 and the second transistor 1130. On the other hand, this can reduce the pitch between the electrodes in the first transistor 1120 and the second transistor 1130 (for example, the pitch between the first electrode E1 and the gate G of the first transistor 1120), which can increase the area of the electrodes of the first transistor 1120 and the second transistor 1130.

For example, since the first transistor 1120 and the second transistor 1130 are not shifted in position during the connection with the first metal layer 1140, the first transistor 1120 and the second transistor 1130 are not in contact with each other even though the distance between the first transistor 1120 and the second transistor 1130 is small, so that the areas of the first transistor 1120 and the second transistor 1130 can be increased in a case where the area of the converter 100 is constant.

For another example, since the first transistor 1120 and the second transistor 1130 are not displaced during the connection with the first metal layer 1140, even if the distance between the first electrode E1 and the gate G provided on the same surface of the first transistor 1120 (the second transistor 1130) is reduced, the first electrode E1 and the gate G of the first transistor 1120 (the second transistor 1130) are less likely to be short-circuited by undesired connection, and thus the area of the electrode provided on the same surface of the first transistor 1120 (the second transistor 1130) can be increased when the area of the first transistor 1120 (the second transistor 1130) is constant.

The first insulating layer 1110 has a first surface S1 distant from the first metal layer 1140 and a second surface S2 close to the first metal layer 1140. Referring to fig. 1, the first surface S1 has one first opening V1 in one-to-one correspondence with each electrode of the first group of electrodes.

Here, the first group of electrodes includes at least one of the second electrode E2 of the first transistor 1120, the first electrode E1 of the second transistor 1130, and the gate G of the second transistor 1130.

For example, the first group of electrodes includes the second electrode E2 of the first transistor 1120, the first electrode E1 of the second transistor 1130, or the gate G of the second transistor 1130. For another example, the first group of electrodes includes any two of the second electrode E2 of the first transistor 1120, the first electrode E1 of the second transistor 1130, and the gate G of the second transistor 1130. For another example, the first group of electrodes includes the second electrode E2 of the first transistor 1120, the first electrode E1 of the second transistor 1130, and the gate G of the second transistor 1130.

Referring to fig. 1, the substrate structure 110 further includes a first metal portion 1161. The first metal part 1161 is located in one first opening V1 corresponding to each electrode in the first group of electrodes, and the first metal part 1161 is connected to the electrode corresponding to the located one first opening V1.

That is, the substrate structure 110 includes one first metal part 1161 in one-to-one correspondence with each electrode in the first group of electrodes.

Taking the first group of electrodes including the second electrode E2 of the first transistor 1120, the first electrode E1 of the second transistor 1130, and the gate G of the second transistor 1130 as an example, the substrate structure 110 includes three first metal portions 1161 corresponding to the three electrodes one by one, respectively, a first metal portion 1161a (located in the first opening V1 a) corresponding to the second electrode E2 of the first transistor 1120, a first metal portion 1161b (located in the first opening V1 b) corresponding to the first electrode E1 of the second transistor 1130, and a first metal portion 1161c (located in the first opening V1 c) corresponding to the gate G of the second transistor 1130. The control chip 120 may be connected with the gate G of the second transistor 1130 via the first metal part 1161c.

As some implementations, the first metal parts 1161a to 1161c may be formed by the same process. That is, in these embodiments, the materials of the first metal parts 1161a to 1161c are the same.

As further implementations, referring to fig. 2A, the first metal portion 1161 includes a first metal sub-layer 11611 and a second metal sub-layer 11612. The first metal sub-layer 11611 is in contact with the electrode corresponding to the first metal portion 1161, and the second metal sub-layer 11612 is located on a side of the first metal sub-layer 11611 away from the electrode corresponding to the first metal portion 1161. That is, the first transistor 1120 or the second transistor 1130 is located on the side of the first metal sublayer 11611 away from the second metal sublayer 11612.

For example, the first metal sub-layer 11611 is formed by sputtering, and the second metal sub-layer 11612 is formed by electroplating. In this way, the second metal sub-layers 11612 are connected to the corresponding electrodes through the uniformly distributed first metal sub-layers 11611, which is beneficial to uniform distribution of current.

In some embodiments, the area of one first opening V1 in one-to-one correspondence with each electrode in the first group of electrodes is greater than or equal to 50% of the area of the corresponding electrode. For example, the area of each first opening V1 is greater than or equal to 60%, 70%, or 80% of the area of the corresponding electrode. Taking an example of a corresponding first opening V1a of the first metal portion 1161a, the area of the first opening V1a is greater than or equal to 50% of the area of the corresponding second electrode E2 of the first transistor 1120.

The area of the orthographic projection of each electrode on a surface of the other insulating layer in the substrate structure 110 can be considered as the area of the electrode. For example, referring to fig. 1, in some embodiments, the substrate structure 110 further includes a second insulating layer 1150 located on a side of the first metal layer 1140 away from the first insulating layer 1110, and the second insulating layer 1150 has a third surface S3 away from the first insulating layer 1110. The area of the orthographic projection of each opening on the third surface S3 can be regarded as the area of the opening. The area of other components may be similar.

As some implementations, the width of each first opening V1 in a cross-sectional view (e.g., fig. 1) is greater than or equal to 50% of the width of the corresponding electrode in the cross-sectional view. For example, the width of the first opening V1a is greater than or equal to 50% of the width of the second electrode E2 of the first transistor 1120.

In some embodiments, the area of each first opening V1 is equal to the area of the corresponding electrode. It should be understood that equality here is an equality within the semiconductor process variation. For example, the orthographic projection of each first opening V1 on the third surface S3 completely overlaps with the orthographic projection of the corresponding electrode on the third surface S3.

It is understood that the larger the area of the first opening V1, the larger the area of the first metal part 1161 in contact with the corresponding electrode. In this case, the smaller the resistance of the first metal part 1161 through which the electrode of the transistor passes current is, and the better the heat dissipation of the first transistor 1120 and the second transistor 1130 through the first metal part 1161 is.

In the above embodiments, in one aspect, the first transistor 1120 and the second transistor 1130 are embedded in the first space and the second space defined by the first insulating layer 1110 of the substrate structure 110, respectively, which can prevent the first transistor 1120 and the second transistor 1130 from being positionally displaced during the connection to the first metal layer 1140. This can reduce the pitch between the first transistor 1120 and the second transistor 1130, thereby increasing the area of the first transistor 1120 and the second transistor 1130, and can reduce the pitch between the electrodes of the first transistor 1120 and the second transistor 1130, thereby increasing the area of the electrodes provided on the surfaces of the first transistor 1120 and the second transistor 1130. On the other hand, the first surface S1 of the first insulating layer 1110 has one first opening V1 in one-to-one correspondence with each electrode in the first group of electrodes, and the area of the first opening V1 is greater than or equal to 50% of the area of the corresponding electrode. Each of the electrodes in the first group of electrodes is connected to the first metal part 1161 located in a corresponding one of the first openings V1 to be connected to other components through the first metal part 1161. This may reduce the resistance of the first metal portion 1161 and facilitate heat dissipation of the first transistor 1120 and the second transistor 1130. Thus, the conduction and heat dissipation efficiency of the electrodes of the first transistor 1120 and the second transistor 1130 can be improved under the condition that the area of the converter 100 is constant, and the conversion efficiency of the converter 100 can be improved.

In addition, by improving the conduction and heat dissipation efficiency of the electrodes of the first transistor 1120 and the second transistor 1130, the possibility of the first transistor 1120 and the second transistor 1130 malfunctioning can be reduced, and the reliability of the converter 100 can be improved.

In some embodiments, the substrate structure 110 further includes a second insulating layer 1150 located on a side of the first metal layer 1140 away from the first insulating layer 1110.

In these embodiments, referring to fig. 1, the converter 100 further includes a control chip 120 located on a side of the second insulating layer 1150 away from the first metal layer 1140. That is, the control chip 120 located outside the substrate structure 110 is stacked on the first transistor 1120 and the second transistor 1130 located inside the substrate structure 110.

The control chip 120 is respectively connected to the gate G of the first transistor 1120 and the gate G of the second transistor 1130.

For example, the control chip 120 may output a Pulse Width Modulation (PWM) signal to adjust a voltage applied to the gate G of the first transistor 1120 and a voltage applied to the gate G of the second transistor 1130. In this manner, the control chip 120 can control the states of the first transistor 1120 and the second transistor 1130. In some embodiments, the control chip 120 may be connected to the gate G of the first transistor 1120 and the gate G of the second transistor 1130 via different wires, respectively.

In the above embodiment, the control chip 120 is stacked on one side of the substrate structure 110 where the first transistor 1120 and the second transistor 1130 are located, which may further increase the area of the first transistor 1120 and the second transistor 1130 without changing the area of the converter 100, compared to when the control chip 120 is also disposed in the substrate structure 110. Thus, the conduction and heat dissipation efficiency of the electrodes of the first transistor 1120 and the second transistor 1130 can be further improved under the condition that the area of the converter 100 is constant, and the conversion efficiency and the reliability of the converter 100 can be further improved.

In addition, the control chip 120 is located on a side of the second insulating layer 1150 away from the first metal layer 1140. In this way, the control chip 120 may be insulated from the first metal layer 1140 by the second insulating layer 1150 contained in the substrate structure 110 itself, so as to prevent the control chip 120 from being electrically connected to the first electrode E1 of the first transistor 1120 or the second electrode E2 of the second transistor 1130 without an additional insulating process. In this manner, the process flow for manufacturing the transducer 100 may be simplified.

In some embodiments, an orthographic projection of the control chip 120 on the third surface S3 of the second insulating layer 1150 at least partially overlaps an orthographic projection of at least one of the first transistor 1120 and the second transistor 1130 on the third surface S3. In this manner, the area of the converter 100 can be further reduced.

For example, an orthographic projection of the control chip 120 on the third surface S3 at least partially overlaps with an orthographic projection 1120' of the first transistor 1120 on the third surface S3. For another example, an orthogonal projection of the control chip 120 on the third surface S3 at least partially overlaps an orthogonal projection 1130' of the second transistor 1130 on the third surface S3. For another example, an orthographic projection of the control chip 120 on the third surface S3 at least partially overlaps with the orthographic projection 1120 'of the first transistor 1120 on the third surface S3, and at least partially overlaps with the orthographic projection 1130' of the second transistor 1130 on the third surface S3.

This is explained below with reference to fig. 2B. Fig. 2B is a top view of a converter according to some embodiments of the present disclosure.

Referring to fig. 2B, an orthogonal projection of the control chip 120 on the third surface S3 partially overlaps with the orthogonal projection 1120 'of the first transistor 1120 on the third surface S3, and partially overlaps with the orthogonal projection 1130' of the second transistor 1130 on the third surface S3. Fig. 1 may be a sectional view taken along a section line in fig. 2B.

Other components of the converter 100 (e.g., the first capacitor 130), and orthographic projections of other metal portions in the substrate structure 110 on the third surface (e.g., the orthographic projection 1163' of the metal portion 1163, the orthographic projection 1181' of the sixth metal portion 1181, and the orthographic projection 1182' of the seventh metal portion 1182) are also schematically illustrated in fig. 2B, which will be described later.

Further, a relatively thick straight line between two components in fig. 2B indicates a lead line connecting the two components. For example, a pad (pad) on the surface of the control chip 120 is electrically connected to the conductive structure 1120G in the substrate structure 110 through a wire, so as to transmit an electrical signal to control the gate G of the first transistor 1120; for another example, another pad on the surface of the control chip 120 is electrically connected to the conductive member 1130G in the substrate structure 110 through a wire, so as to transmit an electrical signal to control the gate G of the second transistor 1130.

The converter 100 is further described below in connection with some embodiments.

In some embodiments, the area of each first opening V1 is greater than or equal to 90% of the area of the corresponding electrode. Thus, the conversion efficiency of the converter 100 can be further improved, and the reliability of the converter 100 can be further improved.

As some implementations, a connection line between a center point of one first opening V1 corresponding to each electrode in the first group of electrodes and a center point of the corresponding electrode is a first line, and the first line is perpendicular to a surface of the electrode corresponding to the one first opening V1, which is close to the one first opening V1. That is, the central point of the orthographic projection of each first opening V1 on the third surface S3 overlaps the central point of the orthographic projection of the corresponding electrode on the third surface S3. For example, a central point of the second electrode E2 of the first transistor 1120 overlaps with an orthographic projection of a central point of one first opening V1a on the third surface S3 where the first metal portion 1161a is located.

In other words, in these embodiments, each of the first openings V1 is disposed substantially symmetrically on both sides of the center point of the corresponding electrode in a direction parallel to the third surface S3. As such, the connection between the first metal portion 1161 and the corresponding electrode is more reliable.

In some embodiments, referring to fig. 1, the second surface S2 of the first insulating layer 1110 has at least one second opening V2 in one-to-one correspondence with each electrode of the second set of electrodes. The second group of electrodes includes at least one of the first electrode E1 of the first transistor 1120, the gate G of the first transistor 1120, and the second electrode E2 of the second transistor 1130.

For example, the second group of electrodes includes the first electrode E1 of the first transistor 1120, the second electrode E2 of the second transistor 1130, or the gate G of the first transistor 1120. For another example, the second group of electrodes includes any two of the first electrode E1 of the first transistor 1120, the second electrode E2 of the second transistor 1130, and the gate G of the first transistor 1120. For another example, the second group of electrodes includes the first electrode E1 of the first transistor 1120, the second electrode E2 of the second transistor 1130, and the gate G of the first transistor 1120.

In these embodiments, the first metal layer 1140 includes a second metal portion 1141. The second metal portion 1141 is located in at least one second opening V2 corresponding to each electrode in the second group of electrodes, and the second metal portion 1141 is connected to the electrode corresponding to the located at least one second opening V2.

That is, the first metal layer 1140 includes one or more second metal portions 1141 in one-to-one correspondence with each electrode of the second group of electrodes.

In some embodiments, similar to the first metal portion 1161, the second metal portion 1141 includes a third metal sub-layer and a fourth metal sub-layer. The third metal sub-layer is in contact with the electrode corresponding to the second metal portion 1141, and the fourth metal sub-layer is located on a side of the third metal sub-layer away from the electrode corresponding to the second metal portion 1141. For example, the third metal sub-layer is formed by sputtering, and the fourth metal sub-layer is formed by electroplating. Therefore, the fourth metal sub-layer is connected with the corresponding electrode through the uniformly distributed third metal sub-layer, and the uniform distribution of current is facilitated.

As some implementations, the second surface S2 has a plurality of second openings V2 in one-to-one correspondence with each electrode in the second set of electrodes. That is, the first metal layer 1140 includes a plurality of second metal portions 1141 corresponding to each electrode of the second group of electrodes one to one.

Referring to fig. 3, the second group of electrodes includes the first electrode E1 of the first transistor 1120, the second electrode E2 of the second transistor 1130, and the gate G of the first transistor 1120 as an example. In these implementations, the second surface S2 has a plurality of second openings V2a corresponding to the first electrode E1 of the first transistor 1120, a plurality of second openings V2b corresponding to the second electrode E2 of the second transistor 1130, and at least one second opening V2c corresponding to the gate G of the first transistor 1120.

In this case, referring to fig. 3, the second metal part 1141 includes a plurality of second metal parts 1141a, a plurality of second metal parts 1141b, and at least one second metal part 1141c. The plurality of second metal portions 1141a are positioned in the plurality of second openings V2a corresponding to the first electrode E1 of the first transistor 1120, the plurality of second metal portions 1141b are positioned in the plurality of second openings V2b corresponding to the second electrode E2 of the second transistor 1130, and the at least one second metal portion 1141c is positioned in the at least one second opening V2c corresponding to the gate G of the first transistor 1120.

In these cases, for example, the second metal portion 1141 is a via (via) connected to the second group of electrodes.

As other implementations, referring to fig. 1, the second surface S2 has one second opening V2 (e.g., one second opening V2a, one second opening V2b, and one second opening V2 c) in one-to-one correspondence with each electrode in the second group of electrodes, instead of a plurality of second openings V2. That is, the first metal layer 1140 includes one second metal part 1141 in one-to-one correspondence with each electrode of the second group of electrodes, instead of the plurality of second metal parts 1141.

In some embodiments, the area of one second opening V2 in one-to-one correspondence with each electrode in the second group of electrodes is greater than or equal to 50% of the area of the corresponding electrode. For example, the area of each second opening V2 is greater than or equal to 60%, 70%, or 80% of the area of the corresponding electrode. For example, the area of one second opening V2a corresponding to the second metal portion 1141a is greater than or equal to 50% of the area of the first electrode E1 of the corresponding first transistor 1120.

As some implementations, the width of each second opening V2 in a cross-sectional view (e.g., fig. 1) is greater than or equal to 50% of the width of the corresponding electrode in the cross-sectional view. For example, the width of the corresponding one of the second openings V2a of the second metal portion 1141a is greater than or equal to 50% of the width of the corresponding first electrode E1 of the first transistor 1120.

In this manner, the resistance of the second metal portion 1141 can be reduced, and heat dissipation of the first transistor 1120 and the second transistor 1130 can be further promoted. In this way, the conversion efficiency of the converter 100 can be further improved, and the possibility of failure of the first transistor 1120 and the second transistor 1130 can be further reduced, thereby further improving the reliability of the converter 100.

In some embodiments, the area of each second opening V2 is greater than or equal to 90% of the area of the corresponding electrode. Thus, the conversion efficiency of the converter 100 can be further improved, and the reliability of the converter 100 can be further improved.

As some implementations, a connecting line between a center point of one second opening V2 corresponding to each electrode in the second group of electrodes and a center point of the corresponding electrode is a second line, and the second line is perpendicular to a surface of the electrode corresponding to the one second opening V2 near the one second opening V2. That is, the central point of the orthographic projection of each second opening V2 on the third surface S3 overlaps the central point of the orthographic projection of the corresponding electrode on the third surface S3.

For example, a central point of the second electrode E2 of the second transistor 1130 overlaps an orthographic projection of a central point of one second opening V2b, where the second metal portion 1141b is located, on the third surface S3.

In other words, in these embodiments, each of the second openings V2 is substantially symmetrically disposed on both sides of the center point of the corresponding electrode in a direction parallel to the third surface S3. Thus, the connection between the second metal portion 1141 and the corresponding electrode is more reliable.

In some embodiments, the first surface S1 of the first insulating layer 1110 further has at least one third opening V3.

In these embodiments, referring to fig. 1, the substrate structure 110 further includes a third metal portion 1162 located in the at least one third opening V3. The third metal portion 1162 is connected to the first electrode E1 of the first transistor 1120 and the second electrode E2 of the second transistor 1130 via the first metal layer 1140.

As some implementations, referring to fig. 1, the second surface S2 of the first insulating layer 1110 further has at least one fourth opening V4. The first metal layer 1140 further includes a fourth metal portion 1142 located in the at least one fourth opening V4, and the substrate structure 110 further includes a fifth metal portion 1170 extending in the first insulating layer 1110.

In these implementations, the third metal portion 1162 is connected to the first metal layer 1140 via the fifth metal portion 1170 and the fourth metal portion 1142 in sequence. The fifth metal portion 1170 is, for example, a metal pillar (e.g., a copper pillar) extending in the first insulating layer 1110. In this way, a reliable connection between the third metal portion 1162 and the first metal layer 1140 on two sides of the first insulating layer 1110 can be achieved through the fifth metal portion 1170 extending in the substrate structure 110.

In these embodiments, the third metal portion 1162 is configured to connect to the output of the converter 100. The first metal portion 1161a corresponding to the second electrode E2 of the first transistor 1120 is configured to be connected to the input terminal of the converter 100, and the first metal portion 1161b corresponding to the first electrode E1 of the second transistor 1130 is configured to be grounded. In this way, the converter 100 can be connected to an external circuit through the first metal parts 1161a to 1161b and the third metal part 1162 to form a complete conversion circuit. The converter 100 may be, for example, a buck converter.

For example, the substrate structure 110 further includes a metal portion 1163 on a side of the first metal portion 1161a away from the first transistor 1120. The metal part 1163 contacts the first metal part 1161a and is configured to be connected to an input terminal of the converter 100. That is, the first metal part 1161a is configured to be connected to the input terminal of the converter 100 via the metal part 1163.

For another example, the substrate structure 110 further includes a metal portion 1164 on a side of the first metal portion 1161b away from the second transistor 1130. The metal part 1164 is in contact with the first metal part 1161b and is configured to be grounded. That is, the first metal part 1161b is configured to be grounded via the metal part 1164.

For another example, the substrate structure 110 further includes a metal portion 1165 located on a side of the third metal portion 1162 away from the fifth metal portion 1170. The metal part 1165 is in contact with the third metal part 1162 and is configured to be connected to an output terminal of the converter 100. That is, the third metal part 1162 is configured to be connected to the output terminal of the converter 100 via the metal part 1165.

In some embodiments, the area of metal portion 1163 is greater than the area of first metal portion 1161 a. In other embodiments, the area of metal portion 1164 is greater than the area of first metal portion 1161 b. In this way, the converter 100 can be more reliably connected to an external circuit.

Fig. 4 is a cross-sectional view of a transducer according to still further embodiments of the present disclosure.

As shown in fig. 4, the substrate structure 110 further includes a sixth metal portion 1181 located on a side of the second insulating layer 1150 far from the first metal layer 1140. The sixth metal part 1181 is in contact with the control chip 120 and configured to be grounded.

In this way, when the first transistor 1120 and the second transistor 1130 perform the on and off operations to generate the electromagnetic interference noise, the grounded sixth metal portion 1181 may shield the electromagnetic interference of the first transistor 1120 and the second transistor 1130 on the control chip 120, so that the reliability of the operation of the control chip 120 may be improved.

In some embodiments, the substrate structure 110 further includes a seventh metal portion 1182 located on a side of the second insulating layer 1150 away from the first metal layer 1140. The seventh metal part 1182 is configured to be connected to the input terminal of the converter 100.

In these embodiments, referring to fig. 4, the converter 100 further includes a first capacitor 130 located on a side of the second insulating layer 1150 that is distal from the first metal layer 1140. A first end of the first capacitor 130 is connected to the sixth metal part 1181, and a second end of the first capacitor 130 is connected to the seventh metal part 1182. In this way, the switching losses of the converter 100 can be reduced.

In some embodiments, the substrate structure 110 further includes an eighth metal part 1183, and the eighth metal part 1183 includes a first portion 1183a and a second portion 1183b. Referring to fig. 4, the first portion 1183a is located on a side of the second insulating layer 1150 away from the first metal layer 1140, and the second portion 1183b extends in the second insulating layer 1150.

In these embodiments, the first portion 1183a is connected to the gate G of the first transistor 1120 via the second portion 1183b.

For example, referring to fig. 4, the converter 100 further includes a metal portion 1143 located on a side of the second metal portion 1141c away from the first transistor 1120, and the metal portion 1143 is in contact with the second metal portion 1141c and is spaced apart, i.e., insulated, from the

second metal portions

1141a and 1141 b.

In these embodiments, the control chip 120 is connected to the gate G of the first transistor 1120 via the eighth metal portion 1183. For example, referring to fig. 4, the control chip 120 is connected to the gate G of the first transistor 1120 via a wire, the first portion 1183a, the second portion 1183b, the metal portion 1143, and the second metal portion 1141c in sequence. As such, the control chip 120 may be connected to the gate G of the first transistor 1120.

As some implementations, the sixth metal part 1181, the seventh metal part 1182, and the eighth metal part 1183 may be formed through the same process. That is, in these embodiments, the materials of sixth metal portion 1181, seventh metal portion 1182, and eighth metal portion 1183 are the same.

In some embodiments, referring to fig. 4, the converter 100 further includes an electronic component 140 located on a side of the control chip 120 away from the substrate structure 110, that is, the electronic component 140, the control chip 120 and the substrate structure 110 are stacked in sequence.

The electronic component 140 includes an inductor 1410. A first terminal of the inductor 1410 is connected to the first electrode E1 of the first transistor 1120 and the second electrode E2 of the second transistor 1130, and a second terminal of the inductor 1410 is configured to be connected to the output terminal of the converter 100.

Therefore, the converter 100 can include more elements without increasing the area of the converter 100, thereby increasing the integration level of the converter 100.

In some embodiments, the electronic assembly 140 further includes a second capacitor 1420. A first end of the second capacitor 1420 is connected to a second end of the inductor 1410 configured to be connected to an output of the converter 100, and a second end of the second capacitor 1420 is configured to be connected to ground. Thus, the integration level of the converter 100 can be further improved without increasing the area of the converter 100.

In some embodiments, referring to fig. 4, the converter 100 is encapsulated by a mold compound 150. The molding compound 150 may be, for example, an Epoxy Molding Compound (EMC).

The following describes a method for packaging the converter 100 according to various embodiments of the present disclosure. Fig. 5 is a flow diagram of a method of packaging a converter according to some embodiments of the present disclosure.

As shown in fig. 5, the packaging method of the converter 100 includes step 502.

At step 502, a substrate structure 110 is provided.

The substrate structure 110 includes a first insulating layer 1110, a first metal layer 1140, a first transistor 1120, and a second transistor 1130. The first transistor 1120 and the second transistor 1130 each include a gate G, a first electrode E1, and a second electrode E2.

Here, the first insulating layer 1110 defines first and second spaces spaced apart. The first transistor 1120 is embedded in the first space, and the second transistor 1130 is embedded in the second space.

The first metal layer 1140 is positioned at one side of the first insulating layer 1110 and is connected to the first electrode E1 of the first transistor 1120 and the second electrode E2 of the second transistor 1130.

The first insulating layer 1110 has a first surface S1 distant from the first metal layer 1140 and a second surface S2 close to the first metal layer 1140.

The first surface S1 has one first opening V1 in one-to-one correspondence with each electrode in the first group of electrodes. Here, the first group of electrodes includes at least one of the second electrode E2 of the first transistor 1120, the first electrode E1 of the second transistor 1130, and the gate G of the second transistor 1130.

The substrate structure 110 further includes a first metal portion 1161. The first metal part 1161 is located in one of the first openings V1 corresponding to the electrodes and is connected to the electrode corresponding to the one of the first openings V1. Here, the area of each first opening V1 is greater than or equal to 50% of the area of the corresponding electrode.

Thus, the converter 100 having a small area, high conversion efficiency, and high reliability can be packaged.

In some embodiments, the substrate structure 110 further includes a second insulating layer 1150 located on a side of the first metal layer 1140 remote from the first insulating layer 1110.

In these embodiments, referring to fig. 5, the packaging method of the converter 100 further includes step 504. In step 504, the control chip 120 is disposed on a side of the second insulating layer 1150 away from the first metal layer 1140.

Here, the control chip 120 is connected to the gate G of the first transistor 1120 and the gate G of the second transistor 1130, respectively.

As such, the area of the converter 100 is further reduced and the conversion efficiency is further improved.

In some embodiments, the second surface S2 of the first insulating layer 1110 has at least one second opening V2, e.g., one second opening V2, in one-to-one correspondence with each electrode of the second set of electrodes. The second group of electrodes includes at least one of the first electrode E1 of the first transistor 1120, the second electrode E2 of the second transistor 1130, and the gate G of the first transistor 1120.

In these embodiments, the first metal layer 1140 includes a second metal portion 1141. The second metal portion 1141 is located in the at least one second opening V2 corresponding to the electrode, and is connected to the electrode corresponding to the at least one second opening V2.

In these embodiments, as shown in FIG. 6, step 502 includes steps 5022-5028.

At step 5022, an initial insulating layer 1110' is formed that encapsulates the first transistor 1120 and the second transistor 1130.

Here, the preliminary insulating layer 1110' has a first preliminary surface S1' and a second preliminary surface S2'. In particular, the first initial surface S1 'is close to the first set of electrodes and the second initial surface S2' is close to the second set of electrodes.

In step 5024, one first opening V1 corresponding to each electrode in the first group of electrodes one by one is formed on the first initial surface S1' to obtain a first surface S1, and the first metal part 1161 filling the one first opening V1 is formed.

As some implementations, a patterned photoresist is formed on the first preliminary surface S1', and the first preliminary surface S1' is etched using the patterned photoresist as a mask to form the first opening V1.

As some implementations, after forming the first opening V1, the first metal sub-layer 11611 in the first metal part 1161 may be first sputter formed and then the second metal sub-layer 11612 in the first metal part 1161 may be electroplated.

At step 5026, at least one second opening V2 corresponding to each electrode in the second group of electrodes one to one is formed on the second initial surface S2' to obtain a second surface S2, and a first metal layer 1140 filling the at least one second opening V2 is formed.

As some implementations, a patterned photoresist is formed on the second initial surface S2', and the second initial surface S2' is etched using the patterned photoresist as a mask to form one second opening V2 corresponding to each electrode. As other implementations, the plurality of second openings V2 corresponding to each electrode are formed by using a laser method.

As some implementations, after forming the second opening V2, the third metal sub-layer in the second metal portion 1141 of the first metal layer 1140 may be first sputtered and then electroplated to form the fourth metal sub-layer in the second metal portion 1141.

Step 5026 may be performed before step 5024, or after step 5024.

At step 5028, a second insulating layer 1150 is formed over the first metal layer 1140 on a side away from the first insulating layer 1110.

In this manner, the substrate structure 110 in which the first transistor 1120 and the second transistor 1130 are embedded in the first insulating layer 1110 may be formed.

It should be understood that step 502 may include only one or more of steps 5022-5028. For example, step 502 may include only step 5022, step 5026 and step 5028.

In some embodiments, as shown in FIG. 7, step 5022 comprises steps 5022 a-5022 d.

In step 5022a, the first transistor 1120 and the second transistor 1130 are fixed to one side of the support 160 with a space therebetween. In some embodiments, the support 160 is an adhesive tape, for example, a Polyimide (PI) adhesive tape.

At step 5022b, a first initial insulating sub-layer 1110a' is formed on one side of the support 160. The first preliminary insulating sublayer 1110a ' has one of a first preliminary surface S1' and a second preliminary surface S2'.

At step 5022c, the support 160 is removed.

At step 5022d, after the supports 160 are removed, a second preliminary insulating sub-layer 1110b 'is formed on the side of the first preliminary insulating sub-layer 1110a' that was on before the supports 160 were removed. The second preliminary insulating sub-layer 1110b ' has the other of the first preliminary surface S1' and the second preliminary surface S2'.

That is, the first and second preliminary insulating sub-layers 1110a ' and 1110b ' constitute a preliminary insulating layer 1110' covering the first and

second transistors

1120 and 1130.

For example, the first preliminary insulating sub-layer 1110a 'has a first preliminary surface S1', and the second preliminary insulating sub-layer 1110b 'has a second preliminary surface S2'. As another example, the first preliminary insulating sub-layer 1110a 'has a second preliminary surface S2', and the second preliminary insulating sub-layer 1110b 'has a first preliminary surface S1'.

It is understood that step 5024 may be performed after the formation of the initial insulating sub-layer having the first initial surface S1', and that step 5026 may be performed after the formation of the initial insulating sub-layer having the second initial surface S2'.

Thus, the initial insulating layer 1110' covering the first transistor 1120 and the second transistor 1130 can be formed by a simple process.

In some embodiments, the first initial insulating sub-layer 1110a 'has a second initial surface S2'.

In these embodiments, after the first metal layer 1140 is formed, the supporters 160 are removed. That is, after step 5024, steps 5022c and 5022d are performed, and after step 5022d, step 5026 is performed.

The following describes a process of providing the substrate structure 110 according to the above-described embodiment with reference to cross-sectional views shown in fig. 8a to 8i.

First, as shown in fig. 8A, a first transistor 1120 and a second transistor 1130 are fixed to one side of the support 160 with a space therebetween.

Then, as shown in fig. 8B, a first preliminary insulating sub-layer 1110a' is formed at one side of the supporter 160. The first preliminary insulating sublayer 1110a 'has a second preliminary surface S2'.

Thereafter, as shown in fig. 8C, at least one second opening V2 corresponding to each electrode of the second group of electrodes in a one-to-one manner is formed at the second initial surface S2' to obtain a second surface S2. After forming the second opening V2, the first initial insulating sublayer 1110a' is the first insulating sublayer 1110a.

Thereafter, as shown in fig. 8D, a first metal layer 1140 filling the at least one second opening V2 is formed. In some embodiments, the second metal portion 1141c located in one of the second openings V2 corresponding to the gate G of the first transistor 1120 and the metal portion 1143 located on a side of the second metal portion 1141c away from the first transistor 1120 may be simultaneously formed in the process of forming the first metal layer 1140.

As some implementation manners, the first metal sub-layer 11611 covering the second surface S2 is formed by sputtering, and then the second metal sub-layer 11612 covering the first metal sub-layer 11611 is formed by electroplating, so as to obtain a first initial metal layer including the first metal sub-layer 11611 and the second metal sub-layer 11612. Then, the first initial metal layer is etched, and the remaining portions of the first initial metal layer are etched to be the first metal layer 1140, the second metal portion 1141c, and the metal portion 1143.

Thereafter, as shown in fig. 8E, a second insulating layer 1150 is formed on a side of the first metal layer 1140 away from the first insulating layer 1110. In some embodiments, the second insulating layer 1150 is a gap between the first metal layer 1140 and the metal portion 1143.

Thereafter, as shown in fig. 8F, the support 160 is removed.

In some embodiments, after forming the second insulating layer 1150, a sixth metal part 1181, a seventh metal part 1182, and an eighth metal part 1183 may be further formed on a side of the second insulating layer 1150 away from the first metal layer 1140. After the sixth metal part 1181, the seventh metal part 1182 and the eighth metal part 1183 are formed, the support is removed.

Thereafter, as shown in fig. 8G, a second preliminary insulating sub-layer 1110b 'is formed at a side of the first preliminary insulating sub-layer 1110a' (i.e., the first insulating sub-layer 1110 a) where the supporter 160 was removed. The second initial insulating sub-layer 1110b 'has a first initial surface S1'.

Thereafter, as shown in fig. 8H, one first opening V1 corresponding one-to-one to each electrode of the first group of electrodes is formed at the first initial surface S1' to obtain the first surface S1. After the first opening V1 is formed, the second initial insulating sub-layer 1110b' is the second insulating sub-layer 1110b.

Thereafter, as shown in fig. 8I, a first metal portion 1161 filling the first opening V1 is formed.

As some implementation manners, a third metal sub-layer covering the first surface S1 is formed by sputtering, and then a fourth metal sub-layer covering the third metal sub-layer is formed by electroplating, so as to obtain a second initial metal layer including the third metal sub-layer and the fourth metal sub-layer. The second initial metal layer is then etched, with the remaining portion of the second initial metal layer etched as metal layer 1160. The metal layer 1160 includes a first metal portion 1161 in the first opening V1.

According to the flow shown in fig. 8a to 8i, after the first insulating sublayer 1110a is formed, a first metal layer 1140 and a second insulating layer 1150 which are located on one side of the first insulating sublayer 1110a are formed. Then, the second insulating sub-layer 1110b and the first metal portion 1161 on the other side of the first insulating sub-layer 1110a are formed. Thus, the process flow can be simplified, and the manufacturing efficiency of the substrate structure 110 can be improved.

The packaging method of the converter 100 according to the embodiments of the present disclosure is further described below with reference to some embodiments.

In some embodiments, the first surface S1 of the first insulating layer 1110 further has at least one third opening V3, and the second surface S2 of the first insulating layer 1110 further has at least one fourth opening V4.

In these embodiments, the substrate structure 110 further includes a third metal portion 1162 located in the at least one third opening V3, and the first metal layer 1140 further includes a fourth metal portion 1142 located in the at least one fourth opening V4. The third metal portion 1162 is connected to the first metal layer 1140 through the fifth metal portion 1170 and the fourth metal portion 1142 extending in the first insulating layer 1110 in sequence.

In these embodiments, the initial insulating layer 1110' formed in step 5022 also coats the fifth metal 1170.

For example, in step 5022a, the fifth metal 1170 is also fixed on the same side of the support 160 as the first transistor 1120 and the second transistor 1130. Here, the fifth metal portion 1170 is spaced apart from the first transistor 1120 and the second transistor 1130, respectively. Thereafter, a first preliminary insulating sub-layer 1110a' is formed.

For example, at step 5024, at least one third opening V3 is also formed in the first initial surface S1'. For another example, at step 5026, at least one fourth opening V4 is also formed on the second initial surface S2'.

Thus, the first metal layer 1140 and the third metal portion 1162 on both sides of the first insulating layer 1110 can be connected by a simple process.

In some embodiments, the substrate structure 110 further includes a sixth metal portion 1181 and a seventh metal portion 1182 on a side of the second insulating layer 1150 away from the first metal layer 1140. The sixth metal part 1181 is in contact with the control chip 120 and configured to be grounded, and the seventh metal part 1182 is configured to be connected to the input terminal of the converter 100.

In these embodiments, referring to fig. 9, the packaging method of the converter 100 further includes step 506. In step 506, a first capacitor 130 is disposed on a side of the second insulating layer 1150 away from the first metal layer 1140.

Here, the first end of the first capacitor 130 is connected to the sixth metal part 1181, and the second end of the first capacitor 130 is connected to the seventh metal part 1182. In this way, the switching losses of the converter 100 can be reduced.

In some embodiments, referring to fig. 9, the packaging method of the converter 100 further includes step 508. At step 508, the electronic component 140 is disposed on a side of the control chip 120 away from the substrate structure 110, the electronic component 140 including the inductor 1410.

A first end of the inductor 1410 is connected to a first electrode E1 of the first transistor 1120 and a second electrode E2 of the second transistor 1130, and a second end of the inductor 1410 is configured to be connected to an output of the converter 100.

In some embodiments, the electronic assembly 140 further includes a second capacitor 1420. A first end of the second capacitor 1420 is connected to a second end of the inductor 1410, and a second end of the second capacitor 1420 is configured to be grounded.

Thus, the integration level of the converter 100 can be improved without increasing the area of the converter 100.

In some embodiments, the packaging method further comprises packaging with the mold compound 150. The molding compound 150 may be, for example, EMC.

The embodiment of the present disclosure further provides an electronic device including the converter 100 of any one of the above embodiments. The electronic device is, for example, a mobile phone, a computer, a charger, or the like.

Thus, various embodiments of the present disclosure have been described in detail. Some details well known in the art have not been described in order to avoid obscuring the concepts of the present disclosure. It will be fully apparent to those skilled in the art from the foregoing description how to practice the presently disclosed embodiments.

Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. It will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A converter, comprising:

a substrate structure (110) comprising:

a first insulating layer (1110) defining first and second spaced apart spaces,

a first transistor (1120) embedded in the first space, including a gate electrode (G), a first electrode (E1), and a second electrode (E2),

a second transistor (1130) embedded in the second space, including a gate electrode (G), a first electrode (E1) and a second electrode (E2), and

a first metal layer (1140) on one side of the first insulating layer (1110) and connected to a first electrode (E1) of the first transistor (1120) and a second electrode (E2) of the second transistor (1130),

wherein the first insulating layer (1110) has a first surface (S1) remote from the first metal layer (1140) and a second surface (S2) close to the first metal layer (1140), the first surface (S1) having one first opening in one-to-one correspondence with each electrode of a first set of electrodes, the first set of electrodes comprising at least one of the second electrode (E2) of the first transistor (1120), the first electrode (E1) of the second transistor (1130), and the gate (G) of the second transistor (1130);

the substrate structure (110) further comprises:

and a first metal part (1161) positioned in the one first opening and connected to the electrode corresponding to the one first opening, wherein an area of the one first opening is greater than or equal to 50% of an area of the corresponding electrode.

2. The converter of claim 1, wherein:

the substrate structure (110) further comprises a second insulating layer (1150) located on a side of the first metal layer (1140) away from the first insulating layer (1110); and

the converter further comprises a control chip (120) which is located on one side of the second insulating layer (1150) far away from the first metal layer (1140) and is respectively connected to the gate (G) of the first transistor (1120) and the gate (G) of the second transistor (1130).

3. The converter of claim 1, wherein the area of the one first opening is greater than or equal to 90% of the area of the corresponding electrode.

4. The transducer of claim 1, wherein a line connecting the center point of the one first opening and the center point of the corresponding electrode is a first line perpendicular to a surface of the one first opening where the corresponding electrode is close to the one first opening.

5. The converter of claim 1, wherein the first metal portion (1161) comprises:

a first metal sublayer (11611) in contact with the electrode corresponding to the one first opening; and

a second metal sub-layer (11612) on a side of the first metal sub-layer away from the electrode corresponding to the first opening.

6. The converter of claim 1, wherein the second surface (S2) has at least one second opening in one-to-one correspondence with each electrode of a second set of electrodes comprising at least one of the first electrode (E1) of the first transistor (1120), the gate (G) of the first transistor (1120), and the second electrode (E2) of the second transistor (1130);

wherein the first metal layer (1140) comprises:

and a second metal part (1141) located in the at least one second opening and connected to an electrode corresponding to the at least one second opening.

7. The converter of claim 6, wherein the at least one second opening is one second opening having an area greater than or equal to 50% of an area of the corresponding electrode.

8. The converter of claim 7, wherein the area of the one second opening is greater than or equal to 90% of the area of the corresponding electrode.

9. The transducer of claim 7, wherein a line connecting the center point of the one second opening and the center point of the corresponding electrode is a second line perpendicular to a surface of the one second opening where the corresponding electrode is close to the one second opening.

10. The converter of claim 1, wherein the first surface (S1) further has at least one third opening;

the substrate structure (110) further comprises:

a third metal portion (1162) in the at least one third opening, connected to the first electrode (E1) of the first transistor (1120) and the second electrode (E2) of the second transistor (1130) via the first metal layer (1140), the third metal portion (1162) configured to be connected to an output terminal of the converter (100);

wherein a first metal portion (1161 a) corresponding to the second electrode (E2) of the first transistor (1120) is configured to be connected to an input terminal of the converter (100), and a first metal portion (1161 b) corresponding to the first electrode (E1) of the second transistor (1130) is configured to be grounded.

11. The converter of claim 10, wherein the second surface (S2) further has at least one fourth opening, the first metal layer (1140) further comprises a fourth metal portion (1142) in the at least one fourth opening, the substrate structure (110) further comprises a fifth metal portion (1170) extending in the first insulating layer (1110), the third metal portion (1162) being connected with the first metal layer (1140) via the fifth metal portion (1170) and the fourth metal portion (1142) in sequence.

12. The converter according to any of claims 1-11, wherein the first insulating layer (1110) comprises a first insulating sub-layer (1110 a) and a second insulating sub-layer (1110 b) on one side of the first insulating sub-layer (1110 a), the first and second insulating sub-layers (1110 a, 1110 b) defining the first and second spaces.

13. The converter of claim 2, wherein the second insulating layer (1150) has a third surface (S3) remote from the first metal layer (1140), an orthographic projection of the control chip (120) on the third surface (S3) at least partially overlapping an orthographic projection of at least one of the first transistor (1120) and the second transistor (1130) on the third surface (S3).

14. The converter of claim 2, wherein the substrate structure (110) further comprises:

a sixth metal portion (1181) located on a side of the second insulating layer (1150) far away from the first metal layer (1140), wherein the sixth metal portion (1181) is in contact with the control chip (120) and configured to be grounded.

15. The converter of claim 14, wherein the substrate structure (110) further comprises:

a seventh metal portion (1182) on a side of the second insulating layer (1150) away from the first metal layer (1140), the seventh metal portion (1182) configured to be connected to an input of the converter (100);

the converter (100) further comprises:

a first capacitor (130) located on a side of the second insulating layer (1150) away from the first metal layer (1140), a first end of the first capacitor (130) being connected to the sixth metal portion (1181), and a second end of the first capacitor (130) being connected to the seventh metal portion (1182).

16. The converter of claim 2, wherein the substrate structure (110) further comprises:

an eighth metal portion (1183) comprising a first portion (1183 a) and a second portion (1183 b), the first portion (1183 a) being located on a side of the second insulating layer (1150) remote from the first metal layer (1140), the second portion (1183 b) extending in the second insulating layer (1150), the first portion (1183 a) being connected to the gate (G) of the first transistor (1120) via the second portion (1183 b);

wherein the control chip (120) is connected to the gate (G) of the first transistor (1120) via the eighth metal part (1183).

17. The converter of claim 2, further comprising:

an electronic component (140) located on a side of the control chip (120) remote from the substrate structure (110), comprising an inductor (1410), a first end of the inductor (1410) being connected to a first electrode (E1) of the first transistor (1120) and a second electrode (E2) of the second transistor (1130), a second end of the inductor (1410) being configured to be connected to an output of the converter (100).

18. The converter of claim 17, wherein the electronic assembly (140) further comprises:

a second capacitor (1420), a first end of the second capacitor (1420) connected to the second end of the inductor (1410), a second end of the second capacitor (1420) configured to be ground.

19. An electronic device, comprising:

the converter of any one of claims 1-18.

20. A method of packaging a converter, comprising:

providing a substrate structure (110), the substrate structure (110) comprising a first insulating layer (1110), a first metal layer (1140), a first transistor (1120) and a second transistor (1130), the first transistor (1120) and the second transistor (1130) each comprising a gate (G), a first electrode (E1) and a second electrode (E2), wherein the first insulating layer (1110) defines a first space and a second space which are spaced apart, the first transistor (1120) is embedded in the first space, the second transistor (1130) is embedded in the second space, the first metal layer (1140) is located on one side of the first insulating layer (1110) and is connected to the first electrode (E1) of the first transistor (1120) and the second electrode (E2) of the second transistor (1130);

wherein the first insulating layer (1110) has a first surface (S1) remote from the first metal layer (1140) and a second surface (S2) close to the first metal layer (1140), the first surface (S1) having one first opening in one-to-one correspondence with each electrode of a first group of electrodes, the first group of electrodes comprising at least one of the second electrode (E2) of the first transistor (1120), the first electrode (E1) of the second transistor (1130), and the gate (G) of the second transistor (1130);

the substrate structure (110) further comprises a first metal portion (1161) located in the one first opening and connected to the electrode corresponding to the one first opening, wherein the area of the one first opening is greater than or equal to 50% of the area of the corresponding electrode.

21. The method of claim 20, wherein,

the second surface (S2) has at least one second opening in one-to-one correspondence with each electrode of a second group of electrodes comprising at least one of the first electrode (E1) of the first transistor (1120), the gate (G) of the first transistor (1120), and the second electrode (E2) of the second transistor (1130);

the first metal layer (1140) includes a second metal portion (1141) in the at least one second opening and connected to an electrode corresponding to the at least one second opening.

22. The method of claim 21, wherein the substrate structure (110) further comprises a second insulating layer (1150) on a side of the first metal layer (1140) remote from the first insulating layer (1110);

the method further comprises the following steps:

and arranging a control chip (120) on one side of the second insulating layer (1150) far away from the first metal layer (1140), wherein the control chip (120) is respectively connected to the grid (G) of the first transistor (1120) and the grid (G) of the second transistor (1130).

23. The method of claim 22, wherein providing a substrate structure (110) comprises:

forming an initial insulating layer encasing the first transistor (1120) and the second transistor (1130), the initial insulating layer having a first initial surface and a second initial surface;

-forming said one first opening in said first initial surface to obtain said first surface (S1), and forming said first metal portion (1161) filling said one first opening;

forming said at least one second opening in said second initial surface to obtain said second surface (S2), and forming said first metal layer (1140) filling said at least one second opening; and

forming the second insulating layer (1150) on a side of the first metal layer (1140) away from the first insulating layer (1110).

24. The method of claim 23, wherein forming an initial insulating layer that encapsulates the first transistor (1120) and the second transistor (1130) comprises:

fixing the first transistor (1120) and the second transistor (1130) to one side of a support at intervals;

forming a first initial insulating sub-layer (1110 a) on the one side of the support, the first initial insulating sub-layer (1110 a) having one of the first initial surface and the second initial surface;

removing the support; and

after removing the support, forming a second initial insulating sub-layer (1110 b) on a side of the first initial insulating sub-layer (1110 a) where the support was removed, the second initial insulating sub-layer (1110 b) having the other of the first initial surface and the second initial surface.

25. The method of claim 24, wherein said first initial insulating sub-layer (1110 a) has said second initial surface;

after forming the first metal layer (1140), the supports are removed.

26. The method of claim 24, wherein the support is an adhesive tape.

27. The method of claim 23, wherein the first surface (S1) further has at least one third opening, the second surface (S2) further has at least one fourth opening, the substrate structure (110) further comprises a third metal portion (1162) in the at least one third opening, the first metal layer (1140) further comprises a fourth metal portion (1142) in the at least one fourth opening, the third metal portion (1162) being connected to the first metal layer (1140) via a fifth metal portion (1170) and the fourth metal portion (1142) extending in the first insulating layer (1110), in that order;

wherein the initial insulating layer further covers the fifth metal portion (1170).

28. The method of claim 22, wherein the substrate structure (110) further comprises a sixth metal portion (1181) and a seventh metal portion (1182) on a side of the second insulating layer (1150) away from the first metal layer (1140), the sixth metal portion (1181) being in contact with the control chip (120) and configured to be grounded, the seventh metal portion (1182) being configured to be connected to an input of the converter (100);

the method further comprises the following steps:

a first capacitor (130) is disposed on a side of the second insulating layer (1150) away from the first metal layer (1140), a first end of the first capacitor (130) is connected to the sixth metal portion (1181), and a second end of the first capacitor (130) is connected to the seventh metal portion (1182).

29. The method of claim 22, further comprising:

-providing an electronic component (140) at a side of the control chip (120) remote from the substrate structure (110), the electronic component (140) comprising an inductor (1410), a first end of the inductor (1410) being connected to the first electrode (E1) of the first transistor (1120) and the second electrode (E2) of the second transistor (1130), a second end of the inductor (1410) being configured to be connected to an output of the converter (100).

30. The method of claim 29, wherein the electronic component (140) further comprises a second capacitor (1420), a first end of the second capacitor (1420) being connected to the second end of the inductor (1410), a second end of the second capacitor (1420) being configured to be ground.