CN115276653A - Calibration device and method for pipelined analog-to-digital conversion circuit and laser radar - Google Patents

Abstract

The calibration device and method for the pipelined analog-to-digital conversion circuit and the laser radar, wherein the pipelined analog-to-digital conversion circuit comprises a pipelined analog-to-digital conversion circuit, the pipelined analog-to-digital conversion circuit comprises a front end conversion module with at least one stage of conversion module and a back end conversion module with at least one stage of conversion module, and the calibration method comprises the following steps: inputting a test analog signal into the pipelined analog-to-digital conversion circuit so that the front-end conversion module receives the test analog signal and outputs a corresponding analog residual signal to the rear-end conversion module; acquiring residual digital information corresponding to the analog residual signal; and judging whether the gain of the front-end conversion module has deviation or not according to the residual digital information. By adopting the scheme, the gain calibration of the pipelined analog-to-digital conversion circuit is realized, the effective gain error can be calibrated, the accuracy of the pipelined analog-to-digital conversion circuit can be improved, and the power consumption requirement under the same accuracy is reduced.

Description

Calibration device and method for pipelined analog-to-digital conversion circuit and laser radar

Technical Field

The embodiment of the specification relates to the technical field of integrated circuits, in particular to a calibration device and method for a pipeline analog-to-digital conversion circuit and a laser radar.

Background

Many physical quantities in nature (such as speed, pressure, temperature, sound, etc.) vary continuously in time and also continuously in amplitude, such continuously varying physical quantities are called analog quantities, and signals representing the analog quantities are called analog signals.

Another type of physical quantity corresponding to an analog quantity is called a digital quantity, which is a numerical value obtained at a series of discrete time instants, and the magnitude and increase and decrease of the numerical value are integer multiples of quantization, that is, they are a series of time-discrete, numerical-discrete signals. A Signal representing a Digital quantity is called a Digital Signal (Digital Signal).

With the widespread use of computers, most electronic systems employ computers to process signals, and the computers cannot directly process Analog signals but only Digital signals, so that Analog/Digital (a/D) conversion technology is required to convert Analog signals into Digital signals, and a circuit for converting Analog signals into Digital signals can be referred to as an Analog-to-Digital conversion circuit.

The analog-to-digital conversion process mainly comprises the following steps: 1) In the sampling period, sampling is carried out on the analog signal to obtain an analog sampling signal which is discrete in time and continuous in amplitude, wherein the continuous amplitude means that the amplitude is not quantized and is still the same as the amplitude of the analog signal; 2) In the holding stage, the amplitude (namely sampling value) of the analog signal is held when the sampling stage is switched to the holding stage, the analog holding signal which is discrete in time and takes the sampling value as the amplitude is obtained, a quantization unit is selected, the sampling value is divided by the quantization unit and an integer is taken, the signal quantization (digitization) is realized, and the digital quantity which is discrete in time and also discrete in numerical value is obtained; 3) The digital quantity is encoded to obtain a corresponding thermometer code, forming a digital signal.

For the convenience of computer use, a binary coding method is generally adopted to obtain a thermometer code with a certain number of bits, and the number of bits of the thermometer code is usually used to represent the number of bits of a digital signal, such as a 10-bit (bit) digital signal. The more bits a digital signal takes, the more accurately an analog signal can be reflected.

In the quantization process of the analog-to-digital conversion, a plurality of comparators are usually used to compare the analog hold signals to obtain the quantization result. Therefore, the more the number of comparators is, the higher the quantization precision is, and the more accurate the output digital signal is, without changing other parameters. However, due to the limitations of space layout, cost, performance and other indexes, digital signals with more bits cannot be obtained by simply and roughly adding comparators.

For example, if an analog signal is to be converted into a 10-bit digital signal, in principle, 1023 comparators may be used to output 1024 digital quantities, and the obtained digital quantities may be encoded to obtain a 10-bit digital signal. A 10bit digital signal would require thousands of comparators and it is thought that this is not possible in practice.

In order to obtain digital signals with more digits under a certain number of comparators, the structure of the analog-to-digital conversion circuit is optimized, and analog-to-digital conversion circuits such as a successive approximation type, an integral type, a pressure-frequency conversion type, a hierarchical type and a pipeline type appear, and the analog-to-digital conversion circuits of the successive approximation type, the integral type and the pressure-frequency conversion type are mainly applied to analog-to-digital conversion scenes with medium-low speed and low precision. The hierarchical and pipelined analog-to-digital conversion circuits can be applied to analog-to-digital conversion scenes with higher speed and higher precision, for example, transient signal processing under the condition of high speed.

A hierarchical quantization structure exists in the pipelined analog-to-digital conversion circuit, and conversion work such as sampling, quantization, coding and the like is performed through a multi-level low-precision conversion module. For each level of conversion module, the rapid analog-to-digital conversion of the level can be realized by adopting a small number of comparators, and the method is the mainstream choice for realizing the high-speed high-precision analog-to-digital conversion at present.

In the pipelined analog-to-digital conversion circuit, after the conversion work is completed by the conversion module of the current stage, the analog component acquired by the current stage needs to be subtracted from the received signal, and the operation result is amplified to a degree suitable for the next stage to perform the conversion work. However, in practice, due to the problem of limited gain error, there may be a deviation between the actual gain (i.e., the actual amplification factor) and the theoretical gain (i.e., the theoretical amplification factor), which increases the error of the subsequent processing and affects the accuracy of the output result of the pipeline analog-to-digital conversion circuit.

The current coping scheme is to provide higher gain (namely amplification factor) and bandwidth for the circuit at the cost of sacrificing the power consumption of the circuit, and although the influence of limited gain error is reduced to a certain degree, the accurate output result of the pipelined analog-to-digital conversion circuit still cannot be guaranteed.

Disclosure of Invention

In view of this, embodiments of the present disclosure provide a calibration apparatus and method for a pipelined analog-to-digital conversion circuit, and a laser radar, so as to implement gain calibration on the pipelined analog-to-digital conversion circuit, which is beneficial to calibrate an effective gain error, and thus, the accuracy of the pipelined analog-to-digital conversion circuit can be improved, and the power consumption requirement under the same accuracy is reduced.

An embodiment of the present disclosure provides a calibration method for an analog-to-digital conversion circuit, where the analog-to-digital conversion circuit includes a pipelined analog-to-digital conversion circuit, where the pipelined analog-to-digital conversion circuit includes a front-end conversion module having at least one stage of conversion module and a back-end conversion module having at least one stage of conversion module, and the calibration method includes:

inputting a test analog signal into the pipelined analog-to-digital conversion circuit so that the front-end conversion module receives the test analog signal and outputs a corresponding analog residual signal to the rear-end conversion module;

acquiring residual digital information corresponding to the analog residual signal;

and judging whether the gain of the front-end conversion module has deviation or not according to the residual digital information.

Embodiments of the present specification also provide a calibration apparatus for an analog-to-digital conversion circuit, where the analog-to-digital conversion circuit includes: the pipelined analog-to-digital conversion circuit comprises a front-end conversion module with at least one stage of conversion module, a rear-end conversion module with at least one stage of conversion module and a digital calculation module, wherein the digital calculation module is suitable for calculating to obtain output digital information according to thermometer codes and corresponding digital domain weights output by each stage of conversion module; the calibration device includes:

the signal generating module is suitable for generating a test analog signal and inputting the test analog signal into the pipelined analog-to-digital conversion circuit so that the front-end conversion module receives the test analog signal and outputs a corresponding analog residual signal to the rear-end conversion module;

and the deviation detection module is suitable for acquiring residual digital information corresponding to the analog residual signal and judging whether the gain of the front-end conversion module has deviation or not according to the residual digital information.

An embodiment of the present specification further provides a laser radar, including: the detection device, the analog-to-digital conversion circuit and the calibration device of any one of the above embodiments; wherein:

the detection device is suitable for collecting echo signals and outputting analog signals to be processed to the analog-to-digital conversion circuit;

the analog-to-digital conversion circuit is suitable for performing analog-to-digital conversion on the analog signal to be processed of the detection device or the test analog signal of the calibration device; the device comprises a pipelined analog-to-digital conversion circuit, wherein the pipelined analog-to-digital conversion circuit comprises a front-end conversion module with at least one stage of conversion module, a rear-end conversion module with at least one stage of conversion module and a digital calculation module;

the calibration device is suitable for calibrating the pipelined analog-to-digital conversion circuit according to the generated test analog signal.

By adopting the calibration method for the analog-to-digital conversion circuit provided by the embodiment of the specification, the analog residual signal in the analog domain is measured and converted into the residual digital information in the digital domain for calculation, so that the gain of the front-end conversion module is verified through the residual digital information, the secondary error generated by measuring the analog residual signal can be avoided, and the calibration accuracy of the effective gain error can be improved; moreover, the calibration method provided in the embodiments of the present specification is implemented based on the existing hardware architecture of the pipelined analog-to-digital conversion circuit, and a better calibration effect can be achieved by combining the existing logic operation device, so that the hardware cost and implementation complexity required for calibration can be effectively reduced, the response speed and execution speed of calibration are improved, the calibration efficiency is higher, and the calibration method has stronger universality.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present specification, the drawings needed to be used in the embodiments of the present specification or in the description of the prior art will be briefly described below, it is obvious that the drawings described below are only some embodiments of the present specification, and it is also possible for a person skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic diagram of a conventional pipelined analog-to-digital conversion circuit.

Fig. 2 is a schematic connection diagram of a conventional sub analog-to-digital conversion unit.

Fig. 3 is a schematic diagram of a conventional gain dac.

Fig. 4 is a graph of input and output curves of a prior art conversion module.

Fig. 5 is a graph of the input and output of the corresponding conversion module of fig. 4 after reducing the gain.

Fig. 6 is a flowchart of a calibration method for an analog-to-digital conversion circuit in an embodiment of the present disclosure.

Fig. 7a is a schematic diagram of another conventional pipelined analog-to-digital conversion circuit.

Fig. 7b is a schematic diagram of another conventional pipelined analog-to-digital conversion circuit.

Fig. 8 is a graph of the input signal and the digital residual information of the front-end transform module in the embodiment of the present disclosure.

Fig. 9a is a schematic diagram of a prior art ramp generator circuit.

Fig. 9b is a waveform diagram of an analog signal output by the ramp generator circuit shown in fig. 9 a.

Fig. 10 is a block diagram of a conventional 12-bit precision pipelined analog-to-digital conversion circuit.

Fig. 11 is a schematic diagram illustrating a connection between an analog-to-digital conversion circuit and a calibration apparatus in an embodiment of the present disclosure.

Fig. 12 is a block diagram of a calibration apparatus for an analog-to-digital conversion circuit in an embodiment of the present disclosure.

Fig. 13 is a block diagram of a laser radar in an embodiment of the present specification.

Detailed Description

In order to make the solution provided by the present disclosure more clearly understood and implemented by those skilled in the art, a schematic description is first given below with reference to the accompanying drawings and specific application scenarios.

Referring to fig. 1, a schematic diagram of a conventional pipelined analog-to-digital conversion circuit is provided, and in practical application, as shown in fig. 1, the pipelined analog-to-digital conversion circuit P0 may include: the circuit comprises a clock generation sub-circuit 01, a band-gap reference sub-circuit 02, a sample-hold amplification module 03, N cascaded conversion modules and a digital calculation module 04. The following describes each component of the pipelined analog-to-digital conversion circuit P0.

The clock generating sub-circuit 01, i.e. the clock source of the pipelined analog-to-digital converting circuit P0, is adapted to generate a plurality of clock signals with non-overlapping phases, and respectively provide the plurality of clock signals with non-overlapping phases to the sample-hold amplifying module 03 and the converting modules Stage1 to Stage n, so that the devices in the sample-hold amplifying module 03 and the converting modules Stage1 to Stage n are controlled to alternately operate by using different time sequences.

The band-gap reference sub-circuit 02, i.e., a reference signal source of the pipelined analog-to-digital conversion circuit P0, is adapted to generate a reference current and a reference voltage, and provide the generated reference current and reference voltage to the sample-hold amplifying module 03 and the conversion modules Stage1 to Stage n, respectively.

Specifically, in an alternative example, as shown in fig. 1, the bandgap reference sub-circuit 02 may include: a bandgap generation module 021, a reference current generation module 022, and a reference voltage generation module 023.

The Bandgap generation module 021, namely, the Bandgap reference source (Bandgap) of the pipelined analog-to-digital conversion circuit P0, is adapted to provide temperature-insensitive reference electrical signals, such as a reference voltage signal and a reference current signal.

The reference current generating module 022, that is, the reference current source of the pipelined analog-to-digital converting circuit P0, is adapted to generate a reference current according to the reference electrical signal, and provide the generated reference current to the sample-hold amplifying module 03 and the Stage converting modules Stage1 to Stage n, respectively.

The reference voltage generating module 023 is a reference voltage source of the pipelined analog-to-digital converting circuit P0, and is adapted to generate a reference voltage according to the reference electrical signal, and provide the generated reference voltage to the sample-hold amplifying module 03 and the Stage converting modules Stage1 to Stage n, respectively.

Further, since the reference voltage is generally used to drive the capacitor, and the capacitor has a charging time and a discharging time, in order to enable efficient charging and discharging operations of the capacitor and provide a precise setup time for the reference voltage generating module 023, the bandgap reference sub-circuit 02 may further include a reference voltage buffering module 024 adapted to buffer the reference voltage output by the reference voltage generating module 023. The Reference voltage Buffer module 024 may include a Buffer (Reference Buffer).

In addition, since the pipelined analog-to-digital conversion circuit generally requires two reference voltages of different levels, for example, a reference voltage of a positive level and a reference voltage of a negative level, the reference voltage generation module 023 needs to perform level shifting to generate the reference voltages of two different levels, thereby ensuring the accuracy and setup time of the reference voltages for the reference voltage generation module 023 through the reference voltage buffer module 024.

The sample-hold amplifying module 03 is adapted to sample the analog signal input to the pipelined analog-to-digital converting circuit P0 to obtain an analog hold signal VC, and stably hold the amplitude of the analog hold signal VC until the next sampling stage comes, and perform the next sampling. Therefore, time deviation is avoided when each subsequent cascaded conversion module carries out processing. The Sample-Hold amplifying module 03 may include a Sample/Hold Amplifier (SHA).

It is to be understood that the above sampling embodiments may be set according to specific scenarios and requirements, and the present specification is not limited thereto.

The N cascaded conversion modules may specifically include a conversion module Stage1, a conversion module Stage2 to a conversion module Stage N-1, and a conversion module Stage N, and the levels of the conversion modules are set according to the cascade order of the conversion modules, as shown in fig. 1, the conversion module Stage1 is a first level, and the conversion module Stage2 is a second level, and the like.

In each of the conversion modules Stage1 to Stage N, the conversion modules Stage1 to Stage N-1 of the first Stage adopt the same internal configuration. Taking the first Stage of the conversion module Stage1 as an example, as shown in fig. 1, the conversion module Stage1 may include: a Sub Analog to Digital conversion unit (Sub-ADC) 11 and a gain Digital to Analog Converter (MDAC) 12.

The sub-analog-to-digital conversion unit 11 samples, quantizes and encodes the received input signal to obtain a first-stage thermometer code DS1, and outputs the first-stage thermometer code DS1 to the gain digital-to-analog conversion unit 12 and the digital calculation module 04, respectively. The number of thermometer codes that can be generated by the sub-analog-number conversion unit 11 is related to the accuracy of the sub-analog-number conversion unit. If the sub-ADC unit 11 has x bits of precision, the sub-ADC unit 11 can generate 2^x-a 1-bit thermometer code.

The gain digital-to-analog conversion unit 12 may include: an arithmetic unit 121, a Sub-digital-to-analog conversion unit (Sub-DAC) 122, and an amplification unit 123. Here, the accuracy of the gain digital-to-analog conversion unit 12 is generally equal to the accuracy of the sub analog-to-digital conversion unit 11. If the sub-adc 11 has an accuracy of x bits, the gain adc 12 also has an accuracy of x bits.

Specifically, the sub digital-to-analog conversion unit 122 is adapted to receive the first-stage thermometer code DS1 output by the sub analog-to-digital conversion unit 11, convert the first-stage thermometer code DS1 into a corresponding first-stage analog component, and output the first-stage analog component to the operation unit 121. The operation unit 121 is adapted to receive the analog hold signal VC output by the sample-and-hold amplification module and the first-stage analog component output by the sub analog-to-digital conversion unit 11, subtract the first-stage analog component from the analog hold signal VC, and output the operation result to the amplification unit 123. The amplifying unit 123 is adapted to receive the operation result output by the operation unit 121, amplify the operation result to obtain a first-Stage analog residual error signal VR1 with the analog residual error amount as an amplitude, and output the first-Stage analog residual error signal VR1 to the second-Stage conversion module Stage2. The amplifying unit may be a transconductance Amplifier (OTA).

The conversion modules Stage2 to Stage n-1 also include a sub-analog-to-digital conversion unit and a gain analog-to-digital conversion unit, and specific reference may be made to the related description of the conversion module Stage1, which is not described herein again.

Therefore, the conversion modules Stage2 to Stage N-1 can obtain the thermometer codes and the analog residual error signals of the corresponding levels according to the received input signals (i.e. the signals output by the previous conversion module), output the thermometer codes of the corresponding levels to the digital calculation module 04, and output the analog residual error signals of the corresponding levels to the next conversion module, specifically referring to fig. 1, the conversion module Stage2 outputs the second-level thermometer codes DS2 to the digital calculation module 04, and outputs the second-level analog residual error signals VR2 to the next conversion module (not shown in fig. 1), and so on, the conversion module Stage N-1 outputs, outputs the N-1-th-level thermometer codes DSN-1 to the digital calculation module 04, and outputs the N-1-th-level analog residual error signals VRN-1 to the next conversion module Stage N.

For the conversion module StageN of the nth stage, which is the last one of the N cascaded conversion modules, the conversion module StageN may include only a sub analog-to-digital conversion unit (not shown in fig. 1), and output the nth stage thermometer code DSN to the digital calculation module 04 according to the analog residual signal output by the nth-1 stage conversion module StageN-1.

It should be noted that the digits of the thermometer codes respectively output by the conversion modules Stage1 to StageN at each level may be set according to specific scenes and requirements, and the conversion modules at each level may output thermometer codes with the same digits or thermometer codes with different digits, which is not limited in this specification.

The digital calculation module 04 is adapted to perform staggered addition on the thermometer codes output by each stage of conversion module according to the stage, so as to perform time alignment on the thermometer codes obtained by different stages of conversion modules at different times, and perform binary conversion to obtain binary output codes. Wherein the number of output codes generated by the digital computation module 04 is related to the accuracy of the digital computation module 04. If the precision of the digital computation module 04 is m bits, then 2 can be generated by the digital computation module 04^m-1 output code. In addition, the precision of the digital computation module 04 may represent the precision of the pipeline analog-to-digital conversion circuit P0.

After introducing the framework of the conventional pipelined analog-to-digital conversion circuit, the following describes specific hardware structures and connection relationships of the sub analog-to-digital conversion unit and the gain digital-to-analog conversion unit by specific embodiments, so as to point out the problems in the prior art.

It should be noted that the sub-analog-to-digital conversion units and the gain analog-to-digital conversion units in the following examples are only used for schematically illustrating technical problems, and in practical application, the conversion modules Stage1 to Stage n may include the following sub-analog-to-digital conversion units, or may include other types of sub-analog-to-digital conversion units; similarly, the conversion modules Stage1 to Stage n-1 may include the following gain digital-to-analog conversion units, and may also include other types of gain digital-to-analog conversion units. This is not limited by the present description.

In an alternative example, as shown in fig. 2, which is a schematic connection diagram of a conventional sub analog-to-digital conversion unit, with reference to fig. 1, in fig. 2, the sub analog-to-digital conversion unit with K-1bit precision may include K resistors R₁、R₂To R_K-2，R_K-1And R_KK-1 comparators C₁、C₂To C_K-2And C_K-1。

Referring to fig. 1 and 2 in combination, in the sub analog-to-digital conversion unit 11, a resistor R_kOne end of the resistor is connected to a first reference voltage Vref1 and a resistor R₁One end of the resistor is connected with a second reference voltage Vref2, and K resistors R₁To R_KThe two ends are connected end to end, wherein the first reference voltage Vref1 is greater than the second reference voltage Vref2. Thus, the K resistors divide a voltage difference formed by the first reference voltage Vref1 and the second reference voltage Vref2.

For K-1 comparators C₁To C_K-1One input end is respectively coupled between two different resistors so as to be respectively connected with a comparative reference voltage with sequentially increased voltage values, and the other input end is connected with an input signal V_inWherein the input signal V_inThe analog holding signal output by the sample-hold amplifying circuit or the signal output by the conversion module of the previous stage can be used.

Each comparator C₁To C_K-1A comparison reference voltage and an input signal V respectively connected thereto_inThe amplitudes are compared to obtain comparison results d 1-dk-1, and the comparison results d 1-dk-1 are output to the digital computation module 04 as thermometer codes.

Wherein, according to K-1 comparators C₁To C_K-1The magnitude order of the comparative reference voltages switched in, comparators C₁To C_K-1The output comparison results d 1-dk-1 are arranged from low to high, i.e. comparator C₁The output comparison result d1 is the least significant bit of the thermometer code, and the comparator C_k-1The output comparison result dk-1 is the most significant bit.

And, due to each comparator C₁To C_K-1The comparison reference voltages respectively connected are increased in turn, so that they are dependent on the input signal V_inThe thermometer code changes from the least significant bit, and the input signal V is characterized only by the logic value of the first-order significant bit in the thermometer code (e.g., logic value "1")_inIs greater than the corresponding comparison reference voltage, the logic value of the one-level significant bit in the thermometer code may change, for example, with the input signal V_inThe thermometer code may change from "00 … …" to "00 … …" but not "00 … … 10".

Accordingly, as shown in fig. 3, which is a connection schematic diagram of a conventional gain digital-to-analog conversion unit, with reference to fig. 1 to fig. 3, the gain digital-to-analog conversion unit may include an operation unit 301, a sub-digital-to-analog conversion unit 302, and a transconductance amplifier 303, where the operation unit 301 may include: a first switch CK1, a first capacitor CS, a second capacitor CF, a third switch CK3 and a fourth switch CK4; the sub digital-to-analog conversion unit 302 may include: and a second switch CK2.

The first switch CK1, the first capacitor CS and the second switch CK2 are respectively in one-to-one correspondence, and there may be a plurality of sets of coupled first switch CK1, first capacitor CS and second switch CK2. The number of the first switches CK1, the first capacitors CS and the second switches CK2 is greater than the number of comparators included in the sub analog-digital conversion unit. For example, if the sub analog-to-digital conversion unit in fig. 2 includes K-1 comparators, the gain digital-to-analog conversion unit in fig. 3 may include K first switches CK1, K first capacitors CS, and K second switches CK2.

The K first switches CK1 are coupled to the inverting input "-" of the transconductance amplifier 303 through the first capacitor CS; the second switch CK2 is a Single Pole Double Throw (SPDT) switch, a stationary terminal of the second switch CK2 is respectively connected to the first reference voltage Vref1 and the second reference voltage Vref2, and a moving terminal of the second switch CK2 is coupled between the first switch CK1 and the first capacitor CS. And the number of the first and second electrodes,

the moving ends of the second switches CK2 of K-1 are respectively controlled by the comparison results (i.e. thermometer codes) of the corresponding comparators in the sub analog-to-digital conversion units, and the other second switch CK2 is used for accessing the common mode signal.

The inverting input "-" of the transconductance amplifier 303 is also connected to ground via a third switch CK3 and to its output via two parallel second capacitors CF. The non-inverting input "+" of the transconductance amplifier 303 is directly connected to ground. The output of the transconductance amplifier 303 is also connected to ground through a fourth switch CK 4.

In the sampling phase of the conversion module, the first switch CK1 and the third switch CK3 are turned on, the fourth switch CK4 is turned on, and the first capacitor CS is turned on to receive the input signal V_inInput signal V_inCan be used for the analog hold signal output by the sample-hold amplifying circuit or the transconductance amplification of the signal output by the last stage of conversion moduleThe output of the device 303 is shorted. Assume that the capacitance value of the first capacitor CS is C_sThen, under ideal conditions, the amount of charge Q accumulated at the 303 input terminal of the transconductance amplifier_sComprises the following steps:

Q_s＝KC_sV_in；

in the amplifying stage of the conversion module, the K-1 second switches CK2 are connected with the corresponding first reference voltage Vref1 or second reference voltage Vref2 according to the thermometer code output by the comparator, the reference signals accessed by the K-1 second switches CK2 can be used as analog components of the stage, a closed-loop feedback loop of the transconductance amplifier is formed through the second capacitor CF, and the remaining second switch CK2 is accessed with a common-mode signal.

Assume that the capacitance values of the second capacitors CF are all C_fThen, under ideal conditions (e.g., infinite open loop gain and bandwidth of the amplifying unit), the amount of charge Q accumulated at the input terminal of the transconductance amplifier 303 is larger_fComprises the following steps:

wherein, b_iIndicates the comparison result of the ith comparator, V_refiA reference voltage value indicating that the second switch CK2 corresponding to the ith comparator is turned on; v_inRepresenting the input signal, V, of the transconductance amplifier 303_outRepresenting the output signal (i.e., the analog residual signal) of transconductance amplifier 303.

According to the conservation of charge, the input-output transfer function of the gain digital-to-analog conversion unit can be obtained as follows:

according to the formula, under the ideal condition, the input and the output of each conversion module in the pipelined analog-to-digital conversion circuit are in a linear relationship, and the slope is the theoretical gain.

For example, referring to fig. 1 to fig. 3, if the precision of the pipelined analog-to-digital conversion circuit is 10 bits, the conversion range can be 0 to 1023 under the premise that the transconductance amplifier and the comparator are in an ideal state. In the case of only grading without calibration, the pipelined analog-to-digital conversion circuit may include 4 cascaded conversion modules, i.e., a first-stage conversion module, a second-stage conversion module, a third-stage conversion module, and a fourth-stage conversion module.

The first stage conversion module comprises 7 comparators with the precision of 3bits, so that the [0,1023] interval is divided into eight intervals equally, the span of each interval is 128, and the corresponding code is 000 to 111. According to the first-stage thermometer code output by the first-stage conversion module, it can be determined in which interval the amplitude value (i.e. the sampling value) of the analog hold signal falls, for example, if the first-stage thermometer code is 010, it can be determined that the analog hold signal falls in the [256, 383] interval corresponding to 010. In addition, in order to facilitate the next-stage conversion module to perform conversion, after subtracting the first-stage analog component from the analog hold signal, the operation result is amplified by 8 times and is output to the second-stage conversion module as the first-stage analog residual signal.

The second-stage conversion module comprises 7 comparators with the precision of 3bits, so that the interval corresponding to the first-stage thermometer code is divided into eight intervals, the span of each interval is 16, and the serial numbers are 000-111 respectively. According to the second-stage thermometer code output by the second-stage conversion module, it can be determined into which interval the amplitude of the first-stage analog residual signal falls, for example, if the second-stage thermometer code is 001, it can be determined that the first-stage analog residual signal falls into [272, 287] interval corresponding to 001. In addition, in order to facilitate the next-stage conversion module to perform conversion, after subtracting the second-stage component from the first-stage analog residual signal, the operation result is amplified by 8 times and is output to the third-stage conversion module as the second-stage analog residual signal.

The third-stage conversion module can comprise 15 comparators with the precision of 4bits, so that the corresponding intervals of the second-stage thermometer codes are equally divided into 16 intervals, the span of each interval is 1, and the serial numbers are 0000-1111 respectively. According to the third-stage thermometer code output by the third-stage conversion module, it can be determined into which interval the amplitude of the second-stage analog residual error signal falls, for example, if the third-stage thermometer code is 0001, it can be determined that the second-stage analog residual error signal falls into [273, 273] interval corresponding to 0001, that is, the sampling value is 273.

However, in an actual circuit, the open-loop gain and the bandwidth of the amplifying unit in the pipeline-type analog-to-digital conversion circuit are limited, and thus a problem of limited gain error may occur. Specifically, in conjunction with the related embodiments of fig. 1 to 3, when considering the case of finite gain and small signal settling of the amplification unit, the input-output transfer function of the gain digital-to-analog conversion unit becomes:

where LG represents the loop gain, BW represents the closed-loop bandwidth, and t represents time.

As can be seen from the above equation, the factors that cause the finite gain error may include: the limitation of the performance of the amplifying unit enables the loop gain not to be infinite and the closed loop bandwidth not to be infinite; and the capacitance devices adopted in the sampling stage and the amplifying stage in the circuit have the problem of capacitance mismatch, namely, an error exists between the first capacitor CS and the second capacitor CF, so that the closed-loop gain is reduced.

Due to the finite gain error, the actual gain will deviate from the theoretical gain. Specifically, as shown in fig. 4, it is an input-output curve diagram of a conventional conversion module. Wherein, the input signal V of the conversion module is used_inIs abscissa, and the output signal V of the conversion module_outAnd establishing a coordinate system for vertical coordinates, wherein the precision of the conversion module is 2bit, the + Vref is a first reference voltage, the-Vref is a second reference voltage, and the + Vref and the-Vref form a theoretical analog domain output range of the conversion module. The dotted line represents the theoretical input-output curve of the conversion module in an ideal state, and the solid line represents the actual input-output curve of the conversion module with finite gain error. In fig. 4, the conversion module uses the full scale gain, i.e. the maximum output value of the theoretical input-output curve is located at the boundary of the theoretical analog domain output range.

As can be seen from fig. 4, the actual gain of the conversion module is greater than the theoretical gain, which results in an error in the output signal (i.e., the analog residual signal), even a portion of the output signal that exceeds the output range of the theoretical analog domain exists, and the output signal of the portion will exceed the input range of the theoretical analog domain of the next conversion module, so that the next conversion module cannot measure the output signal, resulting in code loss.

Therefore, the finite gain error will increase the error of the subsequent processing, and affect the accuracy of the output result of the pipelined analog-to-digital converting circuit.

In order to reduce the effect of the limited gain error, in the prior art, digital Redundant bit (RSD) correction is usually adopted, and the error margin that the conversion module can bear is increased by reducing the gain of the amplification unit, reducing the number of comparators and modifying the reference voltage.

Fig. 5 is a graph of the input and output curves of the conversion module corresponding to fig. 4 after the gain is reduced, wherein a dotted line represents a theoretical input and output curve of the conversion module in an ideal state, and a solid line represents an actual input and output curve of the conversion module with a finite gain error. Referring to fig. 4 and 5 in combination, the gain of the conversion module in fig. 5 is reduced by 1/2 compared to the gain at full scale (i.e., the gain of the conversion module in fig. 4), after the gain is reduced, there is a margin between the maximum output value of the theoretical input-output curve and the theoretical analog domain output range, even if the limited gain error causes the actual gain of the conversion module to become large, the actual input-output curve may still be included in the theoretical analog domain output range, so that the next conversion module can measure the output signal.

However, since the original gain of the conversion module is reduced, the precision of the original pipeline analog-to-digital conversion circuit can be achieved only by adding the cascaded conversion module. For example, referring to the above-mentioned embodiment of the 10-bit pipelined analog-to-digital conversion circuit, without changing the output range of the theoretical analog domain, the gain of the first-stage to third-stage conversion modules is changed to the original 1/2, sufficient margin is left for each stage of conversion module to accommodate errors, and a cascaded conversion module is added, so that the original precision is realized by adding the overlapped number of bits through a thermometer code with more bits (e.g. 11 bits) and adjusting the dislocation.

In summary, although the above digital redundancy bit correction scheme can expand the allowable range of the pipelined analog-to-digital conversion circuit for the gain variation, thereby reducing the effect of the limited gain error to some extent, there is still a possibility of exceeding the theoretical analog domain output range and increasing the circuit power consumption. Therefore, the prior art scheme still cannot ensure that the pipelined analog-to-digital conversion circuit outputs an accurate result.

In order to solve the above technical problem, an embodiment of the present disclosure provides a calibration method for an analog-to-digital conversion circuit, where for a pipeline analog-to-digital conversion circuit included in the analog-to-digital conversion circuit, whether a gain of the pipeline analog-to-digital conversion circuit is biased is determined by obtaining information of an analog residual signal transmitted between stages in a digital domain. Therefore, the gain calibration of the pipelined analog-to-digital conversion circuit is realized, the effective gain error can be calibrated, the accuracy of the pipelined analog-to-digital conversion circuit can be improved, and the power consumption requirement under the same accuracy is reduced.

So that those skilled in the art may more clearly understand and practice the concepts, implementations, and advantages of the present description, reference is made to the following detailed description of the embodiments, which is provided in connection with the accompanying drawings.

Referring to fig. 6, a flowchart of a calibration method for an analog-to-digital conversion circuit in an embodiment of the present disclosure is shown. In an embodiment of the present disclosure, the analog-to-digital conversion circuit includes a pipelined analog-to-digital conversion circuit, and the conversion modules cascaded in the pipelined analog-to-digital conversion circuit are divided into two groups, where one group of the conversion modules close to an input end of the pipelined analog-to-digital conversion circuit may be referred to as a front-end conversion module, and the other group of the conversion modules may be referred to as a back-end conversion module, that is, the pipelined analog-to-digital conversion circuit includes a front-end conversion module having at least one stage of conversion modules and a back-end conversion module having at least one stage of conversion modules.

It should be noted that, in this specification, it is only necessary to ensure that both the front-end conversion module and the back-end conversion module include at least one stage of conversion module, and this specification does not make specific limitations regarding the grouping manner of the conversion modules. For example, referring to fig. 1 in combination, the front-end conversion module may include a first Stage conversion module Stage1, and the back-end conversion module may include the remaining stages of conversion modules.

Based on the grouping of the pipelined analog-to-digital conversion circuits, the calibration method provided by the embodiments of the present specification can be implemented. Specifically, as shown in fig. 6, the calibration method may include the steps of:

and S01, inputting a test analog signal into the pipelined analog-to-digital conversion circuit so that the front-end conversion module receives the test analog signal and outputs a corresponding analog residual signal to the rear-end conversion module. Wherein the test analog signal is: a known signal that varies with time.

And S02, acquiring residual digital information corresponding to the analog residual signal. Wherein, the residual digital information is the information of the analog residual signal in the digital domain.

And S03, judging whether the gain of the front-end conversion module has deviation or not according to the residual digital information.

According to the scheme, the measurement of the analog residual error signal in the analog domain is converted into the calculation of the residual error digital information in the digital domain, so that the gain of the front-end conversion module is verified through the residual error digital information, the secondary error generated by the measurement of the analog residual error signal can be avoided, and the calibration accuracy of the effective gain error can be improved; moreover, the calibration method provided in the embodiments of the present specification is implemented based on the existing hardware architecture of the pipelined analog-to-digital conversion circuit, and a better calibration effect can be achieved by combining the existing logic operation device, so that the hardware cost and implementation complexity required for calibration can be effectively reduced, the response speed and execution speed of calibration are improved, the calibration efficiency is higher, and the calibration method has stronger universality.

It should be noted that the pipeline analog-to-digital conversion circuit in fig. 1 is only an example, and in practical applications, as long as the pipeline analog-to-digital conversion circuit includes a back-end conversion module and can acquire residual digital information corresponding to an analog residual signal, the calibration method provided in the embodiment of the present specification can be implemented, and for an actual hardware architecture (such as a connection relationship between hardware and a specific circuit structure) in the pipeline analog-to-digital conversion circuit, the calibration method provided in the embodiment of the present specification is not affected to implement, that is, the calibration method provided in the embodiment of the present specification has stronger universality.

For example, as shown in fig. 7a, a schematic diagram of another conventional pipelined analog-to-digital conversion circuit is shown, wherein the pipelined analog-to-digital conversion circuit P1 is a fully differential signal input-output structure, and specific embodiments thereof can refer to fig. 1 and related descriptions, which are not repeated herein. Fig. 7b is a schematic diagram of another conventional pipelined analog-to-digital conversion circuit, in which the pipelined analog-to-digital conversion circuit P2 does not include a sample-hold amplifying module, so that the power consumption of the circuit can be reduced.

It is to be understood that, in this specification, for convenience of description, a single line is used in some drawings to represent a signal circulation process, but the drawings can be understood to include a fully differential signal input/output structure in nature; also, other modules than the conversion module and the digital calculation module are omitted in some drawings.

In a specific implementation, thermometer codes respectively output by each stage of conversion modules in the rear-end conversion module may be acquired, and the residual digital information may be determined according to the acquired thermometer codes.

Specifically, each stage of conversion modules in the pipelined analog-to-digital conversion circuit is provided with a digital domain weight, so that thermometer codes and corresponding digital domain weights respectively output by each stage of conversion modules in the rear-end conversion module can be acquired, and weighting calculation is performed according to the acquired thermometer codes and the corresponding digital domain weights, so as to obtain the residual digital information.

From the above, through the thermometer code obtained by quantization of the rear-end conversion module in the pipelined analog-to-digital conversion circuit and the set digital domain weight, the information of the residual analog signal output by the front-end conversion module in the digital domain can be reversely calculated, so that the analog residual signal output by the front-end conversion module can be indirectly read, the residual digital information can effectively replace the analog residual signal to perform gain verification of the front-end conversion module, and the hardware architecture of the existing pipelined analog-to-digital conversion circuit is reasonably utilized, thereby reducing the hardware cost and implementation complexity required by calibration, improving the response speed and execution speed of calibration, and enabling the calibration efficiency to be higher.

In an implementation, in order for the back-end conversion module to process the test analog residual signal of the front-end conversion module, the test analog residual signal output by the front-end conversion module should fall within the theoretical analog domain input range of the back-end conversion module. Therefore, the theoretical analog domain output range of the front-end conversion module is matched with the theoretical analog domain input range of the rear-end conversion module.

For example, referring to FIG. 5, if the theoretical analog domain output range of the front-end conversion module is from-Vref to + Vref, the theoretical analog domain input range of the back-end conversion module may be from-Vref to + Vref. For another example, referring to fig. 7, if the theoretical analog domain output range of the front-end conversion module is from-0.5 × vref to +0.5 × vref, the theoretical analog domain input range of the back-end conversion module may be from-0.5 × vref to +0.5 × vref.

Because the digital residual error information is the information of the analog residual error signal between the front-end conversion module and the rear-end conversion module in the digital domain, and the analog residual error signal and the digital residual error information have a corresponding relationship, a theoretical digital domain output range also exists in the theoretical analog domain output range of the front-end conversion module, and a corresponding theoretical digital domain input range also exists in the theoretical analog domain input range of the rear-end conversion module.

The theoretical digital domain output range is related to the digital domain weight corresponding to the least significant bit in the front-end conversion module and the adopted digital correction method, and the theoretical digital domain input range is related to the adopted digital correction method by the digital domain weight corresponding to the most significant bit in the rear-end conversion module.

For example, as shown in fig. 8, it is a graph of the input signal of the front-end transform module and the digital residual information. The ordinate is the residual error number corresponding to the analog residual error signal output by the front-end conversion moduleInformation D_out1The abscissa is the input signal V of the front-end conversion module_in1. If the digital domain weight corresponding to the least significant bit in the front-end conversion module is W_LSB1And the gain of each stage of conversion module of the pipelined analog-to-digital conversion circuit is reduced by 1/2 compared with the gain at full scale, so that the theoretical digital domain output range of the front-end conversion module can be 0.5 xW_LSB1To 1.5W_LSB1Therefore, the theoretical digital domain input range of the rear-end conversion module can also be 0.5W_LSB1To 1.5W_LSB1。

Based on this, the determining whether there is a deviation in the gain of the front-end transform module according to the residual digital information may include: judging whether the output range of the measurement digital domain corresponding to the residual digital information is consistent with the current theoretical digital domain output range of the front-end conversion module; and when the gain of the front-end conversion module is inconsistent with the gain of the front-end conversion module, judging that an error exists in the gain of the front-end conversion module.

Here, "current" may be understood as a time period during which the gain deviation determination of the front-end conversion module is performed. Measuring the digital domain output range means: and representing the range of the analog residual signal actually output by the front-end conversion module in the digital domain (namely the actual digital domain output range of the front-end conversion module) by the digital domain range obtained by the residual digital information.

Specifically, since the test analog signal input to the pipelined analog-to-digital conversion circuit changes with time and the change of the test analog signal is known, a plurality of residual digital information can be obtained after sampling for a plurality of times, and a measurement digital domain output range can be obtained according to the residual digital information obtained for a plurality of times, thereby determining whether the gain of the front-end conversion module has a deviation.

For example, with reference to fig. 8, with the change of the test analog signal, 5 times of sampling are performed to obtain 5 times of residual digital information, coordinates are formed between the test value when the test analog signal is sampled and the corresponding residual digital information to obtain test points Q1 to Q5 in fig. 8, and thus it can be obtained that the output range of the measurement digital domain of the front-end conversion module is W_c1To W_c2. As is apparent from fig. 8, the output range of the measurement digital domain is not consistent with the output range of the theoretical digital domain, and it can be determined that an error exists in the gain of the front-end conversion module.

Therefore, the difference between the actual digital domain output range and the theoretical digital domain output range of the front-end conversion module can be judged by reasonably and efficiently utilizing the existing hardware architecture of the pipelined analog-to-digital conversion circuit and the measured digital domain output range obtained by residual digital information, so that the hardware cost and implementation complexity required by calibration are reduced, the response speed and execution speed of calibration are improved, the calibration efficiency is higher, and the calibration has stronger universality.

In specific implementation, in order to quickly obtain the output range of the measurement digital domain and reduce the data amount, when the test analog signal changes to the boundary value of the output range of the theoretical digital domain, the pipeline analog-to-digital conversion circuit is used for sampling, and then, corresponding residual digital information is obtained, wherein the residual digital information is the boundary value of the output range of the theoretical digital domain, so that the output range of the measurement digital domain can be directly deduced, the operation amount is reduced, and the processing speed is increased.

For example, as shown in FIG. 8, the analog signal V may be tested_in1When the measured value is changed to V1, the pipelined analog-to-digital conversion circuit is enabled to carry out conversion work, and residual digital information W corresponding to the analog residual signal is obtained_c1A boundary value of the theoretical digital domain output range; accordingly, the analog signal V can be tested_in1When the measured value is changed to V2, the pipelined analog-to-digital conversion circuit is enabled to carry out conversion work, and residual digital information W corresponding to the analog residual signal is obtained_c2I.e. another boundary value of the theoretical digital domain output range. Obtaining the output range of the measurement digital domain of the front-end conversion module as W_c1To W_c2。

In specific implementation, whether the measurement gain corresponding to the residual digital information is consistent with the theoretical gain of the front-end conversion module or not can be judged according to the measurement value of the test analog signal at the measurement time and the current theoretical digital domain output range of the front-end conversion module; and when the gain of the front-end conversion module is inconsistent with the gain of the front-end conversion module, judging that an error exists in the gain of the front-end conversion module.

Wherein, the measurement gain refers to: the gain obtained by the residual digital information is used for representing the gain of the analog residual signal actually output by the front-end conversion module in a digital domain (namely the actual digital domain gain of the front-end conversion module)

Specifically, although the finite gain error affects the gain of the amplifying unit in the transform module, that is, the slope of the input/output curve of the transform module changes, as can be seen from fig. 5, when the analog residual signal is inputted with V_outThe point of =0 is not changed, as is the point Q3 in fig. 5. These points have corresponding points in the curve of the input and residual digital information of the front-end transform module, such as the point Q3 in fig. 8. Therefore, these points can be taken as reference points. And, since the change of the test analog signal is known, the current measurement value of the test analog signal can be determined, so as to form the coordinate of the measurement point by combining with the residual digital information, and the actual slope, namely the measurement gain of the front-end conversion module, can be calculated according to the reference point and the measurement point.

Then, the measured gain corresponding to the residual digital information is compared with the theoretical gain of the front-end conversion module, whether the measured gain and the theoretical gain are consistent or not is judged, and if the measured gain and the theoretical gain are not consistent, it is judged that the gain of the front-end conversion module has an error. As shown in fig. 8, if the reference point is Q3, the measurement point is Q4, and the dotted line represents a theoretical curve corresponding to the test analog signal and the residual digital information of the front-end conversion module, it can be found that the slope calculated from the reference point Q3 and the measurement point Q4 is greater than the slope of the theoretical curve.

Therefore, the existing hardware architecture of the pipelined analog-to-digital conversion circuit can be reasonably and efficiently utilized, and the difference between the actual gain and the theoretical gain of the front-end conversion module can be judged through the measurement gain obtained by the residual digital information, so that the hardware cost and implementation complexity required by calibration are reduced, the response speed and execution speed of calibration are improved, the calibration efficiency is higher, and the universality is stronger.

In an alternative example, reference to FIG. 5 may be madeIt is known that the slope of the input-output curve changes under the influence of finite gain error, but at V_outThe point of =0 is not changed, as is the point Q3 in fig. 5. These points have corresponding points in the curve of the input and residual digital information of the front-end transform module, such as the point Q3 in fig. 8. Therefore, these points can be used as reference points. And, because the change of the test analog signal is known, the current measurement value of the test analog signal can be determined, so as to form the coordinate of the measurement point by combining with the residual digital information, and the actual slope, i.e. the measurement gain of the front-end conversion module, can be calculated according to the reference point and the measurement point, so as to derive the output range of the measurement digital domain corresponding to the residual digital information, if the reference point is Q3 and the measurement point is Q2 in fig. 8, it can be obtained that the output range of the measurement digital domain is W_c1To W_c2。

In specific implementation, in order to avoid erroneous judgment and improve the accuracy and reliability of the judgment result, multiple groups of residual digital information can be obtained, so as to respectively judge whether the gain of the front-end conversion module has deviation or not and obtain multiple groups of judgment results; and then carrying out statistics on the multiple groups of judgment results to determine a final judgment result. For example, it is possible to finally determine whether or not there is a variation in the gain of the front-end conversion module, based on the ratio of the result determined to have a variation to the plurality of sets of determination results.

In an implementation, when the gain of the front-end conversion module is deviated, the gain of the front-end conversion module can be corrected. Specifically, as shown in fig. 6, the calibration method for the analog-to-digital conversion circuit further includes the steps of: and S04, when deviation exists, adjusting the digital domain weight corresponding to the front-end conversion module according to the residual digital information.

Wherein, the adjustment direction of the digital domain weight is as follows: approaching to the direction of the actual gain of the front-end conversion module.

Because the weighting calculation needs to be carried out through the digital domain weight when the output digital information is calculated, the digital domain weight corresponding to the front-end conversion module can represent the gain of the front-end conversion module in a digital domain, and on the basis, the digital domain weight corresponding to the front-end conversion module is adjusted, so that the numerical calculation of the part related to the front-end conversion module in the output numerical information calculation process can be corrected, the theoretical digital domain output range of the front-end conversion module is indirectly modified, and the calculated output digital information can better reflect the actual conversion capability of the pipelined analog-to-digital conversion circuit.

Therefore, by adjusting the digital domain weight to the size consistent with the actual gain capability of the front-end conversion module, the reliability and the accuracy of the output result of the pipelined analog-to-digital conversion circuit can be improved under the condition of not changing the existing hardware architecture of the pipelined analog-to-digital conversion circuit, and the power consumption requirement under the same accuracy is reduced.

In addition, in the actual analog-to-digital conversion process, the pipeline analog-to-digital conversion circuit calibrated by the calibration method described in the embodiments of the present specification has more accurate and reliable output digital information, and therefore, the value of the analog signal to be processed can be more accurately estimated according to the output numerical information of the pipeline analog-to-digital conversion circuit after calibration.

In an implementation example, if the span of the current theoretical digital domain output range of the front-end conversion module is greater than the span of the measurement digital domain output range corresponding to the residual digital information, which indicates that the current theoretical digital domain output range of the front-end conversion module is too large, and the actual gain capability of the front-end conversion module is lower than the gain capability in an ideal state, the digital domain weight corresponding to the front-end conversion module can be reduced, that is, the range span that the front-end conversion module can accommodate is reduced, and thus the range approaches the actual output range of the front-end conversion module.

If the span of the current theoretical digital domain output range of the front-end conversion module is smaller than the span of the measurement digital domain output range corresponding to the residual digital information, the representation that the current theoretical digital domain output range of the front-end conversion module is too small and the actual gain capability of the front-end conversion module is higher than the gain capability in an ideal state indicates that the digital domain weight corresponding to the front-end conversion module is increased, that is, the range span which can be accommodated by the front-end conversion module is enlarged, and the actual output range of the front-end conversion module is more approximate.

Specifically, as shown in fig. 8, the dashed lines represent the span of the output range of the current theoretical digital domain of the front-end conversion module; the solid oblique line represents the span of a measurement digital domain output range corresponding to the residual digital information; and the dotted and dashed lines represent the span of the output range of the measurement digital domain corresponding to the other residual digital information.

The dotted oblique line can approach to a real oblique line by improving the weight of the digital domain corresponding to the front-end conversion module; the dotted line can be close to the dotted line by reducing the weight of the digital domain corresponding to the front-end conversion module.

In another implementation example, if the theoretical gain corresponding to the front-end conversion module is greater than the measured gain corresponding to the residual digital information, which indicates that the current theoretical gain of the front-end conversion module is too large, and the actual gain capability of the front-end conversion module is lower than the gain capability in an ideal state, the digital domain weight corresponding to the front-end conversion module may be reduced, so that the theoretical gain corresponding to the front-end conversion module is closer to the actual gain of the front-end conversion module.

If the theoretical gain corresponding to the front-end conversion module is smaller than the measured gain corresponding to the residual digital information, the current theoretical gain of the front-end conversion module is represented to be too small, and the actual gain capability of the front-end conversion module is higher than the gain capability in an ideal state, so that the digital domain weight corresponding to the front-end conversion module can be increased, and the theoretical gain corresponding to the front-end conversion module is closer to the actual gain of the front-end conversion module.

Specifically, as shown in fig. 8, the slope of the dashed line represents the current theoretical gain of the front-end conversion module; the slope of the solid slope represents a measurement gain corresponding to the residual digital information; and the slope of the dot-dash slope represents the measurement gain corresponding to the other type of residual digital information.

The slope of the virtual oblique line can approach the slope of the real oblique line by improving the weight of the digital domain corresponding to the front-end conversion module; by reducing the digital domain weight corresponding to the front-end conversion module, the slope of the dashed oblique line can approach the slope of the dotted oblique line.

In one embodiment, the digital domain weight of at least one of the conversion modules in the front-end conversion module may be adjusted. Further, a digital domain weight corresponding to at least one valid bit in the conversion module may be adjusted. This specification does not specifically limit this.

In specific implementation, because the output result of the first-stage conversion module affects the processing result of the subsequent circuit, the precision and reliability of the first-stage conversion module are most important for the pipelined analog-to-digital conversion circuit, and when the digital domain weight corresponding to the front-end conversion module is adjusted, the digital domain weight of the first-stage conversion module can be set and adjusted, so that the reliability and precision of the circuit are improved.

In a specific implementation, after determining that there is a deviation in the gain of the front-end transform module according to the residual digital information, the correction information of the digital domain weight corresponding to the front-end transform module may be determined according to the residual digital information, where the correction information includes: adjusting direction and correction amount.

For example, the correction information is obtained based on a span difference between the theoretical digital domain output range and the measured digital domain output range, or a difference between the theoretical gain and the measured gain.

In a specific implementation, in order to reduce the calculation amount and quickly adjust the digital domain weight, after the adjustment direction is determined according to the span difference between the theoretical digital domain output range and the measured digital domain output range or the difference between the theoretical gain and the measured gain, a preset correction step length can be obtained as a correction amount, so as to obtain correction information, and thus, the digital domain weight of the front-end conversion module is adjusted according to the preset correction step length and the adjustment direction.

In an implementation, after the digital domain weight adjustment is completed, the test analog signal may be input into the pipeline analog-to-digital conversion circuit again to determine whether there is a deviation in the gain of the front-end conversion module. The test analog signal input again may be a test analog signal input last time, or may be another test analog signal obtained again, and this specification does not specifically limit this.

And when judging the gain deviation again, the current theoretical digital domain output range of the front-end conversion module is determined by the digital domain weight after the last adjustment. Therefore, the digital domain weight is adjusted in multiple times of gain deviation judgment, so that the digital domain weight better conforms to the actual gain condition of the front-end conversion module.

In a specific implementation, in order to reduce the probability of missed judgment, reduce the number of times of gain adjustment, and improve the calibration efficiency, multiple sets of residual digital information may be obtained, so as to ensure that at least one set of judgment results for judging that the gain of the front-end conversion module has a deviation can be obtained when the gain of the front-end conversion module actually has a deviation, and further obtain at least one set of correction information according to the judgment results. And after obtaining multiple groups of correction information according to the multiple groups of residual digital information, the multiple groups of correction information can be counted to determine the correction information finally used for digital domain weight adjustment.

In a specific implementation, the test analog signal may be an analog signal that changes in a single direction, or may also be an analog signal that changes in multiple directions; the test analog signal may be a linearly changing analog signal or a nonlinearly changing analog signal. For example, the test analog signal may be a linear analog signal varying in a single direction, a nonlinear analog signal varying in a single direction, a linear analog signal varying in multiple directions, a nonlinear analog signal varying in multiple directions, and the like, which is not particularly limited in this specification.

Wherein the test analog signal may be generated by a signal generator. In addition, the linear analog signal is convenient to generate and control, and is more beneficial to implementing the calibration method provided by the embodiment of the specification.

In an alternative example, a Ramp Generator (Ramp Generator) may be used to acquire the test analog signal. Specifically, as shown in fig. 9a, a schematic diagram of a conventional ramp generator circuit is shown. In fig. 9a, a constant current source S1 supplies a current I to a capacitor C1, so that the capacitor C1 integrates to generate a voltage vt, and supplies voltages to the gate of the transistor M1, one input terminal of the driver AMP1, and one input terminal of the hysteresis comparator AMP 2; the source electrode of the transistor M1 is connected with another constant current source S2, and the constant current source S2 outputs current 2I; the gate of the transistor M1 is connected to the output terminal of the hysteresis comparator AMP 2; the other input end of the hysteresis comparator AMP2 is connected with a reference voltage VCM; the output end of the driver AMP1 outputs an analog signal VOUT; the output end of the driver APM1 is grounded through a capacitor C2, and noise reduction is achieved.

The transistor M1 is controlled to be turned off and on by the hysteresis comparator AMP2, so that the capacitor C1 is charged and discharged, thereby forming a linearly increasing and decreasing analog signal VOUT at the output terminal of the driver AMP 1. Referring to fig. 9b, which is a waveform diagram of the analog signal output by the ramp generator circuit shown in fig. 9a, wherein V0+ and V0-represent the peak values of the analog signal, the slope of the linear change of the analog signal VOUT is I/C.

According to the linear relation between the analog signal generated by the ramp generator and time, the output end of the ramp generator can be connected with the input end of the pipeline type analog-to-digital conversion circuit in a specified time period, so that the analog signal generated by the ramp generator in the time period is used as a test analog signal to be input into the pipeline type analog-to-digital conversion circuit. The specified time period may correspond to a time period in which the ramp generator generates an analog signal that changes in a single direction (e.g., a part of the analog signal in the region (1) in fig. 9b, a part of the analog signal in the region (2), etc.), or may correspond to a time period in which the ramp generator generates an analog signal that changes in multiple directions (e.g., a part of the analog signal in the region (1) and the region (2) in fig. 9b, etc.).

In a specific implementation, a plurality of test analog signals may be obtained, and each test analog signal is input into the pipelined analog-to-digital conversion circuit, so as to count residual digital information corresponding to each test analog signal and determine whether a gain of the front-end conversion module has a deviation. The test analog signals can change in a single direction and in different changing modes, namely, the slope of each test analog signal is different. And when deviation exists, counting residual digital information corresponding to each test analog signal, and adjusting digital domain weight corresponding to the front-end conversion module. The description of the related embodiments can be combined specifically, and will not be repeated herein.

In a specific implementation, as shown in fig. 6, the calibration method may further include the following steps: s05, judging whether the calibration end conditions are met, if so, acquiring an analog signal to be processed, and performing analog-to-digital conversion processing; otherwise, continuing to calibrate. The calibration duration can thereby be controlled.

The calibration end condition may be set according to the number of times of calibration, a calibration duration, an allowable deviation range (i.e., a range where the deviation may be considered to be absent), and the like, which is not limited in this specification. In order to facilitate those skilled in the art to understand and implement the calibration scheme provided in the present specification, the following exemplary description is provided in conjunction with the accompanying drawings and specific application scenarios.

In an optional example, as shown in fig. 10, a structure diagram of a conventional 12-bit precision pipelined analog-to-digital conversion circuit is shown, where the 12-bit precision pipelined analog-to-digital conversion circuit P3 includes 7 stages of conversion modules, i.e., a Stage1 conversion module Stage11 to a Stage 7 conversion module Stage17, and specific results of the conversion modules may refer to fig. 1 and related contents thereof, which are not described herein again; the 1 st-Stage conversion module Stage11 and the 2 nd-Stage conversion module Stage12 respectively output a 3bits first-Stage thermometer code DS11 and a second-Stage DS12; the 3 rd-6 th-Stage conversion modules Stage 13-Stage 16 respectively output 2bits of third-sixth-Stage thermometer codes DS 13-DS 16; the 7 th Stage conversion module Stage17 outputs a seventh Stage thermometer code DS17 of 4 bits; the front-end conversion module 101 may include a Stage1 conversion module Stage11; the back-end conversion module may include Stage2 to Stage 7 conversion modules Stage12 to Stage17.

When the numerical value calculation module 103 performs the error phase on the thermometer codes DS11 to DS12 of the first-Stage conversion module Stage12 to the seventh-Stage conversion module Stage17, partial bit coincidence exists between the thermometer codes of each Stage, so that the 12bits output code is obtained. Specifically, the following comparative table 1 can be referred to. D 12-d 10 represent the most significant bit to the least significant bit of the first-stage thermometer code DS11, and so on, and d 20-d 73 represent the bits specifically included in the second-stage thermometer code DS12 to the seventh-stage thermometer code DS17, respectively. In addition, the comparison table 1 also shows that the digital domain weights corresponding to the first-Stage conversion module Stage12 to the seventh-Stage conversion module Stage17 are 512, 128, 64, 32, 16, 8 and 1 respectively.

Comparative Table 1

According to the comparison table 1, the least significant bit of the previous thermometer code and the most significant bit of the next thermometer code coincide, and the numerical calculation module 103 performs the staggered addition according to the coincidence relation shown in the comparison table 1, so as to obtain the 12-bits output code DSC.

And according to the current digital domain weights of the first-Stage conversion module Stage12 to the seventh-Stage conversion module Stage17, digital output information DOUT corresponding to the 12bits output code can be obtained through calculation according to the following formula:

DOUT＝(d12*4+d11*2+d10*1)*512+(d22*4+d21*2+d20*1)*128+(d31*2+d30*1)*64+(d41*2+d40*1)*32+(d51*2+d50*1)*16+(d61*2+d60*1)*8+(d73*8+d72*4+d71*2+d70*1)*1。

acquiring thermometer codes (namely, second-stage thermometer codes DS12 to seventh-stage thermometer codes DS 17) respectively output by each stage of conversion module in the rear-end conversion module 102 and corresponding digital domain weights (namely, 128 to 1), so as to obtain digital residual error information reset 1:

Residue1＝(d22*4+d21*2+d20*1)*128+(d31*2+d30*1)*64+(d41*2+d40*1)*32+(d51*2+d50*1)*16+(d61*2+d60*1)*8+(d73*8+d72*4+d71*2+d70*1)*1。

according to the digital residual error information result 1, judging whether the gain of the front-end conversion module has a deviation, and when the gain has the deviation, obtaining correction information according to the residual error digital information result 1, so as to adjust the digital domain weight corresponding to the front-end conversion module 101, for example, modifying the digital domain weight of the Stage1 conversion module Stage11 into: 512+ WE1, thereby indirectly realizing the modification of the theoretical digital domain output range of the front-end conversion module, and enabling the calculated output digital information to better reflect the actual conversion capability of the 12bits pipelined analog-to-digital conversion circuit P3; wherein, WE1 is correction information, including adjusting direction and correction amount; furthermore, the adjustment direction may be characterized by a sign. Reference may be made to the description of the related embodiments above, which are not repeated herein.

Therefore, after the adjusted digital domain weight is adopted when the numerical value information DOUT is calculated, namely DOUT = (d 12 × 4 × 11 × 2+ d10 × 1) (512 + WE1) + (d 22 × 4+ d21 × 2+ d20 + 1) (d51 × 2+ d50 × 1) (d73 × 8+ 72 + 4+ d71 + 2+ d40 × 1) ((d 51 × 2+ d60) ((d 73 × 8) + 8+ 4+ d72 + d71 + d70) () 1) makes the numerical value information more accurate and reliable.

It is to be understood that the examples described hereinabove provide embodiments that are mutually combinable and cross-referenced without conflict to extend to the various possible embodiments that are all considered to be the disclosed, disclosed embodiments of the examples herein.

The embodiments of the present disclosure further provide a calibration apparatus corresponding to the calibration method described in any of the above embodiments, and the following detailed description is made by specific embodiments with reference to the accompanying drawings. It should be understood that, the following related contents of the calibration method can refer to the above embodiments, and are not repeated herein, and the contents of the calibration device described below can be referred to correspondingly with the contents of the above embodiments.

Referring to fig. 11, which is a schematic diagram illustrating a connection between an analog-to-digital conversion circuit and a calibration apparatus in an embodiment of the present disclosure, in the embodiment of the present disclosure, the analog-to-digital conversion circuit ADC1 may include: the pipelined analog-to-digital conversion circuit P4, wherein the pipelined analog-to-digital conversion circuit P4 may include a front-end conversion module 11a having at least one stage of conversion module, a back-end conversion module 11b having at least one stage of conversion module, and the digital computation module 11c.

For example, referring to fig. 11, the front-end conversion module 11a may include a first-Stage conversion module Stage21, and the back-end conversion module 11b may include Stage2 conversion modules Stage22 to nth-Stage conversion modules Stage2N. The digital calculation module 11c is adapted to calculate to obtain an output code according to the thermometer codes (i.e., the first-Stage thermometer code DS21 to the nth-Stage thermometer code DS2N in fig. 11) output by the Stage conversion modules Stage21 to Stage2N and the corresponding digital domain weight.

The calibration device 110 is connected to the input end of the pipelined analog-to-digital conversion circuit P4 and connected to the back-end conversion module 11b, and its specific structure is shown in fig. 12. With reference to fig. 11 and 12, the calibration device 110 may include:

a signal generating module 111, adapted to generate a test analog signal, and input the test analog signal into the pipelined analog-to-digital converting circuit P4, so that the front-end converting module 11a receives the test analog signal and outputs a corresponding analog residual signal to the back-end converting module 11 b;

the deviation detecting module 112 is adapted to obtain residual digital information corresponding to the analog residual signal, and determine whether the gain of the front-end converting module 11a has a deviation according to the residual digital information.

According to the scheme, the analog residual signal in the analog domain is measured and converted into the residual digital information in the digital domain for calculation, so that the gain of the front-end conversion module is verified through the residual digital information, the secondary error generated by measuring the analog residual signal can be avoided, and the calibration accuracy of the effective gain error can be improved; moreover, the calibration method provided in the embodiments of the present specification is implemented based on the existing hardware architecture of the pipelined analog-to-digital conversion circuit, and a better calibration effect can be achieved by combining the existing logic operation device, so that the hardware cost and implementation complexity required for calibration can be effectively reduced, the response speed and execution speed of calibration are improved, the calibration efficiency is higher, and the calibration method has stronger universality.

It should be noted that the analog-to-digital conversion circuit in this specification may include other types of analog-to-digital conversion circuits besides the pipeline type analog-to-digital conversion circuit, and this specification is not limited thereto.

In a specific implementation, as shown in fig. 12, the deviation detecting module 112 may include any one of the following units:

a first determining unit 1121, adapted to determine whether a measured digital domain output range corresponding to the residual digital information is consistent with a current theoretical digital domain output range of the front-end conversion module 11 a; when the front end conversion module 11a is inconsistent with the front end conversion module, judging that an error exists in the front end conversion module;

a second determining unit 1122, adapted to determine whether a measured gain corresponding to the residual digital information is consistent with a theoretical gain of the front-end converting module 11a according to a measured value of the test analog signal at the measuring time and a current theoretical digital domain output range of the front-end converting module 11 a; when the gain of the front end conversion module 11a is inconsistent with the gain of the front end conversion module, the gain of the front end conversion module 11a is judged to have an error.

The first determining unit 1121 and the second determining unit 1122 may refer to the related contents of the calibration method, and are not described herein again.

Therefore, the difference between the actual digital domain output range and the theoretical digital domain output range of the front-end conversion module can be judged by reasonably and efficiently utilizing the existing hardware architecture of the pipelined analog-to-digital conversion circuit and through the measured digital domain output range obtained by the residual digital information, or the difference between the actual gain and the theoretical gain of the front-end conversion module can be judged through the measured gain obtained by the residual digital information; therefore, the hardware cost and implementation complexity required by calibration are reduced, the response speed and execution speed of calibration are improved, the calibration efficiency is higher, and the method has stronger universality.

In a specific implementation, referring to fig. 11, the calibration apparatus 110 may further be connected to the digital calculation module 11c, and the deviation detection module 112 in the calibration apparatus 110 is further adapted to instruct the digital calculation module 11c to adjust the digital domain weight corresponding to the front-end conversion module 11a according to the residual digital information after determining that the deviation exists.

Therefore, by adjusting the digital domain weight to the size consistent with the actual gain capability of the front-end conversion module, the reliability and the accuracy of the output result of the pipelined analog-to-digital conversion circuit can be improved under the condition of not changing the existing hardware architecture of the pipelined analog-to-digital conversion circuit, and the power consumption requirement under the same accuracy is reduced.

In a specific implementation, as shown in fig. 11 and 12 in combination, the deviation detecting module 112 may further include any one of the following units:

a first modifying unit 1123, adapted to instruct the digital computing module 11c to reduce the digital domain weight corresponding to the front-end converting module 11a when the span of the current theoretical digital domain output range of the front-end converting module 11a is greater than the span of the measured digital domain output range corresponding to the residual digital information; and when the span of the current theoretical digital domain output range of the front-end conversion module 11a is smaller than the span of the measurement digital domain output range corresponding to the residual digital information, instructing the digital calculation module 11c to increase the digital domain weight corresponding to the front-end conversion module. Therefore, the theoretical digital domain output range of the front-end conversion module 11a is more close to the actual output range.

A second modifying unit 1124, adapted to instruct the digital calculating module 11c to reduce the digital domain weight corresponding to the front-end converting module 11a when the theoretical gain corresponding to the front-end converting module 11a is greater than the measured gain corresponding to the residual digital information; and when the theoretical gain corresponding to the front-end conversion module 11a is smaller than the measurement gain corresponding to the residual digital information, instructing the digital calculation module 11c to increase the digital domain weight corresponding to the front-end conversion module 11 a. Therefore, the theoretical gain corresponding to the front-end conversion module 11a is closer to the actual gain of the front-end conversion module.

In a specific implementation, as shown in fig. 11 and 12, the calibration device 110 is respectively connected to the output ends of the conversion modules at different levels in the back-end conversion module 11 b; the deviation detecting module 112 is adapted to determine the residual digital information according to the thermometer codes (i.e., the M +1 th thermometer code DS2M +1 to the nth thermometer code DS2N in fig. 11) respectively output by each stage of the converting modules in the rear-end converting module 11 b.

Specifically, referring to fig. 11 and 12 in combination, the deviation detecting module may further include:

a storage unit 1125 adapted to store thermometer codes respectively output by each stage of the conversion module in the back-end conversion module 11b and digital domain weights corresponding to each stage of the conversion module in the back-end conversion module 11 b;

and the operation unit 1126 is adapted to perform weighting calculation on the acquired thermometer codes according to the digital domain weights corresponding to the conversion modules at all levels in the rear-end conversion module 11b to obtain the residual digital information.

From the above, through the thermometer code obtained by quantization of the rear-end conversion module in the pipelined analog-to-digital conversion circuit and the set digital domain weight, the information of the residual analog signal output by the front-end conversion module in the digital domain can be reversely calculated, so that the analog residual signal output by the front-end conversion module can be indirectly read, the residual digital information can effectively replace the analog residual signal to perform gain verification of the front-end conversion module, and the hardware architecture of the existing pipelined analog-to-digital conversion circuit is reasonably utilized, thereby reducing the hardware cost and implementation complexity required by calibration, improving the response speed and execution speed of calibration, and enabling the calibration efficiency to be higher.

In a specific implementation, referring to fig. 11 and 12 in combination, the signal generating module 111 is adapted to generate a plurality of analog signals, and input each of the test analog signals into the pipeline analog-to-digital converting circuit P4, where each of the analog signals changes in a single direction and in different ways.

The deviation detecting module 112 is adapted to count residual digital information corresponding to each of the test analog signals, and determine whether a deviation exists in the gain of the front-end converting module 11 a; and after the deviation is determined, instructing the digital calculation module to adjust the digital domain weight corresponding to the front-end conversion module according to the counted residual digital information corresponding to each test analog signal.

Therefore, the probability of misjudgment and missed judgment can be reduced, the times of gain adjustment are reduced, and the calibration efficiency is improved. In a specific implementation, referring to fig. 11 and 12 in combination, the deviation detecting module 112 may further include: a third determining unit 1127 adapted to determine whether the calibration end condition is met, if so, ending the calibration, otherwise, continuing the calibration. The calibration duration can thereby be controlled.

The present specification also provides a lidar employing the analog-to-digital conversion circuit according to any of the above embodiments, which is described in detail below with reference to the accompanying drawings.

In a specific implementation, as shown in fig. 13, a structural diagram of a lidar in an embodiment of the present specification is shown. The Laser radar Laser1 may include: the detection device DE1, the analog-to-digital conversion circuit ADC1 and the calibration device 110; wherein:

the detection device DE1 is adapted to collect echo signals and output analog signals to be processed to the analog-to-digital conversion circuit ADC 1.

The analog-to-digital conversion circuit ADC1 is adapted to perform analog-to-digital conversion on the analog signal to be processed of the detection device DE1 or the test analog signal of the calibration device 110; the analog-to-digital conversion circuit ADC1 may include a pipelined analog-to-digital conversion circuit P4, where the pipelined analog-to-digital conversion circuit P4 may include a front-end conversion module 11a having at least one stage of conversion module, a back-end conversion module 11b having at least one stage of conversion module, and a digital computation module 11c; specifically, reference may be made to the above description of related contents, which are not repeated herein.

The calibration device 110 is adapted to calibrate the pipelined analog-to-digital conversion circuit P4 according to the generated test analog signal.

In specific implementation, after the calibration device completes the calibration operation on the pipelined analog-to-digital conversion circuit, the theoretical gain (or the theoretical digital domain output range) of the pipelined analog-to-digital conversion circuit is closer to the actual situation. Therefore, the analog-to-digital conversion circuit calibrated by the calibration device in the embodiment of the specification has more accurate and reliable output digital information. The detection device is started after the calibration of the calibration device is completed and is used for acquiring echo signals and outputting analog signals to be processed, and after the analog-to-digital conversion circuit completes mode conversion on the analog signals to be processed, the numerical values of the analog signals to be processed can be more accurately estimated according to the output numerical information of the streamline analog-to-digital conversion circuit in the analog-to-digital conversion circuit.

In a specific implementation, as shown in fig. 13, the Laser radar Laser1 may further include a control device CO1, adapted to control the calibration device 110 to calibrate the pipelined analog-to-digital conversion circuit P4 after the Laser radar Laser1 is powered on, and control the calibration device 110 to end calibration after a calibration end condition is met, and enable the analog-to-digital conversion circuit ADC1 to perform analog-to-digital conversion processing on an analog signal to be processed.

In a specific implementation, the detection means may comprise a photodetector. Specifically, the photodetector may include: single Photon Avalanche photodiode (SPAD) arrays, silicon photomultiplier (SiPM), and Avalanche Photodiode (APD).

In practical applications, each module and each unit included in the calibration apparatus provided in the embodiments of the present disclosure may be implemented by using corresponding hardware circuits, devices, and various hardware combinations. For example, the signal generation module may be implemented using a signal generator circuit; the first judging unit, the second judging unit, the first correcting unit, the second correcting unit and the like can be realized by processing chips such as a singlechip, a Field Programmable Gate Array (FPGA) and the like; the Memory unit may be implemented by a Random Access Memory (RAM), a register, or the like. The embodiments of the present description are not limited in this regard.

It is to be understood that the examples described hereinabove provide embodiments that are mutually combinable and cross-referenced without conflict to extend to the various possible embodiments that are all considered to be the disclosed, disclosed embodiments of the examples herein.

It is noted that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic may be included in at least one implementation of the specification. And in the description of the present specification, the terms "first", "second", and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of the feature. Moreover, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the specification described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein.

Although the embodiments of the present specification are disclosed above, the embodiments of the present specification are not limited thereto. Various changes and modifications may be effected by one skilled in the art without departing from the spirit and scope of the embodiments herein described, and it is intended that the scope of the embodiments herein described be limited only by the scope of the appended claims.

Claims (16)

1. A calibration method for an analog-to-digital conversion circuit, wherein the analog-to-digital conversion circuit comprises a pipelined analog-to-digital conversion circuit, wherein the pipelined analog-to-digital conversion circuit comprises a front-end conversion module having at least one stage of conversion module and a back-end conversion module having at least one stage of conversion module, the calibration method comprising:

inputting a test analog signal into the pipelined analog-to-digital conversion circuit so that the front-end conversion module receives the test analog signal and outputs a corresponding analog residual signal to the rear-end conversion module;

acquiring residual digital information corresponding to the analog residual signal;

and judging whether the gain of the front-end conversion module has deviation or not according to the residual digital information.

2. The calibration method for analog-to-digital conversion circuit according to claim 1, wherein said determining whether there is a deviation in the gain of the front-end conversion module according to the residual digital information comprises any one of:

judging whether the output range of the measurement digital domain corresponding to the residual digital information is consistent with the current theoretical digital domain output range of the front-end conversion module; when the gain of the front end conversion module is inconsistent with the gain of the front end conversion module, judging that an error exists in the gain of the front end conversion module;

judging whether the measurement gain corresponding to the residual digital information is consistent with the theoretical gain of the front-end conversion module or not according to the measurement value of the test analog signal at the measurement time and the current theoretical digital domain output range of the front-end conversion module; and when the gain of the front-end conversion module is inconsistent with the gain of the front-end conversion module, judging that an error exists in the gain of the front-end conversion module.

3. The calibration method for an analog-to-digital conversion circuit according to claim 1 or 2, characterized by further comprising:

and when deviation exists, adjusting the digital domain weight corresponding to the front-end conversion module according to the residual digital information.

4. The calibration method for analog-to-digital conversion circuit according to claim 3, wherein the adjusting the digital domain weight of the front-end conversion module according to the residual digital information comprises any one of:

if the span of the current theoretical digital domain output range of the front-end conversion module is larger than the span of the measurement digital domain output range corresponding to the residual digital information, reducing the digital domain weight corresponding to the front-end conversion module; if the span of the current theoretical digital domain output range of the front-end conversion module is smaller than the span of the measurement digital domain output range corresponding to the residual digital information, the digital domain weight corresponding to the front-end conversion module is increased;

if the theoretical gain corresponding to the front-end conversion module is larger than the measurement gain corresponding to the residual digital information, reducing the digital domain weight corresponding to the front-end conversion module; and if the theoretical gain corresponding to the front-end conversion module is smaller than the measurement gain corresponding to the residual digital information, the digital domain weight corresponding to the front-end conversion module is increased.

5. The calibration method for analog-to-digital conversion circuit according to claim 1 or 2, wherein said obtaining residual digital information corresponding to said analog residual signal comprises:

acquiring thermometer codes and corresponding digital domain weights respectively output by each stage of conversion modules in the rear-end conversion module;

and performing weighting calculation according to the acquired thermometer code and the corresponding digital domain weight to obtain the residual digital information.

6. The calibration method for analog-to-digital conversion circuit according to claim 1 or 2, wherein the front-end conversion module comprises a first-stage conversion module.

7. The calibration method for analog-to-digital conversion circuit according to claim 1 or 2, wherein said inputting a test analog signal into said pipeline analog-to-digital conversion circuit comprises:

acquiring a plurality of test analog signals, inputting the test analog signals into the pipelined analog-to-digital conversion circuit respectively, counting residual digital information corresponding to the test analog signals, and judging whether the gain of the front-end conversion module has deviation, wherein the test analog signals change in a single direction and in different change modes;

and when deviation exists, counting residual digital information corresponding to each test analog signal, and adjusting digital domain weight corresponding to the front-end conversion module.

8. A calibration arrangement for an analog-to-digital conversion circuit, the analog-to-digital conversion circuit comprising: the pipelined analog-to-digital conversion circuit comprises a front-end conversion module with at least one stage of conversion module, a rear-end conversion module with at least one stage of conversion module and a digital calculation module, wherein the digital calculation module is suitable for calculating to obtain output digital information according to thermometer codes and corresponding digital domain weights output by each stage of conversion module; the calibration device includes:

the signal generating module is suitable for generating a test analog signal and inputting the test analog signal into the pipelined analog-to-digital conversion circuit so that the front-end conversion module receives the test analog signal and outputs a corresponding analog residual signal to the rear-end conversion module;

and the deviation detection module is suitable for acquiring residual digital information corresponding to the analog residual signal and judging whether the gain of the front-end conversion module has deviation or not according to the residual digital information.

9. The calibration device according to claim 8, wherein the deviation detecting module comprises any one of the following units:

the first judgment unit is suitable for judging whether the output range of the measurement digital domain corresponding to the residual digital information is consistent with the current theoretical digital domain output range of the front-end conversion module; when the front end conversion module is inconsistent, judging that an error exists in the front end conversion module;

the second judging unit is suitable for judging whether the measurement gain corresponding to the residual digital information is consistent with the theoretical gain of the front-end conversion module or not according to the measurement value of the test analog signal at the measurement time and the current theoretical digital domain output range of the front-end conversion module; and when the gain of the front-end conversion module is inconsistent with the gain of the front-end conversion module, judging that an error exists in the gain of the front-end conversion module.

10. The calibration apparatus according to claim 8 or 9, wherein the deviation detecting module is further adapted to instruct the digital calculating module to adjust the digital domain weight corresponding to the front-end converting module according to the residual digital information after determining that the deviation exists.

11. The calibration device of claim 10, wherein the deviation detection module further comprises any one of the following units:

the first correcting unit is suitable for indicating the digital computing module to reduce the digital domain weight corresponding to the front-end conversion module when the span of the current theoretical digital domain output range of the front-end conversion module is larger than the span of the measurement digital domain output range corresponding to the residual digital information; when the span of the current theoretical digital domain output range of the front-end conversion module is smaller than the span of the measurement digital domain output range corresponding to the residual digital information, indicating the digital calculation module to improve the digital domain weight corresponding to the front-end conversion module;

the second correction unit is suitable for indicating the digital calculation module to reduce the digital domain weight corresponding to the front-end conversion module when the theoretical gain corresponding to the front-end conversion module is greater than the measurement gain corresponding to the residual digital information; and when the theoretical gain corresponding to the front-end conversion module is smaller than the measurement gain corresponding to the residual digital information, indicating the digital calculation module to improve the digital domain weight corresponding to the front-end conversion module.

12. The calibration device for analog-to-digital conversion circuit according to claim 8 or 9, wherein the deviation detection module further comprises:

the storage unit is suitable for storing thermometer codes respectively output by each stage of conversion module in the rear-end conversion module and digital domain weights corresponding to each stage of conversion module in the rear-end conversion module;

and the operation unit is suitable for carrying out weighting calculation on the acquired thermometer code according to the digital domain weight corresponding to each level of conversion module in the rear-end conversion module to obtain the residual digital information.

13. The calibration device according to claim 8 or 9, wherein the front-end conversion module comprises a first-stage conversion module.

14. The calibration apparatus according to claim 8 or 9, wherein the signal generating module is adapted to generate a plurality of test analog signals, and input the test analog signals into the pipelined analog-to-digital converting circuit respectively, wherein the analog signals respectively vary in a single direction and in different manners;

the deviation detection module is suitable for counting residual digital information corresponding to each test analog signal and judging whether the gain of the front-end conversion module has deviation or not; and after the deviation is determined, instructing the digital calculation module to adjust the digital domain weight corresponding to the front-end conversion module according to the counted residual digital information corresponding to each test analog signal.

15. A lidar characterized by comprising: a detection device, an analog-to-digital conversion circuit and a calibration device according to any one of claims 8 to 14; wherein:

the detection device is suitable for collecting echo signals and outputting analog signals to be processed to the analog-to-digital conversion circuit;

the analog-to-digital conversion circuit is suitable for performing analog-to-digital conversion on the analog signal to be processed of the detection device or the test analog signal of the calibration device; the device comprises a pipelined analog-to-digital conversion circuit, wherein the pipelined analog-to-digital conversion circuit comprises a front-end conversion module with at least one stage of conversion module, a rear-end conversion module with at least one stage of conversion module and a digital calculation module;

the calibration device is suitable for calibrating the pipelined analog-to-digital conversion circuit according to the generated test analog signal.

16. The lidar of claim 15, further comprising:

and the control device is suitable for controlling the calibration device to calibrate the pipelined analog-to-digital conversion circuit after the radar is powered on, controlling the calibration device to finish calibration after the calibration finishing condition is met, and enabling the analog-to-digital conversion circuit to perform analog-to-digital conversion processing on the analog signal to be processed.

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