CN115270699A - CPU chip simulation acceleration method for generating executable file to perform simulation slice recovery - Google Patents
CPU chip simulation acceleration method for generating executable file to perform simulation slice recovery Download PDFInfo
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Abstract
A CPU chip simulation acceleration method for generating an executable file to perform simulation slice recovery comprises the following steps: s1: a behavior simulation model and SimPoint are combined to pick a basic block vector of a part with higher weight in a specified program to generate a feature slice, wherein the behavior simulation model is gem5; s2: modifying the behavior simulation model, operating the behavior simulation model again by using the developed instruction and an instruction context tracking function, and starting to track the execution of the feature slice at the starting execution stage of the feature slice until the execution of the feature slice is finished; s3: after the characteristic slice is executed, the instruction context tracking function generates a section of slice assembly code according to the tracking result to obtain a designated program slice; s4: and executing the obtained specified program slice by using the executable test firmware on the target test system.
Description
Technical Field
The invention relates to the technical field of CPU chip simulation, in particular to a CPU chip simulation acceleration method for generating an executable file to perform simulation slice recovery, and more particularly to a CPU chip simulation acceleration method for realizing simulation slice recovery by generating an executable file.
Background
Slice emulation is a commonly used means for verifying a CPU chip, and if the CPU chip can execute a slice without error, the generated instruction log should be consistent with the instruction log of the generated slice executed on the simulator, and thus, the slice emulation can be used to verify the correctness of the CPU. In the verification process of the CPU chip, a large number of programs need to be executed to verify the stability of the CPU chip, so that the chip simulation execution is a very time-consuming process.
The emulation slice is typically an execution context that generates a slice program, which includes memory, disks, registers, cached snapshots, etc., and is restored into the emulation model. When the real CPU chip hardware is not modeled, especially when the out-of-order execution CPU model is missing, the snapshot generated by different simulation models cannot be restored to the real hardware model.
Several common slicing methods are commonly used in the art, as listed in table 1, and the relationship between the slice simulation application scenario and the hardware CPU model for each method is compared as follows:
table 1:
therefore, a method for generating slices in a general simulator environment and quickly executing the sliced programs in a real hardware environment is needed to achieve the purposes of shortening the simulation time and not consuming a large amount of work.
Disclosure of Invention
In order to solve the above problems, the present invention provides a CPU chip simulation acceleration method for generating an executable file for simulation slice recovery, which only requires a software team to generate slices from a common simulator and execute the slices on real hardware, and can perform a verification effect of executing a program by executing a program feature part, thereby shortening simulation time and workload for executing a large number of programs.
In order to achieve the above object, the present invention provides a CPU chip simulation acceleration method for generating an executable file for simulation slice recovery, which includes:
step S1: a behavior simulation model and SimPoint are combined to pick a basic block vector of a part with higher weight in a specified program to generate a feature slice, wherein the behavior simulation model is gem5;
step S2: modifying the behavior simulation model, operating the behavior simulation model again by using the developed instruction and an instruction context tracking function, and starting to track the execution of the feature slice at the starting execution stage of the feature slice until the execution of the feature slice is finished;
and step S3: after the characteristic slice is executed, the instruction context tracking function generates a section of slice assembly code according to the tracking result to obtain a designated program slice;
and step S4: and executing the obtained designated program slice by using the executable test firmware on the target test system.
In an embodiment of the present invention, step S1 specifically includes:
step S1.1: introducing SimPoint slicing function while running the behavior simulation model gem5, analyzing and extracting program basic block vectors with highest weight, and generating basic block vector side-writing files which can be used by SimPoint and are used for analyzing weight;
step S1.2: operating SimPoint to analyze a basic block vector side-writing file and outputting a SimPoint weight analysis result file;
step S1.3: and executing the behavior simulation model gem5 again, reading in the basic block vector with higher weight of the specified basic block vector side writing file in the SimPoint weight result file, and generating checkpoint snapshots which can be repeatedly executed by the simulator to obtain the feature slice.
In an embodiment of the present invention, the instruction and instruction context tracking function in step S2 is a plug-in of a gem5 simulator, and when the instruction of the designated program is executed by the CPU of the gem5 simulator each time, the plug-in is called, and at this time, the executed instruction code and the state of the memory and register in the simulator at that time are recorded.
In an embodiment of the present invention, the tracking function in step S2 includes automatic tracking of a CPU register, a code, and data, where the data further includes a data segment, a stack, and a heap, and specifically includes:
tracking the CPU register only when the characteristic slice starts to execute, and recording the information of all context registers;
the tracking of the stack is that when the characteristic slice starts to execute, stack information at the beginning of the slice is recorded through a stack pointer;
the tracking of the stack also comprises recording the frame information of the characteristic slice in the execution process of the characteristic slice;
the tracking of the data segment and the heap is to record the content which is read for the first time and is recorded into the memory address in the executing process of the characteristic slice;
the tracking of the data segment and the heap further comprises merging the contents in the memory address read for the first time after the characteristic slice is executed, and forming a discrete list of the memory information accessed in the executing process; and
the tracking of the code is to record executed function symbolic information through a tracking jump/call instruction in the execution process of the feature slice, wherein the function symbolic information comprises a symbolic name and a first address of a target function.
In an embodiment of the present invention, the content of the slice assembly code in step S3 includes:
the first section is a process of loading an instruction for a section of register to recover a context register of the CPU;
the second section is a section of memory read and written by the slicing program, which comprises a heap or data section, so as to establish the process of virtual memory mapping;
the third section is a process of loading a command to a memory so as to recover the address content of the target memory;
the fourth section is a code section which outputs all the recorded function symbol information in a mode of assembly function, wherein the symbols in the function symbol information are represented by symbol names and not represented by addresses;
the fifth section is a code section which outputs the function called by the recorded function by means of assembly function, in which the symbol of the function is also represented by symbol name and not by address; and
the sixth section is a section of stack recovery code, specifically, the stack pointer is modified according to the stack and frame information to obtain the space of the stack and the frame, and the stored frame content is stored in the space of the stack and the frame.
In an embodiment of the present invention, step S4 specifically includes:
step S4.1: adding the support of a memory management unit for the test firmware so that the test firmware has an address space environment similar to that of an operating system when executing a specified program slice;
step S4.2: linking the generated slice assembly code with the test firmware which can be started by the target test system in the form of a slice entry function into an executable file, wherein the linking process is a process of re-linking the symbols into new addresses;
step S4.3: the CPU of the target test system directly executes the executable file, wherein the BSP portion of the target test system test firmware itself is run first, then jumps to the slice assembly code entry, and the entire execution process of the specified program slice can be reproduced by calling the slice entry function.
Compared with the prior art, the CPU chip simulation accelerating method for generating the executable file to recover the simulation slice can be executed on real hardware only by generating the slice by a common simulator without spending huge workload of hardware modeling, and for the execution program, the verification effect of executing the program can be achieved only by executing the characteristic part of the program, so that the simulation time consumed by executing a large number of programs is shortened.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of a cutting basic block;
FIG. 2 is a flow chart of an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art based on the embodiments of the present invention without inventive step, are within the scope of the present invention.
Fig. 1 is a schematic diagram of a principle of cutting a basic block, and as shown in fig. 1, a slice simulation method adopted by the present invention is based on a SimPoint tool to achieve the purpose of shortening simulation execution time, and the principle is as follows: a specific program to be simulated (e.g. a test case in a SPEC CPU (CPU subsystem evaluation software developed by SPEC organization)) may need to run for a very long time to obtain a simulation result, and thus cannot be executed and completed on a hardware simulator. SimPoint is a tool that analyzes program execution by cutting an application code into Basic Block vectors (Basic Block Vector) at intervals of millions of instructions (more or less instructions are also possible), dividing a program instruction stream into Basic blocks (Basic blocks) by taking branch and jump instructions as boundaries (see FIG. 1), wherein the millions of instructions comprise a certain number of Basic blocks (A, B, C, D, E, F, and the like), and analyzing the weight of each Basic Block Vector in the whole execution process, wherein the Basic Block array formed by the Basic blocks is called Basic Block Vector (BBV).
In the actual simulation process, in order to shorten the simulation time, it is usually necessary to extract part of basic block vectors from the specified program, and the execution of the whole program can be represented by executing only the part of basic block vectors, where the part of basic block vectors are basically higher in weight, and are defined as feature slice information of the specified program in the embodiment of the present invention.
Fig. 2 is a flowchart of an embodiment of the present invention, and as shown in fig. 2, the embodiment provides a CPU chip simulation acceleration method for generating an executable file to perform simulation slice recovery, which includes:
step S1: a behavior simulation model and SimPoint are combined to pick a basic block vector of a part with higher weight in a specified program to generate a feature slice, wherein the behavior simulation model is gem5;
gem5 is a modularized discrete event-driven full-system simulator, which is a highly configurable architecture simulator integrating various ISAs and various CPU models, gem5 can support relatively complex out-of-order CPU models, the generated slices have high quality, and the realization of real CPUs can be verified.
In this embodiment, step S1 specifically includes:
step S1.1: introducing SimPoint slicing function while running the behavior simulation model gem5, analyzing and extracting program Basic Block vectors with highest weight, and generating Basic Block Vector (BBV) side write files (Basic Block Vector profiles) which can be used by SimPoint and are used for analyzing weight;
step S1.2: operating an SimPoint analysis Basic Block Vector (BBV) side write file, and outputting an SimPoint weight analysis result file; for example, the main loop of the benchmark program, due to its periodically repeated execution, will be calculated and analyzed by SimPoint as the BBV with higher weight, and will be marked as high weight in the weight analysis result file output by SimPoint.
Step S1.3: and executing the behavior simulation model gem5 again, reading in a Basic Block Vector (BBV) with higher weight of a specified Basic Block Vector (BBV) side write file in the SimPoint weight result file, and generating a checkpoint snapshot which can be repeatedly executed by the simulator to obtain a feature slice. Since checkpoint of gem5 contains the state of the emulator, the emulator can resume execution from the snapshot to complete execution at the end of the snapshot.
Step S2: modifying the behavior simulation model, operating the behavior simulation model again by using the developed instruction and an instruction context tracking function, and starting to track the execution of the feature slice at the starting execution stage of the feature slice until the execution of the feature slice is finished;
in this embodiment, the instruction and instruction context tracking function in step S2 is a plug-in of a gem5 simulator, and when the instruction of the designated program is executed by the CPU of the gem5 simulator each time, the plug-in is called, and at this time, the executed instruction code and the state of the memory and register in the simulator at that time are recorded. Since a program contains a plurality of instructions, the simulator needs one instruction to execute the instructions, so that what instructions are executed by the CPU of the simulator and the content of the registers and the memory (i.e. the context during execution) at the time can be intercepted in the instruction submission stage of the simulator.
In this embodiment, the tracking function in step S2 includes automatic tracking of a register, a code, and data of the CPU, where the data further includes a data segment, a stack, and a heap, and specifically includes:
s2.1: tracking the CPU register only when the characteristic slice starts to execute, and recording the information of all context registers;
s2.2: tracking the stack, namely recording stack information at the beginning of the slice through a Stack Pointer (SP) when the feature slice is started to execute;
s2.3: tracking the stack further includes recording Frame (FP) information of the feature slice during execution thereof;
s2.4: the tracking of the data segment and the heap is to record the content which is read for the first time and is recorded into the memory address in the executing process of the characteristic slice;
s2.5: the tracking of the data segment and the heap further comprises merging the contents in the memory address read for the first time after the characteristic slice is executed, and forming a discrete list of the memory information accessed in the execution process; and
s2.6: the tracking of the code is to record executed function symbol (PC) information including a symbol name and a first address of a target function through a tracking jump/call instruction in the execution process of the feature slice.
And step S3: after the characteristic slice is executed, the instruction context tracking function generates a section of slice assembly code according to a tracking result to obtain a designated program slice;
in this embodiment, the content of the slice assembly code in step S3 includes:
s3.1: the first section is a process of loading an instruction for a section of register to recover a context register of the CPU;
s3.2: the second section is a section of memory read and written by the slicing program, which comprises a heap or data section, so as to establish the process of virtual memory mapping;
s3.3: the third section is a process of loading a command to a memory so as to recover the address content of the target memory;
s3.4: the fourth section is a code section which outputs all the recorded function symbol information in a mode of assembly function, wherein the symbols in the function symbol information are represented by symbol names and not represented by addresses;
s3.5: the fifth section is a code section which outputs the function called by the recorded function by means of assembly function, in which the symbol of the function is also represented by symbol name and not by address; this implementation adds this S3.5 to solve this problem, since the call path taken by the traced function may not include all the functions called by the function, and thus may cause a link failure.
S3.6: the sixth section is a section of stack recovery code, specifically, the stack and frame space is obtained by modifying the Stack Pointer (SP) according to the stack and frame information, and the stored frame content is stored in the stack and frame space.
And step S4: and executing the obtained specified program slice by using the executable test firmware on the target test system.
The target test system in step S4 may be an ARM64 or RISCV system, and since the test firmware is usually developed before the slicing function is implemented, the implementation of the virtual memory is added in this embodiment to recover the saved memory.
In this embodiment, step S4 specifically includes:
step S4.1: adding the support of a Memory Management Unit (MMU) to the test firmware so that the test firmware has an address space environment similar to that of the operating system when executing the specified program slice; the similar address space environment described here is that the MMU function is used to map the physical address of the real chip into a virtual address space, and the address range of the virtual address space is equivalent to the original address space of the program to be sliced, so that the instruction/data address of the program to be sliced can be kept unchanged.
Step S4.2: linking the generated slice assembly code with the test firmware which can be started by the target test system in the form of a slice entry function to form an executable file, wherein the linking process is actually a process of re-linking the symbols into new addresses; because the function and the called function are both output to the code segment, and the global memory access shows that the memory read-write instruction is irrelevant to the variable, the function and the called function can be linked into an executable file without errors, the symbol can be re-linked into a new address in the linking process, and the address of the function symbol (PC) is not concerned because the linking step exists in the whole slice recovery process;
step S4.3: the CPU of the target test system directly executes and runs the executable file, wherein the target test system is run first to test the BSP (generally referred to as board level support package) part of the firmware itself, then jumps to the slice assembly code entry, and the whole execution process of the specified program slice can be reproduced by calling the slice entry function. Note that the entire slice restore process since the stack restore step exists, the entire execution of the slice can be rendered by calling the slice entry function without concern for the Stack Pointer (SP) address.
Compared with the prior art, the CPU chip simulation accelerating method for generating the executable file to carry out simulation slice recovery does not need to spend huge workload of hardware modeling, can be executed on real hardware only by generating the slice by a common simulator, and can play a verification effect of executing the program only by executing the characteristic part of the program, thereby shortening simulation time consumed by executing a large number of programs.
Those of ordinary skill in the art will understand that: the figures are merely schematic representations of one embodiment, and the blocks or flow diagrams in the figures are not necessarily required to practice the present invention.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, and not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (6)
1. A CPU chip simulation acceleration method for generating an executable file to perform simulation slice recovery is characterized by comprising the following steps:
step S1: a behavior simulation model and SimPoint are combined to pick a basic block vector of a part with higher weight in a designated program to generate a feature slice, wherein the behavior simulation model is gem5;
step S2: modifying the behavior simulation model, operating the behavior simulation model again by using the developed instruction and an instruction context tracking function, and starting to track the execution of the feature slice at the starting execution stage of the feature slice until the execution of the feature slice is finished;
and step S3: after the characteristic slice is executed, the instruction context tracking function generates a section of slice assembly code according to the tracking result to obtain a designated program slice;
and step S4: and executing the obtained designated program slice by using the executable test firmware on the target test system.
2. The CPU chip simulation acceleration method for generating an executable file for simulation slice recovery according to claim 1, wherein step S1 specifically includes:
step S1.1: introducing SimPoint slice function while operating the behavior simulation model gem5, analyzing and extracting program basic block vectors with the highest weight, and generating basic block vector side-writing files which can be used by SimPoint and are used for analyzing the weight;
step S1.2: running an SimPoint analysis basic block vector side-writing file, and outputting an SimPoint weight analysis result file;
step S1.3: and executing the behavior simulation model gem5 again, reading in the basic block vector with higher weight of the specified basic block vector side writing file in the SimPoint weight result file, and generating a checkpoint snapshot which can be repeatedly executed by the simulator to obtain the feature slice.
3. The method of claim 1, wherein the instruction and instruction context tracking function in step S2 is a plug-in of a gem5 simulator, and the plug-in is called each time the instruction of the designated program is executed by the CPU of the gem5 simulator, and the executed instruction code and the state of the memory and register in the simulator at that time are recorded.
4. The method for accelerating simulation of a CPU chip for generating an executable file and recovering a simulation slice according to claim 1, wherein the tracking function in step S2 includes automatic tracking of CPU registers, codes and data, wherein the data further includes a data segment, a stack and a heap, and specifically includes:
tracking the CPU register only when the characteristic slice starts to execute, and recording the information of all context registers;
the tracking of the stack is that when the characteristic slice starts to execute, stack information at the beginning of the slice is recorded through a stack pointer;
the tracking of the stack also comprises recording the frame information of the characteristic slice in the execution process of the characteristic slice;
the tracking of the data segment and the heap is to record the content which is read for the first time and is recorded into the memory address in the executing process of the characteristic slice;
the tracking of the data segment and the heap further comprises merging the contents in the memory address read for the first time after the characteristic slice is executed, and forming a discrete list of the memory information accessed in the execution process; and
the tracking of the code is to record executed function symbolic information through a tracking jump/call instruction in the execution process of the feature slice, wherein the function symbolic information comprises a symbolic name and a first address of a target function.
5. The method of claim 4, wherein the contents of the slice assembly code in step S3 comprises:
the first section is a process of loading an instruction for a section of register to recover a context register of the CPU;
the second section is a section of memory read and written by the slicing program, which comprises a heap or data section, so as to establish the process of virtual memory mapping;
the third section is a process of loading a command to a memory so as to recover the address content of the target memory;
the fourth section is a code section which outputs all the recorded function symbol information in a mode of assembly function, wherein the symbols in the function symbol information are represented by symbol names and not represented by addresses;
the fifth section is a code section which outputs the function called by the recorded function in a mode of assembling the function, wherein the symbol of the function is also represented by a symbol name and is not represented by an address; and
the sixth section is a section of stack recovery code, specifically, the stack pointer is modified according to the stack and frame information to obtain the space of the stack and the frame, and the stored frame content is stored in the space of the stack and the frame.
6. The CPU chip simulation acceleration method for generating an executable file for simulation slice recovery according to claim 5, wherein step S4 specifically includes:
step S4.1: adding the support of a memory management unit for the test firmware so that the test firmware has an address space environment similar to that of an operating system when executing a specified program slice;
step S4.2: linking the generated slice assembly code with the test firmware which can be started by the target test system in the form of a slice entry function into an executable file, wherein the linking process is a process of re-linking the symbols into new addresses;
step S4.3: the CPU of the target test system directly executes the executable file, wherein the BSP portion of the target test system test firmware itself is run first, then jumps to the slice assembly code entry, and the entire execution process of the specified program slice can be reproduced by calling the slice entry function.
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