CN115267300A - High-precision current acquisition circuit and electronic equipment - Google Patents
High-precision current acquisition circuit and electronic equipment Download PDFInfo
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Abstract
The invention provides a high-precision current acquisition circuit, which comprises: the device comprises a control module, a first acquisition module, a second acquisition module and an operational amplifier module; the first acquisition module and the second acquisition module form a mirror image acquisition current structure; the second acquisition module comprises a second power tube; the first acquisition module comprises N first power tubes, and the N first power tubes are different in size, so that the proportion K value of the size of each first power tube to the size of the second power tube is different; wherein N is a positive integer and is more than or equal to 2; the control module is used for selecting any one of the N first power tubes as a selection power tube; and the working states of the second power tube and the selected power tube are controlled; the control module adjusts the K value by switching different first power tubes as the selective power tube so as to weaken acquisition errors caused by the input offset voltage of the operational amplifier and improve acquisition precision.
Description
Technical Field
The invention relates to the field of circuits, in particular to a high-precision current acquisition circuit and electronic equipment.
Background
The current collection technology is used for collecting current information on a target device in a manner of adopting a proportional mirror tube so as to be used for subsequent signal processing; in order to accurately acquire a current signal on a target device, an operational amplifier and mirror image acquisition structure is generally adopted, and the virtual short characteristic of the operational amplifier is utilized to enable the three-terminal voltages of a mirror image acquisition tube and the target device to be the same.
However, since the offset voltage of the operational amplifier is fixed, an error of the input offset voltage of the operational amplifier always exists between the voltages va and vb on the mirror image acquisition tube, and meanwhile, the value of the proportion K is fixed, generally, the fixed value of K is larger, if the mirror image current is reduced according to the same proportion when a smaller current is acquired, the Vos of the operational amplifier occupies a large proportion in the acquired current under the same input offset voltage Vos, and finally, the accuracy of the acquired current is deteriorated.
In the prior art, the method for improving the current acquisition precision is to improve the precision of an operational amplifier for stabilizing voltage to enable va and vb values to be as the same as possible, or to reduce Vos of the operational amplifier as much as possible, but the method for improving the precision is difficult to realize under the condition of acquiring small current and has higher cost; the requirement on the precision of the operational amplifier is high, the design of the operational amplifier becomes extremely complex in the aspect of reducing Vos, and once the design of the operational amplifier becomes complex, the stability and the reliability of the system are reduced;
disclosure of Invention
The invention provides a high-precision current acquisition circuit and electronic equipment, aiming at solving the problem that the current acquisition precision is difficult to improve under the condition of smaller current; meanwhile, the current with wide range change can be accurately collected.
According to a first aspect of the present invention, there is provided a high-precision current collecting circuit and an electronic apparatus, the high-precision current collecting circuit including: the device comprises a control module, a first acquisition module, a second acquisition module and an operational amplifier module; the high-precision current acquisition circuit is used for acquiring current information flowing through the first acquisition module; the first acquisition module and the second acquisition module form a mirror image acquisition current structure; the second acquisition module comprises a second power tube; the first acquisition module comprises N first power tubes, and the N first power tubes are different in size, so that the proportion of the size of each first power tube to the size of the second power tube is different; wherein N is a positive integer and is more than or equal to 2;
the output end of the control module is connected with the first input end of the first acquisition module, the second input end of the control module is connected with the second input end of the first acquisition module and the input end of the second acquisition module, the output end of the first acquisition module is connected with the first input end of the operational amplifier module, and the output end of the second acquisition module is connected with the second input end of the operational amplifier module;
the control module is used for selecting a plurality of first power tubes in the N first power tubes as selection power tubes; and the working states of the second power tube and the selected power tube are controlled;
wherein, the first current reference information I flowing through the first acquisition module 1 And the first current reference information I flowing through the second acquisition module 2 Satisfies the following conditions:
I 2 ＝I 1 k is; k is the size ratio of the selected power tube to the second power tube;
an input offset voltage exists between the voltages of the first input end and the second input end of the operational amplifier module, and the control module adjusts the K value by switching different first power tubes to serve as the selective power tubes, so that the acquisition error caused by the input offset voltage is weakened, and the acquisition precision is improved.
Optionally, the reference information of the second current flowing through the second acquisition module satisfies the following condition:
I 3 ＝I 2 +V os /R 2 ；
wherein, V os For inputting offset voltage, R 2 Is the internal resistance of the second acquisition module.
Optionally, the N first power tubes are sequentially arranged in sequence, and the size of the first power tube ordered as the ith meets the following requirements: s. the i ＝X i Wherein S is i Is the size of the ith first power tube, X is a natural number and is more than or equal to 2, i is more than or equal to 1 and is less than or equal to N.
Optionally, the control module includes: the control system comprises a first control unit and a second control unit, wherein the first control unit comprises a first control signal input end, and the second control unit comprises a second control signal input end;
the output end of the first control unit is connected with the input end of the second control unit;
the first control unit is used for selecting a plurality of first power tubes in the N first power tubes as selection power tubes;
the second control unit is used for controlling the working states of the second power tube and the selected power tube.
Optionally, the first acquisition module includes: the MOS transistor comprises a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor and a seventh MOS transistor;
the source electrodes and the drain electrodes of the first MOS transistor to the seventh MOS transistor are respectively connected to the source electrode and the drain electrode of the second power transistor, the grid electrodes of the first MOS transistor to the seventh MOS transistor are connected to the output end of the control module, and the grid electrode of the second power transistor is connected to the second control signal input end.
Optionally, the first control unit includes an encoder, and the second control unit includes a switch circuit;
the control module is configured to:
the encoder generates the first control signal through different permutation and combination and sends the first control signal to the switch circuit so as to select a plurality of first power tubes in the N first power tubes as selection power tubes;
the switch circuit receives the first control signal and the second input control signal to control the working state of the selective power tube and drive the second power tube.
Optionally, the switch circuit includes first to seventh switches;
the control module is further configured to:
the first switch to the seventh switch respectively control the working state of any one of the first MOS transistor to the seventh MOS transistor.
Optionally, the control module is further configured to:
and obtaining a k value based on the ratio of the size of the selected power tube in the first acquisition module to the size of the second power tube.
Optionally, the first acquisition module is configured to:
acquiring first current reference information I flowing through the first acquisition module 1 ；
Based on I 1 And k, determining the reference information I of the first current flowing through the second acquisition module 2 ；
Reference information I of first current flowing through the second acquisition module 2 ＝I 1 And/k is transmitted to the second acquisition module and the operational amplifier module.
Optionally, the second acquisition module is configured to:
acquiring first current reference information I flowing through the second acquisition module 2 ＝I 1 /k；
Based on first current reference information I flowing through the second acquisition module 2 、V os And R 2 Determining second current reference information I flowing through the second acquisition module 3 ＝I 2 +V os /R 2 。
Optionally, the first acquisition module further includes a zeroth MOS transistor, a source and a drain of the zeroth MOS transistor are connected to the second power transistor in parallel, and a gate of the zeroth MOS transistor is connected to the second control signal input end of the control module;
the control module is further configured to:
and obtaining the minimum value of k based on the ratio of the size of the zeroth MOS tube to the size of the second power tube, wherein the minimum value of k is represented as a value meeting the minimum current acquisition precision.
Optionally, the types of the first power tube and the second power tube are the same.
According to a second aspect of the present invention, there is provided an electronic device comprising the high-precision current acquisition circuit of the first aspect and optionally thereof.
According to the high-precision current acquisition circuit and the electronic device, the control module is used for selecting a plurality of first power tubes in the N first power tubes as the selected power tubes and controlling the selected power tubes, so that the size ratio of the selected power tubes to the second power tubes is k, the K value is different due to different sizes of the N first power tubes, and the control module can adjust the K value by controlling the working states of the different first power tubes, so that the acquisition error caused by the input offset voltage is reduced, and the acquisition precision is improved.
Furthermore, the present invention does not pass the reduction of V os The acquisition precision is improved, so that the operational amplifier module is not changed, and the reduction of V is avoided os Which complicates the design of the op-amp.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a first schematic diagram of a prior art current collection circuit according to an embodiment of the present invention;
FIG. 2 is a second schematic diagram of a prior art current collection circuit according to an embodiment of the present invention;
FIG. 3 is a first schematic diagram of the high-precision current collection circuit according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of the high-precision current collection circuit according to an embodiment of the present invention.
Description of reference numerals:
1-a control module;
101-a first control unit;
102-a second control unit;
2-a first acquisition module;
200-a zeroth MOS transistor;
201-a first MOS tube;
202-a second MOS tube;
203-a third MOS tube;
204-a fourth MOS tube;
205-fifth MOS transistor;
206-sixth MOS transistor;
207-seventh MOS transistor;
3-a second acquisition module;
301-a second power tube;
4-operational amplifier module.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The technical means of the present invention will be described in detail with reference to specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
Before the present application is provided, the applicant has made a sufficient study on a current collecting circuit, and based on the study, a current collecting circuit in the prior art shown in fig. 1 is provided, and for the current collecting circuit shown in fig. 1, the following problems exist:
because the offset voltage of the operational amplifier is fixed, the input offset voltage V of the operational amplifier always exists between Va and Vb OS The error of (2). In addition, since the value of the ratio K is fixed, the fixed value of K is usually larger, and when a smaller current is collected, if the mirror current is reduced according to the same ratio, the operational amplifier Vos will occupy a large proportion in the collected current under the same input offset voltage Vos, which finally results in the accuracy of the collected current being deteriorated.
Input offset voltage V related to operational amplifier OS In particular, referring to FIG. 1, M 2 For collecting image tubes, the internal resistance is R 2 ，M 0 The target tube for collecting current has internal resistance R 0 The internal resistance of the MOS tube is calculated by the formula
Specifically, V in an ideal state a ＝V b In practice V a -V b ＝V OS I.e. transport of the amplifierGo into offset voltage V OS According to the internal resistance formula of the MOS tube, the following steps are obtained: k = R 2 /R 0 ＝(W/L) 0 /(W/L) 2 It can be seen that the K value depends on the size ratio of the power tubes.
According to V a -V b ＝V OS ，I 0 ＝(Vin-V b )/R 0 ，I 2 ＝(Vin-V a )/R 2 The following can be obtained:
I 2 ＝[Vin-(V b -V OS )]/R 2
＝[(Vin-V b )+V OS ]/R 2
＝(I 0 R 0 /R 2 )+(V OS /R 2 )
＝I 0 /K+V OS /R 2 ；
according to the above formula, the current I is collected 0 If the value of K is larger, the input offset voltage V of the operational amplifier is smaller OS Induced error versus the collected current I 2 The larger the influence, which in turn leads to a deterioration of the acquisition accuracy.
In one example, if K =1000,i 0 1A, then I 2 ＝1mA+V OS /R 2 (ii) a If K =100,i 0 1A, then I 2 ＝10mA+V OS /R 2 ；
When the value of K is small, V OS /R 2 At the collecting current value I 2 The smaller the ratio of (a) to (b), the smaller the influence on the acquisition accuracy.
Therefore, when small current is collected, if the K value is still kept to be a large value, the collection precision is very low, so that the error caused by Vos occupies a dominant position; and the K value is reduced, so that the error caused by Vos can be weakened, and the acquisition precision is improved.
Referring to fig. 2, the current collecting circuit shown in fig. 2 mainly converts the current on Q1 into a voltage V + by using R1, and then obtains a voltage VOUT including current information through an operational amplifier, and finally, the voltage VOUT is used as a subsequent signal source for processing.
For the current collection circuit in the prior art shown in fig. 2, the following problems exist:
1. under the condition of larger output current, the power consumption of the acquisition circuit is larger;
2. the acquisition precision is mainly determined by an internal acquisition resistor, and the resistance value of the resistor is greatly influenced by the process and is not suitable for chip internal integration.
3. The accuracy requirements for the op-amp are higher than those for the op-amp used in fig. 1.
In view of this, the present invention provides a new current collecting circuit, which can achieve the above effects without making a high requirement on the precision of the operational amplifier.
The scheme of the invention is specifically explained as follows:
referring to fig. 3, the present invention provides a high-precision current collecting circuit, which includes: the system comprises a control module 1, a first acquisition module 2, a second acquisition module 3 and an operational amplifier module 4; the high-precision current acquisition circuit is used for acquiring current information flowing through the first acquisition module 2; the first acquisition module 2 and the second acquisition module 3 form a mirror image acquisition current structure; the second acquisition module 3 comprises a second power tube 301; the first acquisition module 2 comprises N first power tubes, and the sizes of the N first power tubes are different, so that the ratio of the size of each first power tube to the size of the second power tube 301 is different; wherein N is a positive integer and is more than or equal to 2.
The output end of the control module 1 is connected with the first input end of the first acquisition module 2, the second input end of the control module 1 is connected with the second input end of the first acquisition module 2 and the input end of the second acquisition module 3, the output end of the first acquisition module 2 is connected with the first input end of the operational amplifier module 4, and the output end of the second acquisition module 3 is connected with the second input end of the operational amplifier module 4.
The control module 1 is configured to select a plurality of first power transistors of the N first power transistors as selected power transistors; and is used for controlling the working states of the second power tube 301 and the selected power tube;
whereinFirst current reference information I flowing through the first acquisition module 2 1 And the first current reference information I flowing through the second acquisition module 3 2 Satisfies the following conditions:
I 2 ＝I 1 k is; k is the size ratio of the selected power tube to the second power tube;
an input offset voltage exists between the voltages of the first input end and the second input end of the operational amplifier module 4, and the control module 1 adjusts the value K by switching different first power tubes to serve as the selective power tube, so that the acquisition error caused by the input offset voltage is weakened, and the acquisition precision is improved.
Wherein, the reference information of the second current flowing through the second collecting module 3 satisfies: i is 3 ＝I 2 +V os /R 2 ；V os For inputting offset voltage, R 2 Is the internal resistance of the second acquisition module 3.
In a specific embodiment, the second current reference information I flowing through the second collecting module 3 3 And the first current reference information I flowing through the second acquisition module 3 2 For the same current reference information, in particular, I 2 Is a signal in an ideal state and is not subjected to offset voltage V of an operational amplifier os Of (a) and I 3 Receiving offset voltage V of operational amplifier os Is the second current reference information in the actual situation.
In a preferred embodiment, the current collected by the first collecting module 2 is a collected current value in an ideal state, and the current collected by the second collecting module 3 is a collected current value in an actual state.
In other preferred embodiments, the first power tube and the second power tube 301 are of the same type.
Regarding the operational amplifier module 4, in an example, the operational amplifier module 4 adopts a five-tube operational amplifier.
Of course, the invention is not limited thereto, and other types of operational amplifiers are within the scope of the invention.
In the scheme, the operational amplifier V os Under the condition of no change, theBy changing the value of K and thus reducing V os The ratio of the current to the current is acquired, so that the current acquisition precision is improved.
Regarding the first collecting module 2, in a preferred embodiment, the N first power transistors are sequentially arranged in order, and the size of the first power transistor that is ordered as the ith power transistor satisfies: s i ＝X i Wherein S is i Is the size of the ith first power tube, X is a natural number and is more than or equal to 2, i is more than or equal to 1 and less than or equal to N.
In one example, the first and second acquisition modules 2 and 3 are PMOS devices, wherein the PMOS size array design of the first acquisition module 2 is, for example, 2 N N =8 design, others such as 3 N 、4 N And so on, and will not be described herein.
In a specific embodiment, referring to fig. 4, the first collecting module 2 includes: a first MOS transistor 201, a second MOS transistor 202, a third MOS transistor 203, a fourth MOS transistor 204, a fifth MOS transistor 205, a sixth MOS transistor 206, and a seventh MOS transistor 207;
the source and drain of the first MOS transistor 201 to the seventh MOS transistor 207 are respectively connected to the source and drain of the second power transistor 301, and the gates of the first MOS transistor 201 to the seventh MOS transistor 207 are all connected to the output end of the control module 1;
the gate of the second power transistor 301 is connected to the second control signal input terminal.
In other embodiments, the first acquisition module 2 is configured to:
collecting first current reference information I flowing through the first collection module 1 ；
Based on I 1 And k, determining the reference information I of the first current flowing through the second acquisition module 2 ；
Reference information I of first current flowing through the second acquisition module 2 ＝I 1 And/k is transmitted to the second acquisition module 3 and the operational amplifier module 4.
Regarding the selection of the type of the power tube, in other specific examples, the first collection module 2 and the second collection module 3 use an NMOS as the power tube, and the difference between the NMOS and the PMOS as the power tube is that: driving the grid voltage of the NMOS power tube; the NMOS transistor needs to raise the gate voltage through a charge pump or other boosting circuits to ensure the conduction of the power transistor, i.e., a GC (i.e., a second control signal input end) for controlling the gate signal of the power transistor needs a redundant boosting circuit compared to the PMOS transistor as the power transistor; wherein the GC is characterized as a master line signal.
Regarding the first acquisition module, in other preferred embodiments, the first acquisition module 2 further includes a zeroth MOS transistor 200, a source and a drain of the zeroth MOS transistor 200 are connected to the second power transistor 301 in parallel, and a gate of the zeroth MOS transistor 200 is connected to a second control signal input end of the control module 1, so as to control a working state of the zeroth MOS transistor 200 through a signal of the second control signal input end.
In other embodiments, which are not shown in the drawings, the gate of the zeroth MOS transistor 200 may be further connected to the output end of the control module 1, so that the zeroth MOS transistor 200 is selectively controlled by the control module 1.
Of course, the present invention is not limited thereto, and other connection manners of the gate of the zeroth MOS transistor 200 or other methods capable of controlling the zeroth MOS transistor 200 are within the protection scope of the present invention.
Therefore, the control module 1 is configured to control the operating states of the second power transistor 301 and the zeroth MOS transistor 200 and the first MOS transistor 201 to the seventh MOS transistor 207.
The control module 1 is further configured to: and obtaining the minimum value of k based on the ratio of the size of the zeroth MOS tube 200 to the size of the second power tube 301, wherein the minimum value of k is represented as a value meeting the minimum current acquisition precision.
Referring to fig. 4, regarding the control module 1, the control module 1 includes: a first control unit 101 and a second control unit 102, wherein the first control unit 101 comprises a first control signal input end, and the second control unit 102 comprises a second control signal input end;
wherein, the output end of the first control unit 101 is connected with the input end of the second control unit 102; the first control unit 101 is configured to select a plurality of first power transistors of the N first power transistors as selected power transistors; the second control unit 102 is configured to control the operating states of the second power transistor 301 and the selected power transistor.
In a preferred embodiment, the first control unit 101 comprises an encoder, and the second control unit 102 comprises a switch circuit;
the control module 1 is configured to: the encoder generates the first control signal through different permutation and combination and sends the first control signal to the switch circuit so as to select a plurality of first power tubes in the N first power tubes as selection power tubes; the switch circuit receives the first control signal and the second input control signal to control the working states of the selective power transistor and the zeroth MOS transistor and drive the second power transistor 301.
Wherein, the quantity of the first control signal is determined by the number of power tubes in the first collection module 2.
Of course, the present invention is not limited thereto, and other circuits capable of controlling the first and second acquisition modules 2 and 3 are within the protection scope of the present invention.
In another preferred embodiment, the switching circuit includes first to seventh switches.
Of course, the present invention is not limited thereto, the number of the switch circuits is the same as that of the first power transistors, and other numbers of the switch circuits are within the protection scope of the present invention.
The control module 1 is further configured to: the second input control signal controls the working states of the second power transistor 301 and the zeroth MOS transistor, and the first switch to the seventh switch respectively control the working states of the first MOS transistor 201 to the seventh MOS transistor 207.
In particular, the control module 1 is further configured to: based on the ratio of the size of the selected power tube in the first acquisition module 2 to the size of the second power tube 301, a k value is obtained.
Regarding the k value, in a specific embodiment, the k value is a ratio result of a sum of width-to-length ratios of the selected power transistors in the zeroth MOS transistor 200 and the first to seventh MOS transistors 201 to 207 and a width-to-length ratio of the second power transistor; specifically, k = [ (W/L) M0 +(W/L) M1～M 7 ]/(W/L) Second power tube 。
With regard to the second acquisition module 3, referring to fig. 4, the second acquisition module 3 is configured to:
acquiring first current reference information I flowing through the second acquisition module 2 ＝I 1 /k；
Based on first current reference information I flowing through the second acquisition module 2 、V os And R 2 Determining second current reference information I flowing through the second acquisition module 3 ＝I 2 +V os /R 2 。
Regarding the second input control signal, in a preferred embodiment, the second input control signal is a main control line signal GC generated by another control circuit, and the control circuit can adjust a value of the GC signal according to a system state, so as to adjust a current flowing through a power tube in the first collection module 2.
In one example, the main control line signal GC is characterized by the states of 0 and 1 in a digital circuit.
Of course, the present invention is not limited thereto, and analog values adjusted by other analog control circuits according to the system status are within the protection scope of the present invention.
In a specific embodiment, the first control signal is Iset, and if the first control signal Iset is 0000 001, it indicates that the first control unit 101 selects the first switch, and transmits the second input control signal GC to the output end of the control module 1, i.e., the output signal of the control module 1 is 1111 GC, so that the selected power transistor is the first MOS transistor M1;
the devices actually and effectively participating in current collection are the M1, the zeroth MOS transistor M0 and the second power transistor 301.
Based on the ratio of the sizes of the second power tube 301 and M1, M0, the value K is obtained.
GC in the above scheme is a gate voltage for the first acquisition module 2 and the second acquisition module 3, where 1 represents a high level, and can completely turn off the power tube.
Therefore, in the above scheme, the control module selects a plurality of first power tubes of the N first power tubes as the selected power tubes, and controls the working states of the selected power tubes, so as to obtain that the size ratio of the selected power tubes to the second power tubes is k, and since the N first power tubes have different sizes and have different values of k, the control module can control the conduction of the different first power tubes to adjust the value of k, so as to weaken the acquisition error caused by the input offset voltage and improve the acquisition precision.
The invention also provides electronic equipment comprising the high-precision current acquisition circuit.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and these modifications or substitutions do not depart from the spirit of the corresponding technical solutions of the embodiments of the present invention.
Claims (13)
1. A high accuracy current pickup circuit, comprising: the device comprises a control module, a first acquisition module, a second acquisition module and an operational amplifier module; the high-precision current acquisition circuit is used for acquiring current information flowing through the first acquisition module; the first acquisition module and the second acquisition module form a mirror image acquisition current structure; the second acquisition module comprises a second power tube; the first acquisition module comprises N first power tubes, and the N first power tubes are different in size, so that the proportion of the size of each first power tube to the size of the second power tube is different; wherein N is a positive integer and is more than or equal to 2;
the output end of the control module is connected with the first input end of the first acquisition module, the second input end of the control module is connected with the second input end of the first acquisition module and the input end of the second acquisition module, the output end of the first acquisition module is connected with the first input end of the operational amplifier module, and the output end of the second acquisition module is connected with the second input end of the operational amplifier module;
the control module is used for selecting a plurality of first power tubes in the N first power tubes as selection power tubes; and the working states of the second power tube and the selected power tube are controlled;
wherein, the first current reference information I flowing through the first acquisition module 1 And the first current reference information I flowing through the second acquisition module 2 Satisfies the following conditions:
I 2 ＝I 1 k is; k is the size ratio of the selected power tube to the second power tube;
an input offset voltage exists between the voltages of the first input end and the second input end of the operational amplifier module, and the control module adjusts the K value by switching different first power tubes to serve as the selective power tubes, so that the acquisition error caused by the input offset voltage is weakened, and the acquisition precision is improved.
2. The high-precision current collection circuit according to claim 1, wherein the second current reference information flowing through the second collection module satisfies: i is 3 ＝I 2 +V os /R 2 ；
Wherein, V os For inputting offset voltage, R 2 Is the internal resistance of the second acquisition module.
3. According to claimThe high-precision current acquisition circuit of claim 1 is characterized in that the N first power tubes are sequentially arranged in sequence, and the size of the first power tube which is ordered as the ith satisfies the following requirements: s i ＝X i Wherein S is i Is the size of the ith first power tube, X is a natural number and is more than or equal to 2, i is more than or equal to 1 and is less than or equal to N.
4. The high accuracy current acquisition circuit of any one of claims 1-3, wherein the control module comprises: the control system comprises a first control unit and a second control unit, wherein the first control unit comprises a first control signal input end, and the second control unit comprises a second control signal input end;
the output end of the first control unit is connected with the input end of the second control unit;
the first control unit is used for selecting a plurality of first power tubes in the N first power tubes as selected power tubes;
the second control unit is used for controlling the working states of the second power tube and the selected power tube.
5. The high accuracy current acquisition circuit of claim 4 wherein said first acquisition module comprises: the MOS transistor comprises a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor and a seventh MOS transistor;
the source electrodes and the drain electrodes of the first MOS transistor to the seventh MOS transistor are respectively connected to the source electrode and the drain electrode of the second power transistor, the grid electrodes of the first MOS transistor to the seventh MOS transistor are connected to the output end of the control module, and the grid electrode of the second power transistor is connected to the second control signal input end of the control module.
6. The high-precision current collecting circuit according to claim 5, wherein the first control unit comprises an encoder, and the second control unit comprises a switching circuit;
the control module is configured to:
the encoder generates the first control signal through different permutation and combination and sends the first control signal to the switch circuit so as to select a plurality of first power tubes in the N first power tubes as selection power tubes;
the switch circuit receives the first control signal and the second input control signal to control the working state of the selective power tube and drive the second power tube.
7. The high accuracy current collection circuit of claim 6, wherein said switching circuit comprises first through seventh switches;
the control module is further configured to:
the first switch to the seventh switch respectively control the working states of a plurality of MOS tubes in the first MOS tube to the seventh MOS tube.
8. The high accuracy current acquisition circuit of any of claims 7, wherein the control module is further configured to:
and obtaining a k value based on the ratio of the size of the selected power tube to the size of the second power tube in the first acquisition module.
9. The high accuracy current acquisition circuit of claim 8, wherein the first acquisition module is configured to:
acquiring first current reference information I flowing through the first acquisition module 1 ；
Based on I 1 And k, determining the reference information I of the first current flowing through the second acquisition module 2 ；
Reference information I of first current flowing through the second acquisition module 2 ＝I 1 And/k is transmitted to the second acquisition module and the operational amplifier module.
10. The high accuracy current acquisition circuit of claim 9, wherein the second acquisition module is configured to:
acquiring first current reference information I flowing through the second acquisition module 2 ＝I 1 /k；
Based on first current reference information I flowing through the second acquisition module 2 、V os And R 2 Determining second current reference information I flowing through the second acquisition module 3 ＝I 2 +V os /R 2 。
11. The high-precision current collection circuit according to claim 10, wherein the first collection module further comprises a zeroth MOS transistor, a source and a drain of the zeroth MOS transistor are connected in parallel to the second power transistor, and a gate of the zeroth MOS transistor is connected to the second control signal input terminal of the control module;
the control module is further configured to:
and obtaining the minimum value of k based on the ratio of the size of the zeroth MOS tube to the size of the second power tube, wherein the minimum value of k is represented as a value meeting the minimum current acquisition precision.
12. The high accuracy current acquisition circuit of claim 11 wherein said first power transistor and said second power transistor are all of the same type.
13. An electronic device comprising the high-precision current collection circuit according to any one of claims 1 to 12.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211055032.2A CN115267300A (en) | 2022-08-31 | 2022-08-31 | High-precision current acquisition circuit and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211055032.2A CN115267300A (en) | 2022-08-31 | 2022-08-31 | High-precision current acquisition circuit and electronic equipment |
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| Publication Number | Publication Date |
|---|---|
| CN115267300A true CN115267300A (en) | 2022-11-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211055032.2A Pending CN115267300A (en) | 2022-08-31 | 2022-08-31 | High-precision current acquisition circuit and electronic equipment |
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| Country | Link |
|---|---|
| CN (1) | CN115267300A (en) |
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2022
- 2022-08-31 CN CN202211055032.2A patent/CN115267300A/en active Pending
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