CN1152418C - Inactivation method of plastic packel GaAs chip - Google Patents
Inactivation method of plastic packel GaAs chip Download PDFInfo
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- CN1152418C CN1152418C CNB011137339A CN01113733A CN1152418C CN 1152418 C CN1152418 C CN 1152418C CN B011137339 A CNB011137339 A CN B011137339A CN 01113733 A CN01113733 A CN 01113733A CN 1152418 C CN1152418 C CN 1152418C
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- passivation
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- plastic packaging
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Abstract
The present invention provides a passivation method for plastically packaged gallium arsenide chips for improving the reliability for resisting against outside damp and heat environment of the plastically packaged chips. The core of the method is composed of low-stress silicon nitride (Si3N4) film growth and high-reliability buffering film polyimide (PPI). in two times of medium purification, a protective medium grows after gate manufacture at the first time; the protective medium grows at the second time by aiming at protect the medium of the chips except for press points for another time; PPI material is introduced for the third-time passivation after the second-time passivation is completed, and third-time passivation films are used as a stress matching buffering layer between plastic packaging material and chips.
Description
The invention belongs to GaAs microwave device and monolithic integrated circuit technology field, specifically a kind of GaAs (GaAs) chip passivation method that is used for plastic packaging.
Developing rapidly to the GaAs technology of mobile communication, optical-fibre communications brings unprecedented opportunities, for GaAs device and monolithic integrated circuit (IC) are introduced to the market as early as possible, must adopt the plastic packaging technology to reduce the cost of device and IC, improves the market competitiveness.GaAs chip plastic packaging faces two large problems: the one, and anti-extraneous hectic fever environment capacity is poor.GaAs microwave device and monolithic integrated circuit technology can not be by carrying out the dielectric passivation growth from body oxidation and low-pressure chemical vapor phase deposition (temperature is greater than 300 degree) as silicon integrated circuit, must adopt lower temperature technology to realize passivation, therefore be difficult to high steam (being called for short PCT) reliability examination, must improve GaAs chip passivation technology for this reason by plastic device; The 2nd, the stress that plastics are introduced also can superpose with the stress of passivating film, makes device and IC mis-behave even inefficacy.Middle and later periods nineteen nineties, carry out the research of this respect one after another based on each integrated company of big GaAs of the world of the U.S., each company all adopts separately method to carry out device and IC passivation.Conventional GaAs chip fabrication technique should carry out the protective medium growth first time immediately after finishing the grid making.After the positive technology of chip is finished, can select to carry out the growth of second layer medium.The growth conditions of medium is most important to the use of device performance and passivating technique.Heavily stressed meeting causes the be full of cracks of protective medium to make device performance degradation in technological operations such as pressure welding, plastic packaging; must control many parameters during the plasma deposition deielectric-coating; some variable is to being deposited with predictable influence, and the increase with pressure, power increases as deposition rate.Yet interact between the variable in many cases, make the difficulty of measuring and explaining the effect change of a certain particular variables.Therefore, the growth conditions of dielectric passivation is quite strict, must seek a kind of process program, makes the least possible increase stress of deielectric-coating after the growth, the deterioration of avoiding bringing device performance; Require the deielectric-coating densification of growth simultaneously, can resist of the thermal shock of PCT test mesohigh vapours chip.After the medium growth is finished,, should carry out the passivating film growth of the 3rd step in order to offset the stress impact of plastic packaging material.Passivating film also should have excellent anti-water vapor permeable ability except that as the coupling of the stress between plastic packaging material and the chip resilient coating for the third time, and the protection chip is particularly avoided environmental impact under high temperature, high pressure, high humidity environment condition.
From documents and materials, the device of some producers can be tested by high steam, as the Alpha company of the U.S., adopts following standard to carry out the high steam test, and 121 degrees centigrade, 2 atmospheric pressure, 100%RH, 96 hours, number of samples 45, allowing failure number is 0.(PCT test standard 4C) should be and randomly draws 76 samples for IEC, 749III, and 96 hours, 2 atmospheric pressure required zero failure but according to International Power.Number of samples nearly totally exceeds 70% than above-mentioned company, and the examination condition is sternly many.Therefore should improve passivation technology, satisfy the requirements at the higher level of International Power.
Purpose of the present invention just is being based on above requirement, provides a kind of GaAs chip passivation method that is used for plastic packaging for further improving the anti-extraneous hectic fever environmental reliability of GaAs plastic packaging chip.
Technical solution of the present invention:
The core of technical solution of the present invention is made up of two parts, and the one, low stress nitride silicon (Si
3N
4) the film growth, the 2nd, highly reliable buffer film polyimides (PPI).The GaAs chip passivation should be at first from optimizing the media protection technology.
The quality of deielectric-coating is by refractive index, thickness and three parameter decisions of stress, and the stress parameters index is the concentrated expression of all parameters.Should optimize key parameters such as temperature in the medium growth, pressure, growth time, obtain high-quality medium passivating film.
In order to reduce the stress of deposited film, and improve deielectric-coating compactness, we have designed following technology approach: twice medium passivation.Protective medium is grown in to finish and carries out immediately after grid are made for the first time, and the medium growth conditions is 170-220 ℃, pressure 700-1100mTorr, power 20-50W, gas ratio NH
3/ SiH
4/ 3-6/150-350, flow 600sccm, growth time 15-35 minute; Chip front side is electroplated, and anti-carves after technology finishes, and the reply chip carries out second time protective medium and grows.The purpose of protective medium growth for the second time is that the chip except that pressure point is carried out media protection again one time, thereby further improves the moisture resistance energy of chip.With the change segmentation deposit by power, temperature of the deielectric-coating of routine growth, temperature is respectively 170-220 ℃/170-220 ℃, and power is respectively 20-50W/25-50W, and each was grown 4-10 minute, pressure 900mTorr, gas ratio NH
3/ SiH
4/ 3-8/160-350, flow 600sccm, stress is by former 2 * 10 after tested
9Dyn/cm
2Dropped to about 5 * 10
8Dyn/cm
2, puncture voltage raising 1-2V after the more former normal condition passivation of puncture voltage after the passivation.
After each medium growth, photoetching, the dry etching by routine, processing step such as remove photoresist are realized the selective etching of dielectric passivation.
After passivation was for the second time finished, we introduced polyimides (PPI) material and do passivation for the third time.Passivating film is as the coupling of the stress between plastic packaging material and chip resilient coating for the third time.Because it is the dielectric constant of PPI film is 2.6, less to the electrical property influence of device; The extension performance of PPI excellence can be offseted the stress impact of plastic packaging material; PPI also has excellent anti-water vapor permeable ability, and the protection chip is particularly avoided environmental impact under high temperature, high pressure, high humidity environment condition.
The PPI membrane process technique guarantee that we are exclusive prepared PPI film possess the excellent properties of above three aspects.Process is as follows:
Gluing: 2000-5000rpm, 30 seconds time
Drying glue: 100-120 ℃
Exposure: I-Line exposure system, dosage 1000-1200mj/cm
2
Develop: developer solution cyclopatanone, time 30 "
Heat treatment: room temperature-300 ℃, time 3-5 hour.
After PPI membrane process technology is finished, the whole tube cores on the disk are carried out dc parameter test, prove PPI technology front and back saturation current, pinch-off voltage, Primary Component parameter rates of change such as reverse breakdown voltage are less than 2%, and rate of finished products changes less than 1%.
Advantage of the present invention:
(1) the present invention can satisfy IEC standard 749III, 4C, and promptly number of samples is 76, and 96 hours, 2 atmospheric pressure, zero failure.
(2) this passivating method is low stress Si
3N
4The perfect adaptation of film and highly reliable PPI film is simultaneously at Si
3N
4Both matching problems also should have been taken into full account in manufacture craft and the PPI technology: 1) stress coupling; 2) interface coupling.The stress coupling has solved the tolerance problem of PPI membrane stress buffering; The interface coupling has solved Si
3N
4The bonding problem of film and PPI film.Si
3N
4Growth technique in all multifactor by control, make Si
3N
4The quality densification, the decline of absorption steam is PPI film and Si
3N
4The bonding necessary condition of having created of high-quality.Step stepping drying glue technology in the PPI membrane process is evenly got rid of solvent linearly, and good homogeneous is arranged on the vertical distribution of quality, has fully guaranteed PPI film and Si on whole 3 inches areas
3N
4Even adhesion.
(3) this passivating method and GaAs chip technology are compatible fully, make simple and reliablely, and cost is low, is suitable for batch making, is a kind of plastic packaging chip passivation method of practicality.
Therefore the plastic packaging passivation of compound semiconductors such as (4) this method is equally applicable to silica removal indium phosphide in addition, gallium nitride and photoelectric device and IC circuit has very wide application prospect.
The passivation of embodiment (1) GaAs single-pole double throw monolithic IC
Chip area 1200 * 1000 μ m
2, 3 inches disks are made.At first adopt following medium passivating method:
Protective medium growth for the first time, temperature is 170 ℃, pressure 700mTorr, power 25W, gas ratio NH
3/ SiH
4/ 3/150, flow 600sccm, growth time 15 minutes.
Protective medium growth for the second time, temperature is respectively 180 ℃/220 ℃, and power is respectively 20W/25W, and each was grown 4 minutes, pressure 900mTorr, gas ratio NH
3/ SiH
4/ 8/350, flow 600sccm.
PPI passivation for the third time, condition is:
Gluing: 3500,30 seconds time
Drying glue: 110 ℃
Exposure: I-Line exposure system, dosage 1150mj/cm
2
Develop: developer solution cyclopatanone, time 30 "
Heat treatment: room temperature-300 ℃, 4 hours time.
SOT23-6L encapsulation, plastic packaging material are Japanese Nitto company 8000.Encapsulated device main DC parameter changes not obvious, illustrates that plastic packaging stress is effectively offseted.According to IEC (International Power) 749III, 4C randomly draws 76 samples, and 121 degrees centigrade, 96 hours, carry out the PCT test under 2 atmospheric pressure, require zero failure.Allow device reverse leakage parameter values to change one times with reference to the common PCT test of silicon device testing standard back.We under same testing standard, carry out DC test to 76 test devices in PCT test back, and all device reverse leakage changed less than 50% before and after the result showed test, and pinch-off voltage changes less than 10%, and saturation current changes less than 10%.Prove that 76 test device reverse leakage change in regulating scope, all by the PCT test, passivating method is successful.
(1) passivation of GaAs dpdt double-pole double-throw (DPDT) monolithic IC
Chip area 1300 * 1100 μ m
2, 3 inches disks are made.At first adopt following medium passivating method:
Protective medium growth for the first time, temperature is 210 ℃, pressure 1000mTorr, power 35W, gas ratio NH
3/ SiH
4/ 5/350, flow 600sccm, growth time 12 minutes.
Protective medium growth for the second time, temperature is respectively 200 ℃/220 ℃, and power is respectively 25W/35W, and each was grown 8 minutes, pressure 900mTorr, gas ratio NH
3/ SiH
1/ 4/250, flow 600sccm.
PPI passivation for the third time, condition is:
Gluing: 5000rpm, 30 seconds time
Drying glue: 115 ℃
Exposure: I-Line exposure system, dosage 1000mj/cm
2
Develop: developer solution cyclopatanone, time 30 "
Heat treatment: room temperature-300 ℃, 3 hours time
MSOP-8 encapsulation, plastic packaging material are Japanese Nitto company 7400, and encapsulated device main DC parameter changes not obvious, illustrates that plastic packaging stress is effectively offseted.。According to IEC (International Power) 749III, 4C randomly draws 76 samples, and 121 degrees centigrade, 96 hours, carry out the PCT test under 2 atmospheric pressure, require zero failure.Allow device reverse leakage parameter values to change one times with reference to the common PCT test of silicon device testing standard back.We under same testing standard, carry out DC test to 76 test devices in PCT test back, and all device reverse leakage changed less than 20% before and after the result showed test, and pinch-off voltage changes less than 10%, and saturation current changes less than 10%.Prove that 76 test device reverse leakage change in regulating scope, all by the PCT test, passivating method is successful.
(2) passivation of GaAs power field effect pipe
Chip area 540 * 300 μ m
2, 3 inches disks are made.At first adopt following medium passivating method:
Protective medium growth for the first time, temperature is 200 ℃, pressure 1100mTorr, power 40W, gas ratio NH
3/ SiH
4/ 5/250, flow 600sccm, growth time 12 minutes.
Protective medium growth for the second time, temperature is respectively 190 ℃/210 ℃, and power is respectively 40W/50W, and each was grown 7 minutes, pressure 900mTorr, gas ratio NH
3/ SiH
4/ 6/350, flow 600sccm.
PPI passivation for the third time, condition is:
Gluing: 2000rpm, 30 seconds time
Drying glue: 110 ℃
Exposure: I-Line exposure system, dosage 1200mj/cm
2
Develop: developer solution cyclopatanone, time 30 "
Heat treatment: room temperature-300 ℃, 3.5 hours time.
The SOT-89 encapsulation, plastic packaging material is the Japanese samitomo 6710s of company, encapsulated device main DC parameter changes not obvious, illustrates that plastic packaging stress is effectively offseted.。According to IEC (International Power) 749III, 4C randomly draws 76 samples, and 121 degrees centigrade, 96 hours, carry out the PCT test under 2 atmospheric pressure, require zero failure.Allow device reverse leakage parameter values to change one times with reference to the common PCT test of silicon device testing standard back.We under same testing standard, carry out DC test to 76 test devices in PCT test back, and all device reverse leakage changed less than 15% before and after the result showed test, and pinch-off voltage changes less than 10%, and saturation current changes less than 10%.Prove that 76 test device reverse leakage change in regulating scope, all by the PCT test, passivating method is successful.
Claims (2)
1. GaAs chip passivation method that is used for plastic packaging is characterized in that:
A. for the first time protective medium is grown in to finish and carries out immediately after grid are made, and the medium growth conditions is 170-220 ℃, pressure 700-110mTorr, power 20-50W, gas ratio NH
3: SiH
4=3-6: 150-350, flow 600sccm, growth time 15-35 minute;
B. the change segmentation deposit of power, temperature is passed through the deielectric-coating of routine growth in protective medium growth for the second time;
C. the polyimide passivation film is as the coupling of the stress between plastic packaging material and chip resilient coating for the third time, and the polyimide film process is as follows:
Gluing: 2000-5000rpm, 30 seconds time
Drying glue: 100-120 ℃
Exposure: I line exposing system, dosage 1000-1200mj/cm
2
Develop: developer solution cyclopentanone, 30 seconds time
Heat treatment: room temperature-300 ℃, time 3-5 hour.
2. the GaAs chip passivation method that is used for plastic packaging according to claim 1; the temperature that it is characterized in that protective medium growth for the second time is respectively 170-220 ℃/170-220 ℃, and power is respectively 20-50W/25-50W, and each was grown 4-10 minute; pressure 900mTorr, gas ratio NH
3: SiH
4=3-8: 160-350, flow 600sccm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011137339A CN1152418C (en) | 2001-06-29 | 2001-06-29 | Inactivation method of plastic packel GaAs chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011137339A CN1152418C (en) | 2001-06-29 | 2001-06-29 | Inactivation method of plastic packel GaAs chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1325132A CN1325132A (en) | 2001-12-05 |
| CN1152418C true CN1152418C (en) | 2004-06-02 |
Family
ID=4660440
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB011137339A Expired - Fee Related CN1152418C (en) | 2001-06-29 | 2001-06-29 | Inactivation method of plastic packel GaAs chip |
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| Country | Link |
|---|---|
| CN (1) | CN1152418C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101449376B (en) * | 2006-05-23 | 2011-04-20 | 飞思卡尔半导体公司 | Contact surrounded by passivation and polymide and method therefor |
-
2001
- 2001-06-29 CN CNB011137339A patent/CN1152418C/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101449376B (en) * | 2006-05-23 | 2011-04-20 | 飞思卡尔半导体公司 | Contact surrounded by passivation and polymide and method therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1325132A (en) | 2001-12-05 |
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