CN115241267B - Display panel and display device - Google Patents
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- CN115241267B CN115241267B CN202211036968.0A CN202211036968A CN115241267B CN 115241267 B CN115241267 B CN 115241267B CN 202211036968 A CN202211036968 A CN 202211036968A CN 115241267 B CN115241267 B CN 115241267B
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/40—OLEDs integrated with touch screens
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention discloses a display panel and a display device, the display panel includes: a display region and a non-display region at least partially surrounding the display region; the non-display area includes: an electrostatic guard ring disposed along a periphery of the non-display region; a shift register and fan-out wiring connected with the shift register; the electrostatic protection ring is electrically connected with the grounding wire through a connecting wire, and the electrostatic protection ring, the grounding wire and the connecting wire are all positioned on the first touch layer; the display panel further comprises a substrate base plate, and the fan-out wiring is positioned on one side, close to the substrate base plate, of the first touch layer in the direction perpendicular to the plane where the substrate base plate is positioned; in the direction perpendicular to the plane of the substrate, an isolation layer is arranged between the fan-out wiring and the connecting line; the isolation layer, the fan-out trace, and the connection line at least partially overlap in a direction perpendicular to a plane in which the substrate is located. The invention can improve the antistatic capability of the display panel and reduce the damage to the grid driving circuit.
Description
Technical Field
The present invention relates to the field of display technologies, and more particularly, to a display panel and a display device.
Background
With the development of electronic technology, the manufacturing of display panels has also tended to mature, and display panels provided in the prior art include liquid crystal display panels, organic light emitting display panels, plasma display panels, and the like. Organic light emitting diodes are increasingly used as a current-type light emitting device in high performance display, and an OLED display panel has excellent characteristics of self-luminescence, wide viewing angle, fast response speed, high contrast, wide color gamut, low energy consumption, thin panel, rich color, flexible display realization, wide operating temperature range and the like, so that the OLED display panel is known as a next-generation 'star' flat panel display technology. The OLED display panel comprises an anode, a cathode, a hole transmission layer, an organic light-emitting layer and an electron transmission layer, wherein the hole transmission layer, the organic light-emitting layer and the electron transmission layer are arranged between the anode and the cathode, the anode provides hole injection, the cathode provides electron injection, the holes and electrons injected by the cathode and the anode are combined in the organic light-emitting layer under the driving of external voltage, electron hole pairs (namely excitons) at a binding energy level are formed, and the excitons radiate and are de-excited to emit photons to generate visible light.
Static electricity is one of the main reasons for causing the working failure of the display panel, so the antistatic capability is also an important index of the performance of the display panel, the destructiveness of discharging the static electricity around the display area is far greater than that of discharging the static electricity in the middle of the display area, and the static electricity prevention function is usually realized by arranging an antistatic ring at the edge of the display area in the prior art, but the problem of damaging a grid driving circuit exists in the prior art.
Accordingly, it is desirable to provide a display panel and a display device capable of reducing damage to a gate driving circuit while preventing static electricity.
Disclosure of Invention
In view of this, the present invention provides a display panel and a display device capable of improving the antistatic ability of the display panel and reducing damage to the gate driving circuit.
In one aspect, the present invention provides a display panel including: a display region and a non-display region at least partially surrounding the display region;
The non-display area includes:
an electrostatic guard ring disposed along a periphery of the non-display region;
A shift register and fan-out wiring connected with the shift register;
The electrostatic protection ring is electrically connected with the grounding wire through a connecting wire, and the electrostatic protection ring, the grounding wire and the connecting wire are all positioned on the first touch layer;
The display panel further comprises a substrate base plate, and the fan-out wiring is positioned on one side, close to the substrate base plate, of the first touch layer in the direction perpendicular to the plane where the substrate base plate is positioned;
An isolation layer is arranged between the fan-out wiring and the connecting line in the direction perpendicular to the plane of the substrate base plate;
And the isolation layer, the fan-out wiring and the connecting line are at least partially overlapped in the direction perpendicular to the plane of the substrate.
On the other hand, the invention also provides a display device which comprises the display panel.
Compared with the prior art, the display panel and the display device provided by the invention have the advantages that at least the following effects are realized:
The display panel is provided with the static protection ring at the periphery of the non-display area, the static protection ring is connected with the grounding wire through the connecting wire, and when static electricity is generated at the edge of the display panel, the static electricity can be led out from the grounding wire through the static protection ring and the connecting wire, so that the static protection capability of the display panel is improved; in the invention, the shift register and the fan-out wiring connected with the shift register are arranged in the non-display area, the static protection ring is positioned on one side of the shift register and the fan-out wiring far away from the display area, the grounding wire is positioned on one side of the shift register and the fan-out wiring close to the display area, and the static protection ring, the grounding wire and the connecting wire are all positioned on the first touch layer, so that the connecting wire can be partially overlapped with the fan-out wiring in the direction vertical to the plane of the substrate, when static electricity passes from the static protection ring to the grounding wire through the connecting wire, transient high voltage can be generated at the connecting wire, the fan-out wiring overlapped with the connecting wire is damaged, and the shift register is further damaged, so that the display is affected.
Of course, it is not necessary for any one product embodying the invention to achieve all of the technical effects described above at the same time.
Other features of the present invention and its advantages will become apparent from the following detailed description of exemplary embodiments of the invention, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
Fig. 1 is a schematic plan view of a display panel according to the present invention;
FIG. 2 is an enlarged view of a portion of region M of FIG. 1;
FIG. 3 is a cross-sectional view taken along the direction A-A' in FIG. 2;
FIG. 4 is a block diagram of a pixel circuit according to the present invention;
FIG. 5 is a further cross-sectional view taken along line A-A' in FIG. 2;
FIG. 6 is a further cross-sectional view taken along line A-A' in FIG. 2;
FIG. 7 is a further cross-sectional view taken along line A-A' in FIG. 2;
FIG. 8 is a further cross-sectional view taken along line A-A' in FIG. 2;
FIG. 9 is a further cross-sectional view taken along line A-A' in FIG. 2;
FIG. 10 is a further cross-sectional view taken along line A-A' in FIG. 2;
FIG. 11 is a further cross-sectional view taken along line A-A' in FIG. 2;
Fig. 12 is a schematic plan view of a display device according to an embodiment of the present invention.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless it is specifically stated otherwise.
The following description of at least one exemplary embodiment is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any specific values should be construed as merely illustrative, and not a limitation. Thus, other examples of exemplary embodiments may have different values.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures.
In order to realize static prevention of the display panel in the related art, a static protection ring is arranged on the periphery of a non-display area of the display panel, which is close to the edge, and a lead wire in an R angle area of a lower frame connects the static protection ring to a grounding wire on one side, which is close to the display area, so that static is easy to damage a gate driving circuit to cause the failure of the gate driving circuit. In view of the above, the present invention provides a display panel and a display device for preventing static electricity from damaging a gate driving circuit, and detailed description of embodiments of the display panel will be given below.
Referring to fig. 1, 2 and 3, fig. 1 is a schematic plan view of a display panel according to the present invention, fig. 2 is a partially enlarged view of an area M in fig. 1, and fig. 3 is a cross-sectional view taken along A-A' in fig. 2. The display panel 100 in fig. 1 includes: a display area AA and a non-display area BB at least partially surrounding the display area AA; the non-display area BB includes: an electrostatic protection ring 10 disposed along the periphery of the non-display region BB; a shift register VSR and a fan-out trace 20 connected to the shift register VSR; as shown in fig. 3, the ground line 30 is electrically connected to the electrostatic protection ring 10 and the ground line 30 through the connection line 40, and the electrostatic protection ring 10, the ground line 30 and the connection line 40 are all located in the first touch layer 60; the display panel 100 further includes a substrate 1, and the fan-out trace 20 is located on a side of the first touch layer 60, which is close to the substrate 1, in a direction perpendicular to a plane of the substrate 1; an insulating layer 50 is included between the fan-out traces 20 and the connection lines 40 in a direction perpendicular to the plane of the substrate 1; the isolation layer 50, the fan-out traces 20, the connection lines 40 at least partially overlap in a direction perpendicular to the plane of the substrate 1.
It should be noted that, fig. 1 also illustrates that the display panel 100 further includes a non-display area BB surrounding the display area AA, fig. 1 illustrates the display panel 100 by taking only a rectangular display panel 100 as an example, and in some other embodiments of the present application, the display panel 100 may also be embodied in other shapes, such as a circular shape, an oval shape, or a special-shaped structure. Fig. 1 shows only the case where the non-display area BB completely surrounds the display area AA, but the non-display area BB may also partially surround the display area AA (e.g., a water droplet screen), which is not particularly limited herein. Fig. 1 shows only a part of the sub-pixels P in the display area AA, and does not represent the actual number and arrangement of the sub-pixels P contained in the display area AA, and fig. 1 does not represent the actual size of the sub-pixels P, which is merely illustrative.
Alternatively, the display panel 100 may be an organic light emitting display panel 100, and of course, may also be a liquid crystal display panel 100. Also shown in fig. 1 and 2 is a driver chip IC, which provides signals to a shift register VSR, and the shift register VSR is electrically connected to the driver chip IC through a fanout line 20, where the fanout line 20 may be a clock signal line, a trigger signal line, a high potential signal line, a low potential signal line, etc., and the number of the fanout lines 20 in fig. 1 and 2 is merely illustrative. Fig. 1 and 2 also show a scan line G and a data line S, which intersect to define a region of the sub-pixel P, the scan line G is electrically connected to a shift register VSR, the shift register VSR supplies a gate driving signal to the scan line G, the data line S is electrically connected to a driving chip IC, and the driving chip IC supplies a data voltage to the data line S. For the pixel driving circuit in the sub-pixel P, 7T1C, for example, the pixel driving circuit in fig. 4 may be employed. Referring to fig. 4, fig. 4 is a block diagram of a pixel circuit according to the present invention, where the pixel circuit Q may be 7T1C, and includes: a first transistor M1 having a control terminal electrically connected to the light emitting signal input terminal, a first terminal electrically connected to the first power signal terminal PVDD, and a second terminal electrically connected to the first terminal of the driving transistor M0; a second transistor M2 having a control terminal electrically connected to the second scan signal input terminal S2, a first terminal electrically connected to the data signal input terminal Vdata, and a second terminal electrically connected to the first terminal of the driving transistor M0; a driving transistor M0 having a control terminal electrically connected to the second terminal of the fourth transistor M4, and a first terminal electrically connected to the second terminal of the first transistor M1 and the second terminal of the second transistor M2; a third transistor M3 having a control terminal electrically connected to the second scan signal input terminal S2, a first terminal electrically connected to the second terminal of the fourth transistor M4 and the second terminal of the storage capacitor Cst, and a second terminal electrically connected to the second terminal of the driving transistor M0 and the first terminal of the fifth transistor M5; a fourth transistor M4 having a control terminal electrically connected to the first scan signal input terminal S1, a first terminal electrically connected to the reference voltage signal input terminal Vref, and a second terminal electrically connected to the control terminal of the driving transistor M0; a fifth transistor M5 having a control terminal electrically connected to the emission signal input terminal Emit, a first terminal electrically connected to the second terminal of the driving transistor M0 and the second terminal of the third transistor M3, and a second terminal electrically connected to the anode 12 of the light emitting element O; a sixth transistor M6 having a control terminal electrically connected to the second scan signal input terminal, a first terminal electrically connected to the reference voltage signal input terminal Vref, and a second terminal electrically connected to the first terminal of the light emitting element O; a light emitting element O having a first terminal electrically connected to the second terminal of the fifth transistor M5 and the second terminal of the sixth transistor M6, and a second terminal electrically connected to the second power signal terminal PVEE; the first terminal of the storage capacitor Cst is electrically connected to the first power signal terminal PVDD, and the second terminal is electrically connected to the control terminal of the driving transistor M0, the first terminal of the third transistor M3, and the second terminal of the fourth transistor M4.
Referring to the cross-sectional view of fig. 3, in fig. 3, taking the display panel 100 as an example of the organic self-luminous display panel 100, the display panel 100 in this embodiment includes: a substrate 1; a thin film transistor T located on one side of the substrate 1; a light emitting device 11 located on a side of the thin film transistor T away from the substrate 1; the light emitting device 11 comprises an anode 12 layer, a light emitting layer 13 on the side of the anode 12 remote from the substrate 1, and a cathode 14 on the side of the light emitting layer 13 remote from the substrate 1. The thin film transistor T drives the light emitting device 11 to emit light for display. Also shown in fig. 3 are film layers such as a buffer layer 2, an interlayer insulating layer, a gate insulating layer, a planarizing layer, a pixel defining layer 8, and the like, the thin film transistor T includes a second metal layer T2 (source and drain), and a first metal layer T1 is provided between the anode 12 layer and the second metal layer T2. Optionally, a thin film transistor is located on the buffer layer 2. Fig. 3 illustrates a structure of a top gate thin film transistor. The thin film transistor includes a semiconductor active layer including a source region and a drain region formed by doping N-type impurity ions or P-type impurity ions on the buffer layer 2. The region between the source region and the drain region is a channel region in which no impurity is doped. The semiconductor active layer may be formed by changing amorphous silicon into polycrystalline silicon through crystallization of amorphous silicon. To crystallize the amorphous silicon. The first metal layer T1 (gate electrode) is on the gate insulating layer, and the gate electrode may include a single layer or a plurality of layers of gold (Au), silver (Ag), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), aluminum (Al), molybdenum (Mo), or chromium (Cr), or an alloy such as aluminum (Al): neodymium (Nd) alloy, molybdenum (Mo): tungsten (W) alloy. The first metal layer T1 has a source electrode and a drain electrode electrically connected (or bonded) to the active layer source region and the drain region, respectively, through contact holes formed by selectively removing the insulating layer. Optionally, fig. 3 further shows an encapsulation layer 70 located on a side of the light emitting device 11 away from the substrate 1, where the optional encapsulation layer 70 is a stacked structure of an inorganic encapsulation layer 70, an organic encapsulation layer 702, and an inorganic encapsulation layer 70, and of course, the specific structure of the encapsulation layer 70 is not limited in the present invention, and the encapsulation layer 70 may have multiple inorganic encapsulation layers 70 and multiple organic encapsulation layers 702, so as to form a good protection for the light emitting device 11 in the display area AA. The packaging layer 70 further includes a first touch layer 60 on a side far from the substrate 1, and the optional first touch layer 60 is a metal layer nearest to the finger of the display panel 100, for detecting the touch of the display panel 100.
It should be noted that, fig. 1 and 2 also show that the retaining wall BK is disposed on the side of the electrostatic protection ring 10 near the display area AA, where the retaining wall BK serves to prevent water and oxygen from entering the display area AA, and an organic film layer cannot be disposed at the position of the retaining wall BK, so as to prevent the reliability of the display panel 100 from being affected by the corrosion of the water and oxygen. Of course, in order to ensure the reliability of the display panel 100, the height of the barrier layer 50 in the direction perpendicular to the plane of the substrate 1 after adding the barrier layer cannot be higher than the height of the barrier BK, so as to ensure the reliability of the display panel 100.
In the present embodiment, the isolation layer 50 is schematically disposed on the side of the pixel defining layer 8 away from the substrate 1, and of course, the location of the isolation layer 50 is merely illustrative, as long as the isolation layer 50 is located between the fan-out line 20 and the connection line 40 along the direction perpendicular to the plane of the substrate 1.
Optionally, the insulating layer 50, the fan-out traces 20, and the connection lines 40 partially overlap in a direction perpendicular to the plane of the substrate 1, and of course, the insulating layer 50 may cover a region where the connection lines 40 overlap the fan-out traces 20 in a direction perpendicular to the plane of the substrate 1.
Of course, the number of connection lines 40 is only schematically shown in fig. 1 and 2, and a plurality of connection lines 40 may be optionally provided in parallel to be connected between the electrostatic protection ring 10 and the ground line 30, so that the instantaneous voltage on each connection line 40 can be reduced.
In the embodiment, the electrostatic protection ring 10 is disposed at the periphery of the non-display area BB, and the electrostatic protection ring 10 is connected with the ground line 30 through the connection line 40, when static electricity is generated at the edge of the display panel 100, the static electricity can be led out from the ground line 30 through the electrostatic protection ring 10 and the connection line 40, so as to improve the electrostatic protection capability of the display panel 100;
In the invention, a shift register VSR and a fan-out trace 20 connected with the shift register VSR are disposed in a non-display area BB, an electrostatic protection ring 10 is disposed on one side of the shift register VSR and the fan-out trace 20 away from a display area AA, a ground line 30 is disposed on one side of the shift register VSR and the fan-out trace 20 close to the display area AA, and the electrostatic protection ring 10, the ground line 30 and a connecting line 40 are disposed on a first touch layer 60, so that the connecting line 40 and the fan-out trace 20 are partially overlapped in a direction perpendicular to a plane of a substrate 1, in the prior art, when static electricity is transferred from the electrostatic protection ring 10 to the ground line 30 through the connecting line 40, an instant high voltage is generated at the connecting line 40, and the fan-out trace 20 overlapped with the connecting line 40 is damaged, and the shift register VSR is damaged, and the display is affected.
In some alternative embodiments, referring to fig. 5, fig. 5 is a cross-sectional view of fig. 2 along the direction A-A', the display panel includes a first metal layer T1 on one side of the substrate 1, a capacitive metal layer Tc on one side of the first metal layer T1 near the first touch layer 60, and a pixel defining layer 8 on one side of the capacitive metal layer Tc near the first touch layer 60; the fanout wire 20 is positioned on the first metal layer T1 and the capacitor metal layer Tc; the pixel defining layer 8 includes a first portion 8001 located in the display area AA, and a second portion 8002 located in the non-display area BB, the thickness of the first portion 8001 being smaller than the thickness of the second portion 8002 in a direction perpendicular to a plane in which the substrate base plate 1 is located; the second portion 8002 is multiplexed as the insulating layer 50.
It should be understood that, in general, the fan-out wires 20 are disposed on the first metal layer T1 and the capacitor metal layer Tc, and are specifically disposed on the corresponding film layers according to different signals transmitted by the signal wires, and fig. 5 only illustrates that two fan-out wires 20 are disposed on the capacitor metal layer Tc and one fan-out wire 20 is disposed on the first metal layer T1, which is not used for limiting the actual number of the fan-out wires 20 or limiting the film layers of the fan-out wires 20 in an actual product. The size of the orthographic projection area of the second portion 8002 on the substrate 1 is not particularly limited, but it is needless to say that the larger the orthographic projection area of the second portion 8002 on the substrate 1, the better, and only the fan-out wiring 20 can be covered in fig. 5 will be described as an example.
For the organic self-luminous display panel 100, the pixel defining layer 8 is a film layer that must be provided in the display panel 100, and the pixel defining layer 8 may be formed of an organic material such as polyimide, polyamide, benzocyclobutene, acryl resin, or phenol resin. In this embodiment, the pixel defining layer 8 includes a first portion 8001 located in the display area AA, and a second portion 8002 located in the non-display area BB, in a direction perpendicular to the plane of the substrate 1, the thickness of the first portion 8001 is smaller than that of the second portion 8002, the pixel defining layer 8 corresponding to the connection line 40 in the non-display area BB is thicker, that is, the second portion 8002 is used as the isolation layer 50, the second portion 8002 is patterned in fig. 5 for clearly showing the position of the second portion 8002, and of course, the second portion 8002 and the first portion 8001 may be made of the same material, and the second portion 8002, the fanout trace 20, and the connection line 40 at least partially overlap in a direction perpendicular to the plane of the substrate 1. Of course, the insulation layer 50 is not required to be additionally arranged by utilizing the original film layer in the display panel, so that the manufacturing process is simplified, and the production cost is reduced.
In some alternative embodiments, referring to fig. 6, fig. 6 is a cross-sectional view of fig. 2 along the direction A-A', the display panel 100 includes a first metal layer T1 on one side of the substrate 1, a capacitive metal layer Tc on one side of the first metal layer T1 near the first touch layer 60, a second metal layer T2 on one side of the capacitive metal layer Tc near the first touch layer 60, and a first insulating layer 5 between the capacitive metal layer Tc and the second metal layer T2 in a direction perpendicular to the plane of the substrate 1; the first insulating layer 5 includes a third portion 5001 located in the display area AA and a fourth portion 5002 located in the non-display area BB, the thickness of the third portion 5001 being smaller than the thickness of the fourth portion 5002 in a direction perpendicular to the plane of the substrate 1; the fourth portion 5002 is multiplexed as an insulating layer 50.
The size of the orthographic projection area of the fourth portion 5002 on the substrate 1 is not particularly limited, but it is needless to say that the larger the orthographic projection area of the fourth portion 5002 on the substrate 1, the better, and fig. 6 illustrates only an example in which the fan-out wiring 20 can be covered.
It can be understood that, in the display panel 100, the first insulating layer 5 needs to be disposed between the capacitor metal layer Tc and the second metal layer T2 for insulation, in this embodiment, the first insulating layer 5 includes a third portion 5001 located in the display area AA and a fourth portion 5002 located in the non-display area BB, in a direction perpendicular to the plane of the substrate 1, the thickness of the third portion 5001 is smaller than that of the fourth portion 5002, the first insulating layer 5 corresponding to the connection line 40 in the non-display area BB is made thicker, that is, the fourth portion 5002 is used as the insulating layer 50, and in order to clearly show the position of the fourth portion 5002, in fig. 6, the fourth portion 5002 and the third portion 5001 may be made of the same material, and in a direction perpendicular to the plane of the substrate 1, the fourth portion 5002, the fan-out running line 20 and the connection line 40 at least partially overlap, so that when the high voltage generated by static electricity passes through the connection line 40, the fourth portion 5002 is made of the insulating layer, and the fourth portion 5002 is not damaged by the fan-out line will not be damaged by the transient display. Of course, the insulation layer 50 is not required to be additionally arranged by utilizing the original film layer in the display panel, so that the manufacturing process is simplified, and the production cost is reduced.
In some alternative embodiments, referring to fig. 7, fig. 7 is a cross-sectional view of fig. 2 along the direction A-A', the display panel 100 includes a first metal layer T1 on one side of the substrate 1, a capacitive metal layer Tc on one side of the first metal layer T1 adjacent to the first touch layer 60, a second metal layer T2 on one side of the capacitive metal layer Tc adjacent to the first touch layer 60, a third metal layer T3 on one side of the second metal layer T2 adjacent to the first touch layer 60, and a second insulating layer 6 between the second metal layer T2 and the third metal layer T3 in a direction perpendicular to the plane of the substrate 1; the second insulating layer 6 includes a fifth portion 6001 located in the display area AA and a sixth portion 6002 located in the non-display area BB, the thickness of the fifth portion 6001 being smaller than the thickness of the sixth portion 6002 in a direction perpendicular to the plane in which the substrate 1 is located; the sixth portion 6002 is multiplexed into the insulating layer 50.
The size of the orthographic projection area of the sixth portion 6002 on the substrate 1 is not particularly limited, but it is needless to say that the larger the orthographic projection area of the sixth portion 6002 on the substrate 1 is, the better, and fig. 7 illustrates only an example in which the fan-out wiring 20 can be covered.
It can be understood that the third metal layer T3 is used for disposing the data line S, the second metal layer T2 is used for disposing the source electrode and the drain electrode of the transistor, the second insulating layer 6 needs to be disposed between the second metal layer T2 and the third metal layer T3, in this embodiment, the second insulating layer 6 is included between the second metal layer T2 and the third metal layer T3, the second insulating layer 6 includes a fifth portion 6001 located in the display area AA and a sixth portion 6002 located in the non-display area BB, and in a direction perpendicular to the plane of the substrate 1, the thickness of the fifth portion 6001 is smaller than the thickness of the sixth portion 6002; the sixth portion 6002 is multiplexed into the isolation layer 50, the thickness of the fifth portion 6001 is smaller than the thickness of the sixth portion 6002, the second insulating layer 6 corresponding to the connection line 40 in the non-display area BB is made thick, that is, the sixth portion 6002 is used as the isolation layer 50, in order to clearly show the position of the sixth portion 6002, the sixth portion 6002 is pattern-filled in fig. 7, of course, the sixth portion 6002 and the fifth portion 6001 may be made of the same material, and the sixth portion 6002, the fan-out trace 20 and the connection line 40 at least partially overlap in the direction perpendicular to the plane of the substrate 1, so that when the transient high voltage generated by static electricity passes through the connection line 40, the transient high voltage is isolated by the sixth portion 6002 of the second insulating layer 6, which will not damage the fan-out trace 20, will not damage the shift register, and the reliability of the display panel is improved. Of course, the insulation layer 50 is not required to be additionally arranged by utilizing the original film layer in the display panel, so that the manufacturing process is simplified, and the production cost is reduced.
In some alternative embodiments, referring to fig. 8, fig. 8 is a cross-sectional view of fig. 2 along the direction A-A', the display panel 100 includes a first metal layer T1 on one side of the substrate 1, a capacitive metal layer Tc on one side of the first metal layer T1 near the first touch layer 60, a second metal layer T2 on one side of the capacitive metal layer Tc near the first touch layer 60, a third metal layer T3 on one side of the second metal layer T2 near the first touch layer 60, an anode 12 on one side of the third metal layer T3 near the first touch layer 60, and a cathode 14 on one side of the anode 12 near the first touch layer 60; in the display area AA, a pixel defining layer 8 is included between the anode 12 and the cathode 14 in a direction perpendicular to the plane in which the substrate 1 is located; in the non-display region BB, a third insulating layer 15 is provided between the anode 12 and the cathode 14 in a direction perpendicular to the plane in which the substrate 1 is located; the thickness of the third insulating layer 15 is greater than the thickness of the pixel defining layer 8 in a direction perpendicular to the plane in which the substrate 1 lies; the third insulating layer 15 is multiplexed as an insulating layer 50.
It will be appreciated that the pixel defining layer 8 may be disposed only in the display area AA, but the pixel defining layer 8 is not disposed in the non-display area BB, and of course, the light emitting layer 13 is also disposed only in the display area AA, and the light emitting layer 13 is not disposed in the non-display area BB, where the third insulating layer 15 may be disposed between the anode 12 and the cathode 14 in the non-display area BB, and the thickness of the third insulating layer 15 in the direction perpendicular to the plane of the substrate 1 is greater than the thickness of the pixel defining layer 8 in the display area AA in the direction perpendicular to the plane of the substrate 1, and the third insulating layer 15, the fan-out trace 20, and the connection line 40 are at least partially overlapped in the direction perpendicular to the plane of the substrate 1, so that when the transient high voltage generated by static electricity passes through the connection line 40, the third insulating layer 15 insulates the transient high voltage, and does not damage the fan-out trace 20, nor damage the shift register, and improves the reliability of the display panel.
In some alternative embodiments, referring to fig. 9, fig. 9 is a cross-sectional view of fig. 2 along the direction A-A', the display panel includes a first metal layer T1 on one side of the substrate 1, a capacitive metal layer Tc on one side of the first metal layer T1 near the first touch layer 60, a second metal layer T2 on one side of the capacitive metal layer Tc near the first touch layer 60, a third metal layer T3 on one side of the second metal layer T2 near the first touch layer 60, an anode 12 on one side of the third metal layer T3 near the first touch layer 60, a cathode 14 on one side of the anode 12 near the first touch layer 60, and an encapsulation layer 70 on one side of the cathode 14 near the first touch layer 60; the encapsulation layer 70 includes a seventh portion 7001 located in the display area AA and an eighth portion 7002 located in the non-display area BB, the thickness of the eighth portion 7002 being greater than the thickness of the seventh portion 7001 in a direction perpendicular to a plane in which the substrate base plate 1 is located; the eighth section 7002 is multiplexed as the insulating layer 50.
It will be appreciated that the purpose of the encapsulation layer 70 is to protect the light emitting device 11 in the display area AA from the ingress of water and oxygen into the display area AA, the encapsulation layer 70 may be a stacked structure of an inorganic encapsulation layer 70, an organic encapsulation layer 702 and an inorganic encapsulation layer 70, not shown in fig. 9, of course, the specific structure of the encapsulation layer 70 is not limited in the present invention, and the thin film encapsulation layer 70 may have a plurality of inorganic encapsulation layers 70 and a plurality of organic encapsulation layers 702, so as to form a good protection for the device in the display area AA. The height of the retaining wall BK may be made large enough in fig. 9 to ensure that the thickness of the eighth portion 7002 is greater than the thickness of the seventh portion 7001.
The encapsulation layer 70 includes a seventh portion 7001 located in the display area AA and an eighth portion 7002 located in the non-display area BB, the thickness of the eighth portion 7002 being greater than the thickness of the seventh portion 7001 in a direction perpendicular to a plane in which the substrate base plate 1 is located; the eighth portion 7002 is multiplexed to be the insulating layer 50, the encapsulation layer 70 corresponding to the connection line 40 in the non-display area BB is made thick, that is, the eighth portion 7002 is made to be the insulating layer 50, in order to clearly show the position of the eighth portion 7002, the portion playing the role of insulation in the eighth portion 7002 is filled with a pattern, of course, the eighth portion 7002 and the seventh portion 7001 may be made of the same material, and the eighth portion 7002, the fanout trace 20 and the connection line 40 are at least partially overlapped in the direction perpendicular to the plane of the substrate 1, so that when the transient high voltage generated by static electricity passes through the connection line 40, the eighth portion 7002 of the encapsulation layer 70 insulates the transient high voltage, which will not damage the fanout trace 20, will not damage the shift register, and improves the reliability of the display panel. Of course, the insulation layer 50 is not required to be additionally arranged by utilizing the original film layer in the display panel, so that the manufacturing process is simplified, and the production cost is reduced.
In some alternative embodiments, with continued reference to fig. 9, the encapsulation layer 70 includes a first inorganic encapsulation layer 701, an organic encapsulation layer 702, and a second inorganic encapsulation layer 703 that are sequentially stacked on a side of the cathode 14 proximate to the first touch layer 60;
The thickness of the portion of the second inorganic encapsulation layer 703 located in the non-display region BB is greater than the thickness of the portion of the second inorganic encapsulation layer 703 located in the display region AA.
In fig. 9, the package layer 70 has a first inorganic package layer 701 located on a side of the cathode 14 away from the substrate 1, an organic package layer 702 located on a side of the first inorganic package layer 701 away from the substrate 1, and a second inorganic package layer 703 located on a side of the organic package layer 702 away from the substrate 1, and in fig. 9, only the thickness of a portion of the second inorganic package layer 703, which is not the display area BB, is schematically shown to be greater than the thickness of a portion of the display area AA, so that the second inorganic package layer 703 is made thick as the insulating layer 50, thereby insulating the fan-out trace 20 from being damaged due to the instantaneous high voltage generated when static electricity passes through the connection line 40, and improving the reliability of the display panel.
In some alternative embodiments, referring to fig. 10, fig. 10 is a cross-sectional view of fig. 2 along the direction A-A', the display panel 100 includes a first metal layer T1 located on one side of the substrate 1, a capacitive metal layer Tc located on one side of the first metal layer T1 and the first touch layer 60, a second metal layer T2 located on one side of the capacitive metal layer Tc and the first touch layer 60, a third metal layer T3 located on one side of the second metal layer T2 and the first touch layer 60, an anode 12 located on one side of the third metal layer T3 and the first touch layer 60, a cathode 14 located on one side of the anode 12 and the first touch layer 60, an encapsulation layer 70 located on one side of the cathode 14 and the first touch layer 60, a second touch layer 17 located on one side of the encapsulation layer 70 and the first touch layer 60, and a fourth insulating layer 16 located between the first touch layer 60 and the second touch layer 17 in a direction perpendicular to the plane of the substrate 1; the fourth insulating layer 16 includes a ninth portion 1601 located in the display area AA and a tenth portion 1602 located in the non-display area BB, and the tenth portion 1602 has a thickness greater than that of the ninth portion 1601 in a direction perpendicular to the plane of the substrate 1; the tenth portion 1602 is multiplexed into the barrier layer 50.
It can be understood that the organic self-luminous display panel 100 needs to use an externally hung touch structure, the touch electrodes are distributed on the first touch layer 60 and the second touch layer 17, the first touch layer 60 is the layer closest to the finger, the second touch layer 17 is located on one side of the first touch layer 60 close to the substrate 1, the fourth insulating layer 16 is disposed between the first touch layer 60 and the second touch layer 17, in this embodiment, the fourth insulating layer 16 includes a ninth portion 1601 located in the display area AA and a tenth portion 1602 located in the non-display area BB, the thickness of the tenth portion 1602 is greater than that of the ninth portion 1601 in the direction perpendicular to the plane of the substrate 1, the tenth portion 1602 is multiplexed as the insulating layer 50, the tenth portion 1602 is made thick corresponding to the connecting wire 40 in the non-display area BB, and is used as the layer 50, in order to clearly show the position of the tenth portion 1602, in fig. 10, the tenth portion 1602 is filled with patterns, the tenth portion 1602 is of course, the tenth portion is made of the same material as the tenth portion, the tenth portion 1602, and the connecting wire is not damaged by the electrical insulation layer 40 in the direction perpendicular to the plane, and the fourth portion 1602 is not damaged by the electrical insulation layer 40, and the electrical insulation layer is instantaneously damaged when the fourth portion is not damaged by the electrical fan-out of the connecting wire is made in the direction perpendicular to the plane of the substrate 20, and the tenth portion is not damaged by the electrical insulation layer 20. Of course, the insulation layer 50 is not required to be additionally arranged by utilizing the original film layer in the display panel, so that the manufacturing process is simplified, and the production cost is reduced.
In some alternative embodiments, with continued reference to fig. 1, the material of the insulating layer 50 is an inorganic material.
It can be appreciated that, if the insulating layer 50 is disposed in the non-display area BB, specifically in the R-angle position, if the organic material is disposed in the non-display area BB, which is not beneficial to the water-oxygen resistance of the display panel 100, in this embodiment, the material of the insulating layer 50 is an inorganic material, so that the inorganic material has better water-oxygen resistance, and can prevent water and oxygen from entering the display area AA from the non-display area BB, thereby improving the reliability of the display panel 100.
In some alternative embodiments, with continued reference to fig. 1, the insulating layer 50 covers the connection lines 40 in a direction perpendicular to the plane of the substrate 1.
The insulating layer 50 is used for insulating the connecting wire 40 from the fan-out wiring 20, so that the instant high current formed by static electricity in the connecting wire 40 is prevented from breaking down the fan-out wiring 20, the larger the overlapping area of the insulating layer 50 and the connecting wire 40 is in the direction perpendicular to the plane of the substrate 1, the better the insulating effect is, in the embodiment, the insulating layer 50 covers the connecting wire 40 in the direction perpendicular to the plane of the substrate 1, and thus the better insulating effect can be achieved.
In some alternative embodiments, with continued reference to fig. 2, the insulating layer 50 at least partially covers the ground line 30 in a direction perpendicular to the plane of the substrate 1.
It should be understood that, in fig. 2, the insulating layer 50 partially covers the ground line 30 in the direction perpendicular to the plane of the substrate 1, and of course, the area of the insulating layer 50 may be larger to completely cover the ground line 30, and it should be understood that the current generated when static electricity is conducted to the ground line 30 is relatively large, and other traces are not shown, and if the insulating layer 50 is disposed on the side of the ground line 30 close to the substrate 1, the influence of the ground line 30 on the other traces can be prevented.
In some alternative embodiments, referring to fig. 11, fig. 11 is a further cross-sectional view taken along the direction A-A' in fig. 2, the insulating layer 50 includes a plurality of insulating sublayers 500, the plurality of insulating sublayers 500 being located in different layers.
The insulating layer 50 is shown in fig. 11 to include two insulating sub-layers 500, namely the second portion 8002 of the pixel defining layer 8 and the fourth portion 5002 of the first insulating layer 5, and, in conjunction with fig. 7 to 10, the insulating layer 50 may include one or more of the sixth portion 6002 of the second insulating layer 6, the third insulating layer 15, the eighth portion 7002 of the encapsulation layer 70, and the tenth portion 1602 of the fourth insulating layer 16, which will not be described again here.
It can be understood that the greater the number of insulating sub-layers 500 in the insulating layer 50, the better the insulating effect, the more capable of preventing the transient high voltage generated by static electricity from breaking down the fan-out wiring 20, and the scratch is used as a register, thereby further improving the reliability of the display panel 100.
In some alternative embodiments, please refer to fig. 12, fig. 12 is a schematic plan view of a display device according to an embodiment of the present invention, and a display device 200 according to the present embodiment includes a display panel 100 according to the above embodiment. The embodiment of fig. 12 is only taken as an example of a mobile phone to describe the display device 200, and it is to be understood that the display device 200 provided in the embodiment of the present invention may be any other display device 200 having a display function, such as a computer, a television, a vehicle-mounted display device, etc., which is not particularly limited in the present invention. The display device 200 provided in the embodiment of the present invention has the beneficial effects of the display panel 100 provided in the embodiment of the present invention, and the specific description of the display panel 100 in the above embodiments may be referred to in the embodiments, which is not repeated here.
As can be seen from the above embodiments, the display panel and the display device provided by the present invention at least achieve the following beneficial effects:
The display panel is provided with the static protection ring at the periphery of the non-display area, the static protection ring is connected with the grounding wire through the connecting wire, and when static electricity is generated at the edge of the display panel, the static electricity can be led out from the grounding wire through the static protection ring and the connecting wire, so that the static protection capability of the display panel is improved; in the invention, the shift register and the fan-out wiring connected with the shift register are arranged in the non-display area, the static protection ring is positioned on one side of the shift register and the fan-out wiring far away from the display area, and the grounding wire is positioned on one side of the shift register and the fan-out wiring close to the display area, so that the connecting wire can be partially overlapped with the fan-out wiring in the direction vertical to the plane of the substrate, in the prior art, when static electricity passes from the static protection ring to the grounding wire through the connecting wire, instantaneous high voltage is generated at the connecting wire, the fan-out wiring overlapped with the connecting wire is damaged, and the shift register is damaged, thereby influencing the display.
While certain specific embodiments of the invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (12)
1. A display panel, comprising: a display region and a non-display region at least partially surrounding the display region;
The non-display area includes:
an electrostatic guard ring disposed along a periphery of the non-display region;
A shift register and fan-out wiring connected with the shift register;
The electrostatic protection ring is electrically connected with the grounding wire through a connecting wire, and the electrostatic protection ring, the grounding wire and the connecting wire are all positioned on the first touch layer;
The display panel further comprises a substrate base plate, and the fan-out wiring is positioned on one side, close to the substrate base plate, of the first touch layer in the direction perpendicular to the plane where the substrate base plate is positioned;
in the direction perpendicular to the plane of the substrate, an isolation layer is arranged between the fan-out wiring and the connecting line, and the isolation layer comprises at least one isolation sub-layer;
the isolation layer, the fan-out wiring and the connecting line are at least partially overlapped in the direction perpendicular to the plane of the substrate;
in the direction perpendicular to the plane of the substrate, the isolation layer covers the connecting line in the width direction of the connecting line.
2. The display panel of claim 1, wherein the display panel comprises,
The display panel comprises a first metal layer positioned on one side of the substrate base plate, a capacitance metal layer positioned on one side of the first metal layer close to the first touch control layer, and a pixel definition layer positioned on one side of the capacitance metal layer close to the first touch control layer;
The fan-out wire is positioned on the first metal layer and the capacitance metal layer;
The pixel definition layer comprises a first part and a second part, wherein the first part is positioned in the display area, the second part is positioned in the non-display area, and the thickness of the first part is smaller than that of the second part in the direction perpendicular to the plane of the substrate;
the second portion is multiplexed as the insulating layer.
3. The display panel according to claim 1, wherein the display panel includes a first metal layer on a side of the substrate, a capacitive metal layer on a side of the first metal layer adjacent to the first touch layer, a second metal layer on a side of the capacitive metal layer adjacent to the first touch layer, and a first insulating layer between the capacitive metal layer and the second metal layer in a direction perpendicular to a plane of the substrate;
the first insulating layer comprises a third part positioned in the display area and a fourth part positioned in the non-display area, and the thickness of the third part is smaller than that of the fourth part in the direction perpendicular to the plane of the substrate;
The fourth portion is multiplexed as the insulating layer.
4. The display panel according to claim 1, wherein the display panel includes a first metal layer on a side of the substrate, a capacitive metal layer on a side of the first metal layer adjacent to the first touch layer, a second metal layer on a side of the capacitive metal layer adjacent to the first touch layer, a third metal layer on a side of the second metal layer adjacent to the first touch layer, and a second insulating layer between the second metal layer and the third metal layer in a direction perpendicular to a plane in which the substrate is located;
The second insulating layer comprises a fifth part positioned in the display area and a sixth part positioned in the non-display area, and the thickness of the fifth part is smaller than that of the sixth part in the direction perpendicular to the plane of the substrate;
the sixth portion is multiplexed as the insulating layer.
5. The display panel of claim 1, wherein the display panel comprises a first metal layer on a side of the substrate, a capacitive metal layer on a side of the first metal layer adjacent to the first touch layer, a second metal layer on a side of the capacitive metal layer adjacent to the first touch layer, a third metal layer on a side of the second metal layer adjacent to the first touch layer, an anode on a side of the third metal layer adjacent to the first touch layer, and a cathode on a side of the anode adjacent to the first touch layer;
In the display area, a pixel definition layer is included between the anode and the cathode in a direction perpendicular to a plane in which the substrate is located;
A third insulating layer between the anode and the cathode in a direction perpendicular to a plane of the substrate in the non-display region;
the thickness of the third insulating layer is larger than that of the pixel defining layer in the direction perpendicular to the plane of the substrate;
the third insulating layer is multiplexed as the insulating layer.
6. The display panel of claim 1, wherein the display panel comprises a first metal layer on a side of the substrate, a capacitive metal layer on a side of the first metal layer adjacent to the first touch layer, a second metal layer on a side of the capacitive metal layer adjacent to the first touch layer, a third metal layer on a side of the second metal layer adjacent to the first touch layer, an anode on a side of the third metal layer adjacent to the first touch layer, a cathode on a side of the anode adjacent to the first touch layer, and an encapsulation layer on a side of the cathode adjacent to the first touch layer;
The packaging layer comprises a seventh part positioned in the display area and an eighth part positioned in the non-display area, and the thickness of the eighth part is larger than that of the seventh part in the direction perpendicular to the plane of the substrate;
the eighth portion is multiplexed as the insulating layer.
7. The display panel according to claim 6, wherein the encapsulation layer comprises a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer sequentially stacked on a side of the cathode adjacent to the first touch layer;
The thickness of the non-display area of any one of the first inorganic package, the organic package layer and the second inorganic package layer is greater than that of the display area.
8. The display panel of claim 1, comprising a first metal layer on a side of the substrate, a capacitive metal layer on a side of the first metal layer adjacent to the first touch layer, a second metal layer on a side of the capacitive metal layer adjacent to the first touch layer, a third metal layer on a side of the second metal layer adjacent to the first touch layer, an anode on a side of the third metal layer adjacent to the first touch layer, a cathode on a side of the anode adjacent to the first touch layer, an encapsulation layer on a side of the cathode adjacent to the first touch layer, a second touch layer on a side of the encapsulation layer adjacent to the first touch layer, and a fourth insulating layer between the first touch layer and the second touch layer in a direction perpendicular to a plane of the substrate;
The fourth insulating layer comprises a ninth part positioned in the display area and a tenth part positioned in the non-display area, and the thickness of the tenth part is larger than that of the ninth part in the direction perpendicular to the plane of the substrate;
The tenth portion is multiplexed as the insulating layer.
9. The display panel of claim 1, wherein the material of the insulating layer is an inorganic material.
10. The display panel of claim 1, wherein the insulating layer at least partially covers the ground line in a direction perpendicular to a plane in which the substrate lies.
11. The display panel of claim 1, wherein the insulating layer comprises a plurality of the insulating sublayers, the plurality of insulating sublayers being located on different layers.
12. A display device comprising the display panel of any one of claims 1-11.
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| CN107393906A (en) * | 2017-07-28 | 2017-11-24 | 上海天马有机发光显示技术有限公司 | A kind of organic electroluminescence display panel and preparation method thereof, organic light-emitting display device |
| CN110032007A (en) * | 2019-04-25 | 2019-07-19 | 厦门天马微电子有限公司 | Display panel and display device |
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