CN115241059A - Method for producing semiconductor structure with getter - Google Patents

Method for producing semiconductor structure with getter Download PDF

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Publication number
CN115241059A
CN115241059A CN202210781569.0A CN202210781569A CN115241059A CN 115241059 A CN115241059 A CN 115241059A CN 202210781569 A CN202210781569 A CN 202210781569A CN 115241059 A CN115241059 A CN 115241059A
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Prior art keywords
annealing
hours
density
substrate
getter
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CN202210781569.0A
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Chinese (zh)
Inventor
洪学天
赵大国
林和
王尧林
牛崇实
黄宏嘉
陈宏�
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Jinxin Advanced Technology Research Institute Shanxi Co ltd
Jinxin Electronics Manufacturing Shanxi Co ltd
Hongda Xinyuan Shenzhen Semiconductor Co ltd
Original Assignee
Jinxin Advanced Technology Research Institute Shanxi Co ltd
Jinxin Electronics Manufacturing Shanxi Co ltd
Hongda Xinyuan Shenzhen Semiconductor Co ltd
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Priority to CN202210781569.0A priority Critical patent/CN115241059A/en
Publication of CN115241059A publication Critical patent/CN115241059A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour

Abstract

The invention discloses a method for manufacturing a semiconductor structure by using a getter, belonging to the technical field of semiconductors. The method comprises the following steps: s01, annealing in an oxidizing atmosphere; s02, carrying out two-stage annealing in an inert atmosphere. The invention has the main advantages of high oxygen defect adsorption efficiency, simple process and low cost. The method adopted by the invention can be used for reducing the oxygen defect content of silicon-based semiconductor devices and integrated circuits, and can also be popularized and applied to reducing the micro defect content of substrates of compound semiconductor power devices and integrated circuits.

Description

Method for producing semiconductor structure with getter
Technical Field
The invention belongs to the technical field of semiconductors, and relates to a method for producing a semiconductor structure with a getter.
Background
In the fabrication of semiconductor devices, power devices and large and very large scale integrated circuits, how to reduce the oxygen content in silicon wafers is the key to improving the reliability and stability of semiconductor devices and integrated circuit applications.
Generally, the methods for forming silicon semiconductor ohmic contacts by reducing the oxygen content in silicon wafers are commonly used, and there are several methods:
1 forming an oxygen defect adsorption layer on the back surface of the silicon by chemical etching.
2 forming an oxygen defect adsorption layer on the back surface of the silicon by ion implantation.
3 techniques for methods and apparatus for removing impurities from a wafer of SOI (silicon on insulator) fabricated using a controlled dicing process.
The main drawbacks of the above described process are:
1, poor stability and repeatability;
2, the adsorption efficiency of oxygen is low;
3, the process is complex and the cost is high, such as an SOI adsorption layer method and the like.
Disclosure of Invention
The aim of the invention is to increase the stability of the gettering so that it is not necessary to take into account the oxygen content of the silicon. Through experimentation, it was found that additionally introducing a low temperature anneal of 430-450 ℃ during the process of forming the internal getter changed the oxygen precipitation process during the subsequent high temperature treatment: this significantly accelerates the formation of nucleation centers and actually leads to the formation of another type of microdefect. Introducing this annealing into the process for producing the internal getter allows the formation of getter centres in the wafer, even with wafers made by zone melting (i.e. melting of zones with low oxygen content).
The invention discloses a method for manufacturing a semiconductor structure by using a getter, which comprises the following steps:
s01, annealing in an oxidizing atmosphere;
s02, carrying out two-stage annealing in an inert atmosphere.
In some preferred embodiments of the present invention, in S01, annealing is performed in an oxidizing atmosphere at 1120-1250 ℃ for 2-3 hours (h).
In some preferred embodiments of the present invention, in S01, the oxidizing atmosphere is a dry oxygen atmosphere.
In some preferred embodiments of the present invention, in S01, the oxidizing atmosphere further comprises a chlorine-containing additive, preferably having an active chlorine content of 0.4-1.2% by weight based on the oxygen content.
In some preferred embodiments of the present invention, in S02, the two-stage annealing comprises annealing at 1000 to 1050 ℃ or 1020 to 1080 ℃ and annealing at 425 to 455 ℃; preferably, the annealing at 1000-1050 ℃ for 9-11 hours (h) or 1020-1080 ℃ for 3-6 hours (h) and the annealing at 425-455 ℃ for 1-7 hours (h) are included.
In some preferred embodiments of the present invention, the temperature and duration of the two-stage annealing in S02 depend on the density of micro-defects after the substrate is annealed in an oxidizing ambient.
In some preferred embodiments of the present invention, in S02, the density of micro-defects after annealing the substrate in an oxidizing ambient is < 2 × 10 4 cm -3 Firstly, annealing at 1000-1050 ℃ for 9-11 hours (h), and then annealing at 425-455 ℃ for 5-7 hours (h);
2×10 4 cm -3 the density of micro defects after the substrate is annealed in an oxidizing environment is less than or equal to 2 multiplied by 10 6 cm -3 Firstly, annealing at 1020-1080 ℃ for 3-6 hours (h), and then annealing at 425-455 ℃ for 5-7 hours (h);
2×10 6 cm -3 the density of micro defects after the substrate is annealed in an oxidizing environment is less than or equal to 2 multiplied by 10 7 cm -3 Firstly, annealing at 1020-1080 ℃ for 3-6 hours (h) And then annealed at 425-455 ℃ for 1-3 hours (h).
In some preferred embodiments of the present invention, the step of etching and determining the density of the etched pattern after S01 is further included.
In some preferred embodiments of the present invention, in the etching step, the silicon wafer is etched in a composition of 3 to 5 parts by weight of hydrogen fluoride, 45 to 50 parts by weight of chromic anhydride, and 45 to 50 parts by weight of water for 1.2 to 1.6 hours (h).
In some preferred embodiments of the present invention, the step of determining the density of the etching pattern performs a metallographic examination of the surface of the substrate under an optical microscope, and calculates the detected density of the etching pattern.
The invention has the beneficial effects that:
it was found through experiments that during the process of forming the internal getter, including a first step of annealing at 1120-1250 ℃ for 2-3 hours in an oxidizing atmosphere, and a second step of annealing at 1000-1080 ℃ for 3-11 hours and at 425-455 ℃ for 1-7 hours, respectively, in an inert atmosphere depending on the density of micro-defects in the semiconductor structure, a low temperature anneal in the range of 425-455 ℃ may change the oxygen precipitation process during the subsequent high temperature treatment: this significantly accelerates the formation of nucleation centers and actually leads to the formation of another type of microdefect. Introducing this annealing into the process for producing the internal getter allows the formation of getter centres in the wafer, even with wafers made by zone melting (i.e. melting of zones with low oxygen content).
The method has the main advantages of high oxygen defect adsorption efficiency, simple process and low cost. The method adopted by the invention can be used for reducing the oxygen defect content of silicon-based semiconductor devices and integrated circuits, and can also be popularized and applied to reducing the micro defect content of substrates of compound semiconductor power devices and integrated circuits.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Unless otherwise specified, the examples and comparative examples are parallel tests with the same components, component contents, preparation steps, preparation parameters.
Typically, in a starting silicon rod of silicon, the composition of the excimer Si-O-Si contains oxygen. The first high temperature heat treatment (oxidation at 1120-1250 ℃) and cooling after this treatment results in the removal of some of the dissolved oxygen from the excimer state and the onset of the formation of small oxygen complexes, an effect which can be seen in the etch pattern. The formation of these primary complexes depends on the oxygen content and on the growth history of the silicon rod, i.e. the presence of precipitation centers in the growth of the silicon ingot. Thus, selective metallographic monitoring after the first oxidation allows to evaluate the precipitation capacity of the material and to determine the time required for low temperature annealing at 455 ℃ and 1000-1080 ℃ to obtain high quality getters for a specific silicon rod material.
The time range of different density etched patterns after the first oxidation is determined through experimental selection. When the density of the air suction center is 3X 10 9 cm -3 And the predominant type of defects in the bulk is precipitation-dislocation complexes having an overall size of 0.25-0.55 μm, the internal getter can be considered a qualified getter. The getter can stably withstand subsequent heat treatment without losing its gettering ability during annealing at 1120 ℃ for 18-22 hours. Typically, this time exceeds the total time of high temperature heat treatment for many types of equipment.
The reduction of the annealing time at a temperature of 455 c compared to the time suggested by the different density of the etched pattern after the first oxidation leads to a sharp decrease in the density of the getter centers formed or to a reduction in the size of the oxygen precipitates formed, which in turn leads to the decomposition of these precipitates during the thermal treatment of the wafer and to a failure of the gettering action. The increased duration of annealing at 455 ℃ and 1000-1080 ℃ compared to the proposed protocol may lead to dislocations and getteringThe cores separate and appear in the active area of the silicon wafer, reducing the yield of the device crystal. Especially when the density of the etched pattern after the first oxidation is higher than 2X 10 4 cm -3 Even a further 30 minutes of annealing at 455 c results in the formation of too strong getters and dislocations on the working surface, resulting in substrate bowing. Therefore, at such a density of micro-defects after the first oxidation, it is generally not recommended to perform an additional annealing treatment at a temperature of 425-455 ℃ during the process cycle of internal getter formation.
At this temperature, at low microdefect densities, an increase in annealing time above 6 hours does not result in further activation of the precipitation process; conversely, an increase in the low temperature annealing time may result in a decrease in the getter center density. Then, by increasing the low temperature annealing time to 10-12 hours in an annealing process cycle of 1000-1080 ℃, even at very low micro-defect densities (less than 2 x 10) 4 cm -3 I.e., the oxygen content in silicon is very low), high quality internal getters can be obtained.
Without introducing a low temperature anneal of 425-455 c into the process cycle, increasing the anneal time at a temperature of 1000-1080 c does not ensure the formation of an internal getter on materials with low oxygen content.
Example 1
A monocrystalline silicon wafer with the crystal orientation of (100) is adopted, and the surface of the monocrystalline silicon wafer is subjected to chemical mechanical polishing and chemical cleaning. The silicon single crystal wafer has an oxygen concentration of 8.9-9.3X 10 17 cm -3 。
The substrate is preliminarily oxidized in dry oxygen gas added with gaseous hydrogen chloride (HCl) at 1220 ℃ (the content of active chlorine in an oxidizing environment is 1 percent), for 2 hours, and then etching is carried out in the composition, wherein the composition comprises the following components in percentage by mass: 4% of hydrogen fluoride, 48% of chromic anhydride and 48% of water, and selectively etching the silicon wafer for 1 hour. Prior to selective etching, the substrate is etched for a short period in a standard polish etchant to remove surface defects. Then, after the selective etching, the surface of the substrate was subjected to metallographic examination under an optical microscope, and the density of the detected etching pattern was calculated. The results showed that the defect density was 8.9X 10 6 -1.2×10 7 cm -3 Are a common feature. Then, the substrate is annealed in two stages: the first stage is annealed at 1050 ℃ for 5 hours; the second stage was annealed at a temperature of 435 ℃ for 2 hours. Furthermore, the substrate produced in this way was sent to study the quality of the getter. It is etched in a selective etchant and then the chip is examined under an optical microscope. Electrical tests and physical analysis methods such as capacitance-voltage (C-V), scanning Electron Microscopy (SEM), transmission Electron Microscopy (TEM), X-ray diffraction (XRD), etc. are used. The presence and width of the depletion region of the semiconductor device, the density of gettering sites within the substrate, distribution uniformity and appearance are recorded. In addition, the working surface of the substrate is inspected to establish the fact that the gettering region has effectively been formed free of defects in the semiconductor substrate.
Example 2
A monocrystalline silicon wafer with the crystal orientation of (100) is adopted, and the surface of the monocrystalline silicon wafer is subjected to chemical mechanical polishing and chemical cleaning. The silicon single crystal wafer has an oxygen concentration of 6.1-6.5X 10 17 cm -3 。
The substrate is preliminarily oxidized in dry oxygen gas added with gaseous hydrogen chloride (HCl) at 1220 ℃ (the content of active chlorine in an oxidizing environment is 1%) for 2 hours, and then etching is carried out in the composition, wherein the composition comprises the following components in percentage by mass: 4% of hydrogen fluoride, 48% of chromic anhydride and 48% of water, and carrying out selective etching on the silicon wafer for 1 hour. The substrate is etched for a short period of time in a standard polish etchant to remove surface defects prior to selective etching. Then, after the selective etching, the surface of the substrate was subjected to metallographic examination under an optical microscope, and the density of the detected etching pattern was calculated. The results showed that the defect density ranged from 5.3X 10 6 -7.2×10 6 cm -3 . The substrate is then annealed in two stages: the first stage annealing at 1020 ℃ for 3 hours; the second stage was annealed at a temperature of 450 c for 5 hours. Furthermore, the substrate produced in this way was sent to study the quality of the getter. It is etched in a selective etchant and then the chip is examined under an optical microscope. Methods using electrical tests and physical analysis, such as capacitance-voltage (C-V), scanning Electron Microscopy (SEM), transmission Electron Microscopy (TEM), X-ray diffraction(XRD), and the like. The presence and width of the depletion region of the semiconductor device, the getter center density within the substrate, the distribution uniformity and the appearance are recorded.
Example 3
A monocrystalline silicon wafer with the crystal orientation of (100) is adopted, and the surface of the monocrystalline silicon wafer is subjected to chemical mechanical polishing and chemical cleaning. The silicon single crystal wafer has an oxygen concentration of 1.6-1.8X 10 16 cm -3 。
The substrate is preliminarily oxidized in dry oxygen gas added with gaseous HCl (hydrogen chloride) (the content of active chlorine in an oxidizing environment is 1 percent) at the temperature of 1220 ℃ for 2 hours, and then etching is carried out in the composition, wherein the composition comprises the following components in percentage by mass: 4% of hydrogen fluoride, 48% of chromic anhydride and 48% of water, and selectively etching the silicon wafer for 1 hour. The substrate is etched for a short period of time in a standard polish etchant to remove surface defects prior to selective etching. Then, after the selective etching, the surface of the substrate was subjected to metallographic examination under an optical microscope, and the density of the detected etching pattern was calculated. The results showed that the defect density ranged from 1.1X 10 4 -1.7×10 4 cm -3 . The substrate is then annealed in two stages: the first stage is annealed at a temperature of 1020 ℃ for 10 hours; the second stage was annealed at a temperature of 450 c for 7 hours. Furthermore, the substrate produced in this way was sent to study the quality of the getter. It is etched in a selective etchant and then the chip is examined under an optical microscope. Electrical tests and physical analysis methods such as capacitance-voltage (C-V), scanning Electron Microscopy (SEM), transmission Electron Microscopy (TEM), X-ray diffraction (XRD), etc. are used. The presence and width of the depletion region of the semiconductor device, the density of gettering sites within the substrate, distribution uniformity and appearance are recorded.
Experimental results show that the production using the method for manufacturing getters proposed by the present invention allows to form high quality getter areas within the substrate; the merged region has a width of 8-30 microns and the presence of a large number of precipitate-dislocation centers uniformly distributed throughout the volume of the substrate is observed, with no recorded presence of defects in the depletion region of the semiconductor device.
The method adopted by the invention can be used for reducing the oxygen defect content of silicon-based semiconductor devices and integrated circuits, and can also be popularized and applied to reducing the micro defect content of substrates of compound semiconductor power devices and integrated circuits.
While the preferred embodiments and examples of the present invention have been described in detail, the present invention is not limited to the embodiments and examples, and various changes can be made without departing from the spirit of the present invention within the knowledge of those skilled in the art.

Claims (10)

1. A method of fabricating a semiconductor structure with a getter, comprising the steps of:
s01, annealing in an oxidizing atmosphere;
s02, carrying out two-stage annealing in an inert atmosphere.
2. The method of claim 1, wherein in S01, the annealing is performed in an oxidizing atmosphere at 1120-1250 ℃ for 2-3 hours (h).
3. The method according to claim 1 or 2, wherein in S01, the oxidizing atmosphere is a dry oxygen atmosphere.
4. The method according to any one of claims 1 to 3, wherein in S01, the oxidizing atmosphere further comprises a chlorine-containing additive, preferably an active chlorine content of 0.4-1.2% by weight of the oxygen content.
5. The method according to any one of claims 1 to 4, wherein in S02, the two-stage annealing comprises annealing at 1000-1050 ℃ or 1020-1080 ℃ and annealing at 425-455 ℃; preferably, the annealing at 1000-1050 ℃ for 9-11 hours (h) or 1020-1080 ℃ for 3-6 hours (h) and the annealing at 425-455 ℃ for 1-7 hours (h) are included.
6. The method according to any one of claims 1 to 5, wherein in S02, the temperature and duration of the two-stage annealing depend on the density of the micro-defects after the substrate is annealed in the oxidizing ambient.
7. The method according to any of claims 1 to 6, wherein in S02 the density of micro-defects after annealing of the substrate in an oxidizing ambient is < 2 x 10 4 cm -3 Firstly, annealing at 1000-1050 ℃ for 9-11 hours (h), and then annealing at 425-455 ℃ for 5-7 hours (h);
2×10 4 cm -3 the density of micro defects after the substrate is annealed in an oxidizing environment is less than or equal to 2 multiplied by 10 6 cm -3 Firstly, annealing at 1020-1080 ℃ for 3-6 hours (h), and then annealing at 425-455 ℃ for 5-7 hours (h);
2×10 6 cm -3 the density of micro defects after the substrate is annealed in an oxidizing environment is less than or equal to 2 multiplied by 10 7 cm -3 In the method, annealing is carried out at 1020-1080 ℃ for 3-6 hours (h), and then annealing is carried out at 425-455 ℃ for 1-3 hours (h).
8. The method according to any one of claims 1 to 7, further comprising a step of etching after said S01 and determining a density of an etched pattern.
9. The method according to any one of claims 1 to 8, wherein in the etching step, the silicon wafer is etched in a composition of 3 to 5 parts by weight of hydrogen fluoride, 45 to 50 parts by weight of chromic anhydride, and 45 to 50 parts by weight of water for 1.2 to 1.6 hours (h).
10. The method according to any one of claims 1 to 9, wherein the step of determining the density of the etched pattern comprises performing a metallographic examination of the surface of the substrate under an optical microscope and calculating the density of the detected etched pattern.
CN202210781569.0A 2022-07-04 2022-07-04 Method for producing semiconductor structure with getter Pending CN115241059A (en)

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Application Number Priority Date Filing Date Title
CN202210781569.0A CN115241059A (en) 2022-07-04 2022-07-04 Method for producing semiconductor structure with getter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210781569.0A CN115241059A (en) 2022-07-04 2022-07-04 Method for producing semiconductor structure with getter

Publications (1)

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CN115241059A true CN115241059A (en) 2022-10-25

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