CN115224924A - On-chip soft start circuit of switching power supply and control method - Google Patents
On-chip soft start circuit of switching power supply and control method Download PDFInfo
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- CN115224924A CN115224924A CN202210601618.8A CN202210601618A CN115224924A CN 115224924 A CN115224924 A CN 115224924A CN 202210601618 A CN202210601618 A CN 202210601618A CN 115224924 A CN115224924 A CN 115224924A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/36—Means for starting or stopping converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0012—Control circuits using digital or numerical techniques
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0025—Arrangements for modifying reference values, feedback values or error values in the control loop of a converter
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0038—Circuits or arrangements for suppressing, e.g. by masking incorrect turn-on or turn-off signals, e.g. due to current spikes in current mode control
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention discloses an on-chip soft start circuit of a switching power supply and a control method thereof, wherein the circuit comprises a current soft start control part, a voltage soft start control part, an error amplifier and a PWM (pulse width modulation) comparator; wherein, the soft start control part of electric current includes: the device comprises an M-bit counter, a decoder, a multi-way switch, a comparator A2, a two-way switch S2, a PMOS (P-channel metal oxide semiconductor) tube M1 AND an AND gate AND1; the voltage soft start control part comprises: the circuit comprises a buffer, resistors R1 and R2, a low-pass filter, a variable current source Iref, a comparator A1, an N-bit counter and a two-way switch S1. The control method divides the soft start stage into a current soft start stage and a voltage soft start stage, and compared with the soft start circuit in the prior art, the control method realizes that the overshoot and the surge current of the output voltage are considered at the same time, and shortens the soft start time.
Description
Technical Field
The invention relates to the field of integrated circuit design, in particular to an on-chip soft start circuit of a switching power supply and a control method.
Background
The switching power supply has the characteristics of high conversion efficiency, wide input and output range, small volume, stable work and the like, and is widely applied to various communication, industrial control and consumer electronic products. The switching power supply is used as an intermediate link of the power supply equipment and the electric equipment, the starting process needs to simultaneously give consideration to the friendliness of the power supply equipment and the electric equipment, namely, a lithium battery and the like which provide electric energy cannot be burnt due to the generation of large surge current, and load overvoltage damage cannot be caused due to the generation of large overshoot voltage. Therefore, during the starting process of the switching power supply, a special soft start circuit needs to be designed to simultaneously suppress surge current and voltage overshoot.
As shown in fig. 1, in a start-up stage of a switching power supply, a voltage generated by charging a capacitor C1 with a small current Ichg instead of a VBG voltage and a VFB voltage generates an error voltage at an output COMP point of EA, so as to limit a peak value of an inductor current and slowly increase an output voltage. Whether the conventional soft start circuit can suppress the surge current and the output voltage overshoot depends on the rising speed of the voltage on the capacitor C1. The VFB point voltage is pulled to rise slowly only if the rate of rise is slow enough to suppress output voltage overshoot. Likewise, the COMP point voltage can be adjusted to a lower value to suppress the inrush current only if the rise speed is slow enough.
In order to make the voltage on the capacitor C1 rise slowly enough (in the order of ms), the charging current Ichg needs to be of the order of nA or the capacitor C1 needs to be of the order of nF. The nA-level small current is easily influenced by the process change of the integrated circuit, and easily interferes the soft start circuit, so that the soft start circuit is abnormal when being started. For nF-level capacitances, it is obviously difficult to integrate inside the chip. Therefore, the C1 capacitor requires an external chip for reliable suppression of voltage overshoot and surge current.
In the article of 'electronic device' volume 31, phase 2, 'a novel soft start circuit design of a DC-DC switching power supply', a novel soft start circuit based on an MOS (metal oxide semiconductor) process is provided, and the fast and stable soft start of output voltage is realized by utilizing the peak current limiting and digital soft start technology of current mode DC-DC. However, the inductor current during start-up is not controlled. From the data provided in this document, the inductor current jumps directly to around 10A at the beginning of start-up, and the inrush current is not completely suppressed.
The patent number is 200810046622, titled as a soft start circuit of a pulse width modulation DC switch power supply, and discloses a soft start circuit of a pulse width modulation DC-DC switch power supply, which controls the duty ratio step-type change by limiting the peak current to change from small to large in stages, so that the output voltage slowly rises in stages, and the surge current in the starting process can be effectively avoided. However, this method is actually affected by the size of the external output capacitor, and when the output capacitor is small, there is a possibility that the output voltage overshoots.
In the prior art, only the output voltage overshoot can be effectively controlled, or only the surge current can be effectively inhibited, and the output voltage overshoot and the surge current cannot be considered at the same time.
Disclosure of Invention
The invention aims to provide an on-chip soft start circuit of a switching power supply and a control method thereof, so as to simultaneously inhibit the problems of output voltage overshoot and surge current in the starting process of the switching power supply.
In order to solve the above technical problem, the present invention provides an on-chip soft start circuit of a switching power supply, including: the device comprises a current soft start control part, a voltage soft start control part, an error amplifier and a PWM comparator;
wherein, the current soft start control part includes: the device comprises an M-bit counter, a decoder, a multi-way switch, a comparator A2, a two-way switch S2, a PMOS (P-channel metal oxide semiconductor) tube M1 AND an AND gate AND1; the voltage soft start control part comprises: the circuit comprises a buffer, resistors R1 and R2, a low-pass filter, a variable current source Iref, a comparator A1, an N-bit counter and a two-way switch S1.
Further, the enable signal EN and the clock signal CLK enter the current soft-start control section and the voltage soft-start control section at the same time, and the enable signal EN and the clock signal CLK are both connected to the M-bit counter and the N-bit counter, respectively.
Further, in the current soft start control section, an output terminal of the M-bit counter is connected to an input terminal of the decoder; the output end of the decoder outputs a signal with a control input of Vref<0> ~ Vref<
-1>The multi-way switch of (2); the positive input end of the comparator A2 is connected with a voltage signal VSense obtained by current sampling, the negative input end of the comparator A2 is connected with an output signal of the output end of the multi-way switch, and the output end of the comparator A2 outputs a PeakLimit signal; a first input end and a second input end of the two-way switch S2 are respectively connected with clamping signals VclampH and VclampL, an output end is connected with a grid electrode of the PMOS tube M1, and a drain electrode of the PMOS tube M1 is connected with an output end of the error amplifier and a negative input end of the PWM comparator; the second input end of the AND gate AND1 is connected with the output end of the PWM comparison, AND the output end outputs a PWM signal; the negative input of the error amplifier is connected to the VFB signal.
Further, in the voltage soft start control part, the band-gap reference VBG is connected to the positive input end of the buffer and the first input end of the two-way switch S1 at the same time, and the output end of the buffer is connected to the negative input end of the buffer and one end of the R1; the other end of the R1 is connected with one end of the R2 and one end of the low-pass filter; the second input end of the two-way switch S1 is connected with the output end of the low-pass filter, and the output end of the two-way switch S1 is connected with the positive input end of the error amplifier; the other end of R2 is connected with a variable current source Iref connected to the ground and the negative input end of the comparator A1; the positive input end of the comparator A1 is connected to the VFB signal, AND the output end of the comparator A1 is simultaneously connected with the third input end of the double-way switch S2, the first input end of the AND gate AND1 AND the input end of the N-bit counter; the first output end of the N-bit counter outputs Qb 0-Qbn signals to the controllable current source Iref, and the second output end generates SS _ Finished control signals to the third input end of the double-way switch S1.
The invention also provides an on-chip soft start control method of the switching power supply, which comprises the following steps:
in the current soft start stage, the output voltage is quickly increased to be close to a set voltage soft start initial value through the current soft start;
a voltage soft start stage, wherein the output voltage slowly rises to a final target voltage value through the voltage soft start stage and overshoot is avoided;
after the soft start is finished, the positive input of the error amplifier is switched back to the VBG through the two-way switch S1, the influence of the offset voltage of the buffer on the accuracy of the output voltage of the system is eliminated, and meanwhile, the comparator A2 is also switched back to the normal highest current-limiting reference voltage value, so that the system returns to the maximum loading capacity again.
Further, the method comprises the following steps:
enabling the chip to be powered on;
entering a current soft start stage, selecting a VBG _ SS signal at the positive input end of an error amplifier, switching the output COMP of the error amplifier to preset VclampL in a high clamping mode, shielding the output of a PWM (pulse width modulation) comparator, gradually increasing a peak current limiting value along with the time, and setting an inductive current by a peak current limiting comparator A2 at the stage;
when the VFB voltage rises to enable the comparator A1 to turn over, the voltage enters a voltage soft start stage, the VBG _ SS signal is selected by the positive input end of the error amplifier and is gradually increased under the control of the N-bit counter along with time, the COMP high-clamping output of the error amplifier is switched to the preset VclamH, the output of the PWM comparator is released, and the peak current limiting value is the maximum value set in the current soft start stage;
and the N-bit counter finishes counting, generates a soft start ending mark signal SS _ Finished, switches the positive input end of the error amplifier to VBG voltage, switches the peak current limiting value to the current limiting value normally set by the system, and ends the soft start.
Further, for the current soft start phase, the CLK signal is generated by the M-bit counter and decoder in sequence
The control signal controls the multi-way switch to select different peak current limiting reference signals Vref<0> ~ Vref<
-1>So that the peak value of the inductor current is gradually increased.
Further, in a voltage soft start stage, the comparator A1 is used for judging the output voltage, and when the VFB voltage rises to a voltage soft start preset initial value, the comparator A1 outputs a control signal V _ SoftStart to start the N-bit counter to work and enter the voltage soft start; CLK signal passing through N-bit meterGenerating N-bit control signals Qb 0-Qbn after the counter
Combining the states to convert the current of variable current source Iref from Iref 0 Gradually decreasing to 0, the voltage VBG _ SS at the positive input terminal of the error amplifier rises from an initial value k1 VBG to a voltage equal to VBG, where k<1。
Further, in the current soft start stage, the output high clamping voltage of the error amplifier is set at a lower value and the output of the PWM comparator is shielded, so that the constant voltage loop of the switching power supply works in an open loop state, and the peak value of the inductive current is controlled by the comparator A2 only to gradually increase the current limiting value.
Further, after entering a voltage soft start stage, the output high clamping voltage of the error amplifier is switched to a higher value, and the output of the PWM comparator is not shielded any more, so that the constant voltage loop of the switching power supply operates in a closed loop state, and the peak value of the inductor current is controlled by the PWM comparator and the comparator A2 together.
Compared with the prior art, the invention at least has the following beneficial effects:
according to the technical scheme, a soft start stage is divided into a current soft start stage and a voltage soft start stage, and in the current soft start stage, a multi-way switch is controlled by a control signal to select different peak current limiting signals, so that the peak current of an inductor is gradually increased, and the output voltage is quickly increased to be close to a set voltage soft start initial value; in the voltage soft start phase, the reference voltage is controlled to slowly rise from a lower initial value to a set value, so that the output voltage is controlled to slowly rise to a final target voltage value and overshoot does not occur. Compared with a soft start circuit in the prior art, the soft start circuit realizes that output voltage overshoot and surge current are considered simultaneously, and shortens soft start time.
Drawings
FIG. 1 is a schematic circuit diagram of a soft start circuit in the prior art;
fig. 2 is a schematic circuit diagram of an on-chip soft start circuit of a switching power supply according to an embodiment of the invention;
FIG. 3 is a flowchart illustrating a method for controlling an on-chip soft start of a switching power supply according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating the outputs of an M-bit counter and decoder according to an embodiment of the present invention;
FIG. 5 is a schematic diagram illustrating the VBG _ SS voltage variation with time according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a starting process of the switching power supply according to an embodiment of the invention.
Detailed Description
The on-chip soft start circuit and the control method of the switching power supply of the present invention will be described in more detail with reference to the schematic drawings, in which preferred embodiments of the present invention are shown, and it is to be understood that those skilled in the art can modify the present invention described herein while still achieving the advantageous effects of the present invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
The invention is more particularly described in the following paragraphs with reference to the accompanying drawings by way of example. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is provided for the purpose of facilitating and clearly illustrating embodiments of the present invention.
Example 1
The embodiment 1 provides an on-chip soft start circuit of a switching power supply, and the embodiment described below with reference to the drawings is exemplary only and is not to be construed as limiting the present invention. Referring to fig. 2, the on-chip soft start circuit of the switching power supply includes:
the device comprises a current soft start control part, a voltage soft start control part, an error amplifier and a PWM comparator;
wherein, the current soft start control part includes: the device comprises an M-bit counter, a decoder, a multi-way switch, a comparator A2, a two-way switch S2, a PMOS (P-channel metal oxide semiconductor) tube M1 AND an AND gate AND1; the voltage soft start control section includes: the circuit comprises a buffer, resistors R1 and R2, a low-pass filter, a variable current source Iref, a comparator A1, an N-bit counter and a two-way switch S1.
Therefore, the on-chip soft start circuit of the switching power supply divides the soft start stage into a current soft start stage and a voltage soft start stage, realizes the simultaneous consideration of output voltage overshoot and surge current, and shortens the soft start time.
Example 2
This embodiment 2 can be further improved on the basis of embodiment 1, and the description of the same or similar parts is omitted. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention and are not to be construed as limiting the present invention. Specifically, as shown in fig. 2, the present embodiment includes:
the enable signal EN and the clock signal CLK enter the current soft start control part and the voltage soft start control part at the same time and are respectively connected to the M-bit counter and the N-bit counter.
The output end of the M-bit counter is connected to the input end of the decoder; the output signal of the decoder has Vref as control input<0> ~ Vref<
-1>The multi-way switch of (2); the positive input end of the comparator A2 is connected with a voltage signal VSense obtained by current sampling, the negative input end of the comparator A2 is connected with an output signal of the output end of the multi-way switch, and the output end of the comparator A2 outputs a PeakLimit signal; the first input end and the second input end of the double-path switch S2 are respectively connected with clamping signals VclamH and VclamL, the output end of the double-path switch S is connected with the grid electrode of a PMOS tube M1, and the drain electrode of the PMOS tube M1 is connected with the output end of the error amplifier and the negative input end of the PWM comparator; the positive input end of the PWM comparator is connected with the VSlope signal, the second input end of the AND gate AND1 is connected with the output end of the PWM comparator, AND the output end of the AND gate AND1 outputs the PWM signal; the negative input of the error amplifier is connected to the VFB signal.
The band-gap reference VBG is connected to the positive input end of the buffer and the first input end a1 of the two-way switch S1 at the same time, and the output end of the buffer is connected to the negative input end of the buffer and one end of the R1; the other end of the R1 is connected with one end of the R2 and one end of the low-pass filter; the second input end of the double-circuit switch S1 is connected with the output end of the low-pass filter, and the output end of the double-circuit switch S1 is connected with the positive input end of the error amplifier; the other end of R2 is connected with a variable current source Iref connected to the ground and the negative input end of the comparator A1; the positive input end of the comparator A1 is connected to the VFB signal, AND the output end of the comparator A1 is simultaneously connected with the third input end of the double-way switch S2, the first input end of the AND gate AND1 AND the input end of the N-bit counter; the first output end of the N-bit counter outputs Qb 0-Qbn signals to the controllable current source Iref, and the second output end generates SS _ Finished control signals to the third input end of the double-way switch S1.
In one example, the low pass filter may be composed of R3 and C1.
Example 3
Embodiment 3 may be further implemented on the basis of embodiment 1 or embodiment 2, and may not be limited to the on-chip soft start circuit of the switching power supply described in the present invention. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention and are not to be construed as limiting the present invention. Specifically, the present embodiment includes:
an on-chip soft start control method of a switching power supply comprises the following steps:
in the current soft start stage, the output voltage is quickly increased to be close to a set voltage soft start initial value through current soft start;
a voltage soft start stage, wherein the output voltage slowly rises to a final target voltage value through the voltage soft start stage and overshoot does not occur;
after the soft start is over, the error amplifier input is switched back to VBG, and comparator A2 is also switched back to the normal maximum current limit reference voltage value.
Through the soft start scheme, the current limiting value is gradually increased in the current soft start stage, so that the inductive current presents a process of gradually increasing from small to large, the method is friendly to a preceding stage power supply system, and cannot be damaged due to suddenly rising current. In addition, the current soft start can enable the output voltage to reach k1 times of the normal output in a short time (generally, k1 can be set to be 0.8-0.9), and the start time is saved as much as possible. During the voltage start-up phase, overshoot of the output voltage can be avoided by slowly pulling the output voltage VFB up.
Example 4
This embodiment 4 may be further improved on the basis of embodiment 3, and the description thereof will be omitted for the same or similar parts. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention. Specifically, referring to fig. 3, the present embodiment includes:
s1, enabling the chip to be powered on.
In S1, the bias voltage module and the bias current module (not shown) operate normally, and the clock module (not shown) generating CLK operates normally, thereby obtaining the enable signal EN and the clock signal CLK. The enable signal EN is asserted while disabling the current soft start control portion and the voltage soft start control portion. Since the N-bit counter of the soft start voltage control part is also controlled by the V _ SoftStart signal output by the comparator A1, and VFB does not rise above VBG-Iref0 (R1 + R2), the V _ SoftStart signal is not valid, and the soft start voltage control circuit does not operate.
S2, entering a current soft start stage, selecting a VBG _ SS signal at the positive input end of the error amplifier, switching the output COMP of the error amplifier to a preset VclampL in a high clamping mode, shielding the output of the PWM comparator, gradually increasing a peak current limiting value along with the time, and completely setting the inductive current by the peak current limiting comparator at the stage.
In S2, after the bias module and the clock module work normally, entering a current soft start stage: the CLK signal is generated sequentially by the M-bit counter and decoder
The control signal controls the multi-way switch to select different peak current limiting reference signals Vref<0> ~ Vref<
-1>So that the peak value of the inductor current is gradually increased.
Fig. 4 is a schematic diagram illustrating the outputs of the M-bit counter and decoder according to an embodiment of the present invention.
For example, selecting the
A Vref<0> ~ Vref<
-1>The voltage signal of (A2) is used as a reference voltage of the comparator (A2) and compared with a voltage signal (VSense) representing the inductor current obtained by current sampling, when the VSense signal is greater than the reference voltage signal of the negative input end of the comparator (A2), the comparator (A2) outputs high level to control the turn-off of a charging tube (not shown) of the switching power supply, therefore, the comparator (A2) determines the peak current of the inductor. Vref (reference sign)<0> ~ Vref<
1>Is a reference voltage signal that gradually increases with time, and therefore, the inductor peak current also gradually increases.
In the current soft start stage, the positive input terminal of the error amplifier selects the VBG _ SS signal (initial value is set to k1 × VBG, where k1< 1), and the output of the error amplifier COMP is switched to a lower preset value VclampL in a high-clamp manner. The main consideration is that since the positive input of the error amplifier is terminated at VBG _ SS, which is always greater than the VFB voltage during the current soft start phase, the voltage at the output COMP of the error amplifier will be pushed to a high clamp value, vclampH + Vth, which is usually a relatively high value. When the current soft start is switched to the voltage soft start, the output voltage of the error amplifier needs to be adjusted to a lower value from VclamH + Vth, and is limited by the slew rate of the error amplifier and the influence of the loop bandwidth of the switching power supply, the adjustment speed is slower, and therefore, a larger surge current can be generated in the switching process. In order to ensure smooth switching of current soft start and voltage soft start, namely no surge current is generated in the switching process, the output COMP high-clamping reference voltage of the error amplifier is switched from VclampH + Vth to VclampL + Vth, the voltage at the COMP point is equal to VclampL + Vth, the Vth is threshold voltage, and the VclampL + Vth is a lower value, so that the adjusting stroke of the error amplifier can be shortened when the voltage soft start is switched, and the response can be completed more quickly. And the peak value of the inductive current determined by the value is possibly smaller than the maximum current peak value set by the current soft start, so that the difference of different load capacitances of the switching power supply system is obvious, and therefore, the PWM signal is shielded in the current soft start stage, namely, a constant voltage loop of the switching power supply system is disconnected, and the current loop limited by the peak value works independently. Therefore, after the switching is carried out to the voltage soft start stage, the voltage at the COMP point gradually rises to the value required by the system loop from VclampL + Vth, and the surge current in the switching process is effectively avoided.
And S3, when the VFB voltage rises to enable the comparator A1 to turn over, the voltage soft start stage is started, the VBG _ SS signal is selected at the positive input end of the error amplifier and is gradually increased under the control of the N-bit counter along with the time, the output COMP of the error amplifier is switched to be the preset VclampH in a high clamping mode, the output of the PWM comparator is released, and the peak current limiting value is the maximum value set in the current soft start stage.
In S3, when the voltage of VFB rises to make the comparator A1 overturn, for example, when the voltage of VFB rises to VBG-Iref 0 * And (R1 + R2) or above, entering a voltage soft start stage. In the voltage soft start stage, the output voltage is judged through the comparator A1, and when the voltage of the VFB rises to a preset initial value of the voltage soft start, the comparator A1 outputs a control signal V _ SoftStart to start an N-bit counter to work and enter the voltage soft start; the CLK signal passes through the N-bit counter to generate N-bit control signals Qb 0-Qbn
A combination of states, gradually reducing the current of the variable current source Iref from Iref0 to 0, increasing the voltage VBG _ SS at the positive input terminal of the error amplifier from an initial value k1 VBG to a voltage equal to VBG, wherein k is<1。
The peak current limiting reference voltage can enter the voltage soft start phase at any value between Vref <0> -Vref <2M-1>, depending on the load size, but the maximum value of the peak current is set by the reference voltage Vref <2M-1 >. The method has the advantage that the time of the current soft start phase can be adaptively adjusted according to different loads, so that the total soft start time can be shortened when the load is smaller.
The positive input of the error amplifier selects a VBG _ SS voltage signal, which is a voltage smaller than VBG generated by the variable current source Iref on the resistors R1 and R2 after the VBG voltage passes through the buffer, and the initial value is k1 × VBG.
Referring to FIG. 5, before the constant voltage loop starts to work, the current in the variable current source Iref is initially Iref 0 The output voltage is equal to VBG regardless of the offset voltage of the buffer. The initial voltage of VBG _ SS is therefore:
VBG_SS 0 =VBG-Iref 0 *R1 （1）
for variable current sources, this is generally achieved by a V-I converter circuit, the value of which is Iref 0 = VBG/R0, and substitution into (1) yields:
VBG_SS 0 =VBG-Iref 0 *R1= VBG*(1-R1/R0)= VBG*k1 (2)
where k1= (1-R1/R0), which is a constant less than 1, the ratio of R1 and R0 may be adjusted to set the initial voltage value in the constant voltage stage in the design.
From equation (1), it can be seen that VBG _ SS is completely equal to VBG when the variable current source Iref decreases to 0. Therefore, as long as the variable current source is controlled to slowly step down to 0 over time, a slow gradual increase in VBG _ SS over time to the VBG voltage is obtained. Generating all 0 to all 1 2 by N-bit counter N Seed combinations, i.e. the number of steps in which VBG _ SS changes from VBG x k to VBG is 2 N . The voltage increment per step can be found to be:
△V= VBG*(1－k1)/2 N (3)
unlike the current soft start time, the voltage soft start time is fixed and depends on the number of steps in the period Tclk sum of the clock CLK, which is expressed as follows:
T v_ss = 2 N *Tclk (4)
in the voltage soft start stage, the output COMP of the error amplifier is switched to the preset VclampH in a high clamping mode, the output of the PWM comparator is released, and the peak current limiting value is the maximum value set in the current soft start stage. The VFB voltage is pulled by the VBG _ SS voltage to slowly increase so that no output voltage overshoot is produced.
In the stage of current soft start, the output high clamping voltage of the error amplifier is set at a lower value and the output of the PWM comparator is shielded, so that the constant voltage loop of the switching power supply works in an open loop state, and the peak value of the inductive current is controlled by the comparator A2 only to gradually increase the current limiting value.
After entering a voltage soft start stage, the output high clamping voltage of the error amplifier is switched to a higher value, and the output of the PWM comparator is not shielded any more, so that the constant voltage loop of the switching power supply works in a closed loop state, and the peak value of the inductive current is controlled by the PWM comparator and the comparator A2 together.
And S4, finishing counting by the N-bit counter, generating a soft start ending mark signal SS _ Finished, switching the positive input end of the error amplifier to VBG voltage, switching the peak current limiting value to a current limiting value normally set by the system, and ending the soft start.
Before the N-bit counter counts full output 1, the SS _ Finished signal is at low level, the two-way selector switch 1 is controlled to select the signal of VBG _ SS after being filtered by the low-pass filter formed by R3 and C1 to enter the positive input end of the error amplifier to control the traction VFB voltage to rise slowly. When N is the full output total 1 of the counter, the SS _ Finished signal is in a high level, and the double-circuit selection switch 1 is controlled to select the VBG signal, so that the influence of the offset voltage of the buffer on the accuracy of the output voltage can be eliminated.
When SS _ Finished is 1, the end of soft start is marked, and the signal can control the multi-way switch to switch the peak current-limiting reference voltage signal back to the current-limiting value of normal operation of the system, so that the normal load carrying capacity of the system is ensured.
Referring to fig. 6, from the result of the start-up process, the peak value of the inductor current undergoes three times of gradually rising processes in the current start-up phase, which corresponds to three times of gradually rising slopes of the output voltage in the current soft start-up phase. And entering a voltage soft start stage, intervening a constant voltage loop, and having a loop regulation process for a period of time in the early stage, wherein the inductive current tends to be stable and the output voltage also slowly rises with a small slope. As mentioned above, the scheme of the invention can completely control the inductive current and the output voltage in the whole starting stage, and the condition of surge current and output voltage overshoot can not occur.
Compared with the prior art, the invention at least has the following beneficial effects:
according to the technical scheme, a soft start stage is divided into a current soft start stage and a voltage soft start stage, and in the current soft start stage, a multi-way switch is controlled by a control signal to select different peak current limiting signals, so that the peak current of an inductor is gradually increased, and the output voltage is quickly increased to be close to a set voltage soft start initial value; in the voltage soft start phase, the reference voltage is controlled to slowly rise from a lower initial value to a set value, so that the output voltage is controlled to slowly rise to a final target voltage value and overshoot does not occur. Compared with a soft start circuit in the prior art, the soft start circuit realizes that the overshoot and the surge current of the output voltage are considered at the same time, and shortens the soft start time.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. An on-chip soft start circuit of a switching power supply is characterized by comprising a current soft start control part, a voltage soft start control part, an error amplifier and a PWM comparator;
wherein, the soft start control part of electric current includes: the device comprises an M-bit counter, a decoder, a multi-way switch, a comparator A2, a two-way switch S2, a PMOS (P-channel metal oxide semiconductor) tube M1 AND an AND gate AND1; the voltage soft start control part comprises: the circuit comprises a buffer, resistors R1 and R2, a low-pass filter, a variable current source Iref, a comparator A1, an N-bit counter and a two-way switch S1.
2. The on-chip soft-start circuit of the switching power supply as claimed in claim 1, wherein the enable signal EN and the clock signal CLK enter the current soft-start control section and the voltage soft-start control section at the same time, and the enable signal EN and the clock signal CLK are respectively connected to the M-bit counter and the N-bit counter.
3. The on-chip soft-start circuit of a switching power supply according to claim 2, wherein in the current soft-start control section, an output terminal of the M-bit counter is connected to an input terminal of the decoder; the output signal of the decoder has Vref as control input<0> ~ Vref<
-1>The multi-way switch of (2); the positive input end of the comparator A2 is connected with a voltage signal VSense obtained by current sampling, the negative input end of the comparator A2 is connected with an output signal of the output end of the multi-way switch, and the output end of the comparator A2 outputs a PeakLimit signal; the first input end and the second input end of the double-path switch S2 are respectively connected with clamping signals VclamH and VclamL, the output end of the double-path switch S is connected with the grid electrode of a PMOS tube M1, and the drain electrode of the PMOS tube M1 is connected with the output end of the error amplifier and the negative input end of the PWM comparator; the second input end of the AND gate AND1 is connected with the output end of the PWM comparison, AND the output end outputs a PWM signal; the negative input of the error amplifier is connected to the VFB signal.
4. The on-chip soft-start circuit of the switching power supply according to claim 2, wherein in the voltage soft-start control section, the bandgap reference VBG is connected to both the positive input terminal of the buffer and the first input terminal of the two-way switch S1, and the output terminal of the buffer is connected to the negative input terminal thereof and one terminal of R1; the other end of the R1 is connected with one end of the R2 and one end of the low-pass filter; the second input end of the two-way switch S1 is connected with the output end of the low-pass filter, and the output end of the two-way switch S1 is connected with the positive input end of the error amplifier; the other end of R2 is connected with a variable current source Iref connected to the ground and the negative input end of the comparator A1; the positive input end of the comparator A1 is connected to the VFB signal, AND the output end of the comparator A1 is simultaneously connected with the third input end of the double-way switch S2, the first input end of the AND gate AND1 AND the input end of the N-bit counter; the first output end of the N-bit counter outputs Qb 0-Qbn signals to the controllable current source Iref, and the second output end generates SS _ Finished control signals to the third input end of the double-way switch S1.
5. An on-chip soft start control method of a switching power supply is characterized by comprising the following steps:
in the current soft start stage, the output voltage is quickly increased to be close to a set voltage soft start initial value through the current soft start;
a voltage soft start stage, wherein the output voltage slowly rises to a final target voltage value through the voltage soft start stage and overshoot does not occur;
after the soft start is over, the positive input of the error amplifier is switched back to VBG, and at the same time, comparator A2 is also switched back to the normal maximum current limit reference voltage value.
6. The on-chip soft-start control method of a switching power supply according to claim 5, comprising:
enabling the chip to be powered on;
entering a current soft start stage, selecting a VBG _ SS signal at the positive input end of an error amplifier, switching the output COMP of the error amplifier to a preset VclampL in a high clamping mode, shielding the output of a PWM comparator, gradually increasing a peak current limiting value along with the time, and setting an inductive current by a peak current limiting comparator A2 at the stage;
when the VFB voltage rises to enable the comparator A1 to turn over, the voltage enters a voltage soft start stage, the VBG _ SS signal is selected by the positive input end of the error amplifier and is gradually increased under the control of the N-bit counter along with time, the COMP high-clamping output of the error amplifier is switched to the preset VclamH, the output of the PWM comparator is released, and the peak current limiting value is the maximum value set in the current soft start stage;
and the N-bit counter finishes counting, generates a soft start ending mark signal SS _ Finished, switches the positive input end of the error amplifier to VBG voltage, switches the peak current limiting value to the current limiting value normally set by the system, and ends the soft start.
7. The on-chip soft-start control method of the switching power supply as claimed in claim 6, wherein for the current soft-start phase, the CLK signal is generated sequentially after being acted on by the M-bit counter and the decoder
The control signal controls the multi-way switch to select different peak current-limiting reference signals Vref<0> ~ Vref<
-1>So that the peak value of the inductor current is gradually increased.
8. The on-chip soft-start control method of the switching power supply according to claim 6, wherein for the voltage soft-start stage, the comparator A1 determines the output voltage, and when the VFB voltage rises to the preset initial value of the voltage soft-start, the comparator A1 outputs a control signal V _ SoftStart to start an N-bit counter and enter the voltage soft-start; the CLK signal passes through the N-bit counter to generate N-bit control signals Qb 0-Qbn
A combination of states for changing the current of the variable current source Iref from Iref 0 Gradually decreasing to 0, the voltage VBG _ SS at the positive input terminal of the error amplifier rises from an initial value k1 VBG to a voltage equal to VBG, where k<1。
9. The on-chip soft-start control method of switching power supply according to claim 6, wherein the output high clamp voltage of the error amplifier is set at a lower value and the output of the PWM comparator is masked in the current soft-start stage, so that the constant voltage loop of the switching power supply operates in an open loop state, and the peak value of the inductor current is controlled by the comparator A2 only to gradually increase the current limit value.
10. The on-chip soft-start control method of the switching power supply as claimed in claim 6, wherein after entering the voltage soft-start stage, the output high clamp voltage of the error amplifier is switched to a higher value, and the output of the PWM comparator is not shielded, so that the constant voltage loop of the switching power supply operates in a closed loop state, and the peak value of the inductor current is controlled by the PWM comparator and the comparator A2.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117559376A (en) * | 2024-01-12 | 2024-02-13 | 苏州四方杰芯电子科技有限公司 | Peak voltage control circuit and software control system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117559376A (en) * | 2024-01-12 | 2024-02-13 | 苏州四方杰芯电子科技有限公司 | Peak voltage control circuit and software control system |
| CN117559376B (en) * | 2024-01-12 | 2024-03-22 | 苏州四方杰芯电子科技有限公司 | Peak voltage control circuit and software control method |
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