CN115224662A

CN115224662A - Over-temperature protection circuit of functional circuit and power supply chip

Info

Publication number: CN115224662A
Application number: CN202210937351.XA
Authority: CN
Inventors: 王子威; 尚宇
Original assignee: Longxin Zhongke Nanjing Technology Co ltd
Current assignee: Longxin Zhongke Nanjing Technology Co ltd
Priority date: 2022-08-05
Filing date: 2022-08-05
Publication date: 2022-10-21

Abstract

The embodiment of the invention provides an over-temperature protection circuit of a functional circuit and a power supply chip, and relates to the technical field of circuits. In the embodiment of the invention, when the working temperature of the functional circuit is increased to a higher temperature and decreased to a lower temperature, the gate end voltage of the input geminate transistor of the fully differential amplifier is greatly changed, so that the temperature hysteresis circuit outputs different high and low levels, thereby triggering the functional circuit to be turned off or turned on.

Description

Over-temperature protection circuit of functional circuit and power supply chip

Technical Field

The invention relates to the technical field of circuits, in particular to an over-temperature protection circuit of a functional circuit and a power supply chip.

Background

The over-temperature protection function of the circuit is to control the working state of the circuit by detecting the working temperature of the circuit. During the operation of the circuit, heat loss is inevitably generated, so that the temperature of the circuit is increased, and if the heat dissipation effect of the circuit is poor, the temperature is increased until the circuit is burnt out. The over-temperature protection function is that the circuit is closed when the temperature of the circuit exceeds the designated temperature during working, so that the circuit is prevented from being burnt out due to over-high temperature, and the circuit is restarted to restart after the circuit is cooled down due to heat dissipation.

In practical application, the over-temperature protection function can detect temperature through the temperature sensitive device, however, when a circuit is manufactured, the over-temperature protection function needs to be integrated inside the circuit, the number of selectable temperature sensitive devices is very small, and many of the selectable temperature sensitive devices need special process support, so that the number of over-temperature protection circuits applicable to the common process is small.

The range of temperature hysteresis of the conventional overtemperature protection circuit is very limited, so that the protection effect of the overtemperature protection circuit is poor.

Disclosure of Invention

In view of the above problems, embodiments of the present invention are provided to provide an over-temperature protection circuit of a functional circuit and a power chip, so as to solve the problem that the current over-temperature protection circuit has a limited temperature range, which results in poor over-temperature protection effect.

In order to solve the above problems, an embodiment of the present invention discloses an over-temperature protection circuit for a functional circuit, including a temperature hysteresis circuit and a hysteresis enhancement circuit, where the hysteresis enhancement circuit is connected to at least one functional circuit respectively;

the temperature hysteresis circuit is used for detecting and controlling the temperature of the functional circuit and comprises a triode and a fully differential amplifier; the emitter electrode of the triode outputs an emitter voltage to the fully differential amplifier; the fully differential amplifier outputs a first signal to the hysteresis enhancement circuit based on the emitter voltage, and an externally input reference voltage and an output common-mode reference voltage;

the hysteresis enhancement circuit comprises a Schmitt trigger circuit, and the Schmitt trigger circuit enhances and shapes the first signal and then outputs a second signal to the functional circuit;

wherein the emitter voltage is inversely related to the operating temperature of the functional circuit; the voltage corresponding to the first signal is positively correlated with the emitter voltage; the voltage corresponding to the second signal is in negative correlation with the voltage corresponding to the first signal so as to control the functional circuit to be closed or opened.

Optionally, the fully differential amplifier comprises a main operational amplifier circuit and a common-mode feedback amplifier;

the main operational amplifier circuit comprises a first PMOS transistor, a second PMOS transistor, a first resistor, a second resistor, a first NMOS transistor and a second NMOS transistor; the first NMOS transistor and the first PMOS transistor are respectively connected with the positive end of the common mode feedback amplifier through the first resistor, and the second NMOS transistor and the second PMOS transistor are respectively connected with the positive end of the common mode feedback amplifier through the second resistor so as to send output common mode voltage to the common mode feedback amplifier;

and the common mode feedback amplifier stabilizes the output common mode voltage according to the output common mode reference voltage and outputs the obtained stabilized voltage to the first NMOS transistor and the second NMOS transistor respectively.

Optionally, the first PMOS transistor is configured to turn on when the operating temperature of the functional circuit increases to a maximum value of a set hysteresis temperature interval and turn off when the operating temperature of the functional circuit decreases to a minimum value of the hysteresis temperature interval; the second PMOS transistor is configured to be in an opposite on-off state to the first PMOS transistor.

Optionally, the emitter voltage is configured to decrease when the operating temperature of the functional circuit increases, and is lower than a certain voltage value of the input reference voltage when the operating temperature of the functional circuit increases to a maximum value of a set hysteresis temperature interval; and configured to increase when the operating temperature of the functional circuit decreases and to be higher than the certain voltage value when the operating temperature of the functional circuit decreases to a minimum value of the hysteresis temperature interval;

the first PMOS transistor is specifically configured to turn on when the emitter voltage is lower than the certain voltage value and turn off when the emitter voltage is higher than the certain voltage value; the second PMOS transistor is specifically configured to turn off when the emitter voltage is lower than the certain voltage value and to turn on when the emitter voltage is higher than the certain voltage value.

Optionally, the voltage value of the input reference voltage is set as an average value of a first voltage value and a second voltage value; the first voltage value is a voltage value corresponding to a common connection position of a grid end of the first PMOS transistor and an emitting electrode of the triode when the working temperature of the functional circuit is increased to the maximum value of the hysteresis temperature interval, and the second voltage value is a voltage value corresponding to a common connection position of a drain end of the first PMOS transistor, a first end of the first resistor and a drain end of the first NMOS transistor when the working temperature of the functional circuit is reduced to the minimum value of the hysteresis temperature interval.

Optionally, the voltage value of the output common-mode reference voltage is set as an average value of a third voltage value and a fourth voltage value; the third voltage value is a voltage value corresponding to a common connection point between the first end of the first resistor and the drain end of the first NMOS transistor, or a common connection point between the second end of the second resistor and the drain end of the second NMOS transistor when the operating temperature of the functional circuit increases to the maximum value of the hysteresis temperature interval, and the fourth voltage value is a voltage value corresponding to a common connection point between the first end of the first resistor and the drain end of the first NMOS transistor, or a common connection point between the second end of the second resistor and the drain end of the second NMOS transistor when the operating temperature of the functional circuit decreases to the minimum value of the hysteresis temperature interval.

Optionally, the first signal comprises a first sub-signal and a second sub-signal that are inverted with respect to each other; a first output terminal of the temperature hysteresis circuit is configured to output the first sub-signal, and a second output terminal of the temperature hysteresis circuit is configured to output the second sub-signal;

the Schmitt trigger circuit comprises a first Schmitt trigger and a second Schmitt trigger, and the second signal comprises a third sub-signal and a fourth sub-signal which are mutually inverted; the first Schmitt trigger receives the output of the first output end of the temperature hysteresis circuit, and is specifically configured to perform signal enhancement based on the first sub-signal and output the third sub-signal; the second schmitt trigger receives an output of the second output terminal of the temperature hysteresis circuit, and is specifically configured to perform signal enhancement based on the second sub-signal and output the fourth sub-signal;

and the voltage corresponding to the first sub-signal is in negative correlation with the voltage of the emitter, and the voltage corresponding to the third sub-signal is in negative correlation with the voltage corresponding to the first sub-signal.

Optionally, the temperature hysteresis circuit further comprises a bias circuit for biasing the transistor and the fully differential amplifier; the bias circuit comprises a third PMOS transistor, a fourth PMOS transistor and a fifth PMOS transistor;

the third PMOS transistor receives bias current which is input from the outside and is in direct proportion to the temperature, and the bias current is respectively output to the fourth PMOS transistor connected with the triode and the fifth PMOS transistor connected with the fully differential amplifier, so that the triode and the fully differential amplifier can stably operate.

Optionally, the over-temperature protection circuit further comprises a signal shaping circuit, and the hysteresis enhancement circuit is connected with the functional circuit through the signal shaping circuit;

the signal shaping circuit is configured to shape the second signal, obtain a shaped third signal, and output the third signal to the functional circuit, so that the functional circuit is turned off or turned on according to the third signal.

Optionally, the signal shaping circuit comprises an inverter circuit and a reset-set flip-flop;

the inverter circuit comprises at least one inverter and is configured to shape the second signal for the first time to obtain a fourth signal and output the fourth signal to the reset-set flip-flop;

the reset-set flip-flop is configured to shape the fourth signal a second time to obtain the third signal.

Optionally, the inverter circuit comprises a first inverter and a second inverter;

the fourth signal includes a fifth sub-signal and a sixth sub-signal that are inverted with respect to each other; the first inverter is configured to shape the third sub-signal for the first time to shorten a signal rising edge time and a signal falling edge time, adjust a signal level, obtain the fifth sub-signal, and output the fifth sub-signal to a reset input terminal of the reset-set flip-flop; the second inverter is configured to shape the fourth sub-signal for the first time to shorten a signal rising edge time and a signal falling edge time, adjust a signal level, obtain the sixth sub-signal, and output the sixth sub-signal to a set input terminal of the reset-set flip-flop;

and the voltage corresponding to the fifth sub-signal and the voltage corresponding to the third sub-signal are in negative correlation.

Optionally, the third signal comprises a seventh sub-signal and an eighth sub-signal that are inverted with respect to each other; the reset set flip-flop is configured to shape the fifth sub-signal and the sixth sub-signal for a second time to shorten a signal rising edge time and a signal falling edge time and adjust a level of a signal, and output the seventh sub-signal from a non-Q terminal of the reset set flip-flop to the functional circuit and output the eighth sub-signal from a Q terminal of the reset set flip-flop to the functional circuit;

wherein a voltage corresponding to the seventh sub-signal is positively correlated with a voltage corresponding to the fifth sub-signal.

The embodiment of the invention also discloses a power supply chip, which comprises a functional circuit and the over-temperature protection circuit for performing over-temperature protection on the functional circuit.

The embodiment of the invention has the following advantages:

in the embodiment of the invention, when the working temperature of the functional circuit is increased to a higher temperature and decreased to a lower temperature, the gate end voltage of the input geminate transistor of the fully differential amplifier is greatly changed, so that the located temperature hysteresis circuit outputs different high and low levels, and further the over-temperature protection circuit outputs enable signals with different voltages, thereby triggering the functional circuit to be turned off or turned on. Thus, the over-temperature protection of the functional circuit is realized, and the temperature hysteresis of the over-temperature protection is realized.

Drawings

FIG. 1 is a circuit diagram of an over-temperature protection circuit embodiment of a functional circuit of the present invention;

FIG. 2 is a circuit diagram of a temperature hysteresis circuit of the present invention;

FIG. 3 is a circuit diagram of a common mode feedback amplifier of the present invention;

FIG. 4 is a circuit diagram of another temperature hysteresis circuit of the present invention;

FIG. 5 is a circuit diagram of another common mode feedback amplifier of the present invention;

FIG. 6 is a circuit diagram of a Schmitt trigger in accordance with the present invention;

FIG. 7 is a circuit diagram of an over-temperature protection circuit embodiment of another functional circuit of the present invention;

FIG. 8 is a circuit diagram of an inverter of the present invention;

FIG. 9 is a circuit diagram of a reset-set flip-flop of the present invention;

FIG. 10 is a simulation result of the output of the over-temperature protection circuit of a functional circuit of the present invention;

fig. 11 is a result of simulation of the output of the overheat protection circuit of another functional circuit of the present invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.

Referring to fig. 1, a circuit diagram of an embodiment of an over-temperature protection circuit of a functional circuit according to the present invention is shown, the over-temperature protection circuit may specifically include a temperature hysteresis circuit 10 and a hysteresis enhancement circuit 20, the hysteresis enhancement circuit 20 is connected to at least one functional circuit 30 (only one functional circuit 30 is shown in the figure), and the over-temperature protection circuit 10 is used for over-temperature protection of the functional circuit 30.

Referring to fig. 2, a circuit diagram of a temperature hysteresis circuit 10 according to the present invention is shown, the temperature hysteresis circuit 10 is used for detecting and controlling the temperature of a functional circuit 30, the temperature hysteresis circuit 10 is a comparator structure COMP _0, and includes a transistor 11 and a fully differential amplifier 12, and the comparator structure COMP _0 is a three-input two-output module. The emitter e of the transistor 11 is connected to the fully differential amplifier 12, the transistor 11 is configured to output an emitter voltage to the fully differential amplifier 12, and the fully differential amplifier 12 is configured to output a first signal (corresponding to NET _ 0/1) to the hysteresis enhancement circuit 20 based on the emitter voltage (= NET _ 7) output by the transistor 11, and the input reference voltage (Vi _ ref) and the output common mode reference voltage (Voc _ ref) input from the outside of the over-temperature protection circuit. Where the output common mode reference voltage (Voc _ ref) is used to implement the common mode feedback of the fully differential amplifier 12. The input reference voltage (Vi _ ref) is used for representing a temperature interval, the hysteresis enhancing circuit 20 includes a schmitt trigger circuit, the schmitt trigger circuit includes at least one schmitt trigger (ST _ 0/1), the schmitt trigger circuit is connected with the fully differential amplifier 12, and the schmitt trigger circuit enhances and shapes the first signal (corresponding to NET _ 0/1) and outputs a second signal (corresponding to NET _ 2/3) to the function circuit 30.

Wherein the emitter voltage (= NET _ 7) is negatively correlated with the operating temperature of the functional circuit, the voltage (NET _ 0/1) corresponding to the first signal is negatively correlated with the emitter voltage (= NET _ 7), the voltage (NET _ 2/3) corresponding to the second signal is negatively correlated with the voltage (NET _ 0/1) corresponding to the first signal, and the functional circuit 30 is configured to be turned off or on based on the voltage (NET _ 2/3) corresponding to the second signal that is correlated with the operating temperature.

In the embodiment of the present invention, the temperature hysteresis means that when the operating temperature of the functional circuit is raised to a temperature T1, the over-temperature protection mechanism is triggered to turn off the functional circuit, and then when the operating temperature of the functional circuit is lowered from a high temperature to a temperature T2, the recovery mechanism is triggered to restart the functional circuit. The reason why the over-temperature protection requires the hysteresis function is that if the over-temperature protection does not have the hysteresis function, the functional circuit is turned off once the working temperature of the functional circuit reaches a temperature threshold, the functional circuit is turned on again once the working temperature of the functional circuit is lower than the temperature threshold, and the temperature rapidly rises to the temperature threshold due to power consumption after the functional circuit is turned on again, so that the working state of a chip to which the functional circuit belongs is continuously oscillated, and the chip cannot normally work. If the comparator structure employs an active load amplifier, it is the case as described above, and therefore, if the active load amplifier is employed as the comparator, the condition for generating the hysteresis function cannot be satisfied.

In the embodiment of the present invention, the fully differential amplifier 12 includes the input pair transistors, and the fully differential amplifier 12 can output by comparing the magnitudes of two voltages input to the gate terminals of the input pair transistors, wherein one voltage input to the input pair transistors is the emitter voltage of the transistor 11, which is negatively related to the operating temperature of the functional circuit, and the other voltage input to the input pair transistors is the input reference voltage (Vi _ ref). Because the emitter voltage of the triode 11 is in negative correlation with the working temperature of the functional circuit 30, when the working temperature of the functional circuit 30 is increased, the emitter voltage of the triode 11 is reduced, and when the temperature is increased to a temperature T3, the emitter voltage of the triode 11 is lower than a specific voltage value of the input reference voltage (Vi _ ref), two transistors in the input pair transistor can work in a state that one transistor is conducted and the other transistor is turned off, so that a first signal output by the over-temperature protection circuit based on the state can be used as an enabling signal for triggering the functional circuit 30 to be turned off; after the functional circuit 30 is turned off, as the working temperature of the functional circuit 30 decreases with the passage of time, the emitter voltage of the triode 11 increases, and when the temperature decreases to the temperature T4, the emitter voltage of the triode 11 is higher than another specific voltage value of the input reference voltage (Vi _ ref), then two transistors in the input pair transistor will work in a state that one transistor is turned off, the other transistor is turned on, and the on-off state of the two transistors is opposite to the on-off state of the two transistors in the previous period, different high and low levels are output, so that the first signal output by the over-temperature protection circuit based on this state can be used as an enable signal for triggering the functional circuit 30 to be turned on, the full differential amplifier compares the emitter voltage of the triode input to the input pair transistor with different input reference voltages, so as to realize temperature hysteresis, and referring to the principle of temperature hysteresis, the probability of continuous oscillation of the working state of the chip to which the circuit belongs to is reduced, and the working stability of the chip is ensured.

The specific voltage value corresponds to the operating temperature range of the functional circuit 30, and is related to the circuit bias condition and the process used, so that the specific voltage value is adjustable, and in practical application, the specific voltage value can be set by adjusting the circuit parameters according to the required temperature hysteresis range requirement.

In addition, the schmitt trigger has a certain hysteresis characteristic, so that after the first signal with the hysteresis characteristic is input into the schmitt trigger, the schmitt trigger can enhance the hysteresis effect, thereby expanding the hysteresis temperature interval from [ T4, T3] to [ T2, T1], wherein T2 < T4 < T3 < T1.

In addition, the schmitt trigger may shape the first signal output by the fully-differential amplifier 12. In practical application, the rising edge and the falling edge of the output waveform of the fully differential amplifier 12 change slowly, and the misjudgment of the high and low levels is easily generated in the slow change process, so that the output waveform of the fully differential amplifier 12 can be shaped into the waveform with short rising edge time and short falling edge time through the schmitt trigger, so that the change between the high and low levels is close to sudden change, and the performance of the over-temperature protection circuit is improved.

When the operating temperature of the functional circuit 30 is increased to the maximum value T1 of the required hysteresis temperature interval and decreased to the minimum value T2 of the required hysteresis temperature interval, the input pair transistors of the fully differential amplifier 12 may operate in different states, so that the over-temperature protection circuit outputs enable signals with different voltages, thereby triggering the functional circuit 30 to be turned off or on, and thus, the over-temperature protection of the functional circuit 30 may be implemented based on the temperature hysteresis. In addition, the temperature hysteresis is realized through the fully differential amplifier 12, the first signal is output, and the hysteresis effect of the first signal is enhanced through the Schmitt trigger, so that a larger hysteresis temperature interval can be realized.

In one implementation of the main operational amplifier circuit of the embodiment of the present invention, referring to fig. 2, the fully differential amplifier 12 includes a main operational amplifier circuit and a common mode feedback amplifier A0.

The main operational amplifier circuit comprises a first PMOS Transistor (positive channel Metal-Oxide-Semiconductor Field-Effect Transistor) (PM 3), a second PMOS Transistor (PM 4), a first resistor (R0), a second resistor (R1), a first NMOS Transistor (negative channel Metal-Oxide-Semiconductor Field-Effect Transistor) (NM 0) and a second NMOS Transistor (NM 1). The first NMOS transistor (NM 0) and the first PMOS transistor (PM 3) are respectively connected with the positive end of the common-mode feedback amplifier A0 through a first resistor (R0), and the second NMOS transistor (NM 1) and the second PMOS transistor (PM 4) are respectively connected with the positive end of the common-mode feedback amplifier A0 through a second resistor (R1) so as to send output common-mode voltage to the common-mode feedback amplifier A0; the common mode feedback amplifier A0 stabilizes an output common mode voltage according to an output common mode reference voltage, and outputs the resultant stabilized voltage to the first NMOS transistor (NM 0) and the second NMOS transistor (NM 1), respectively.

Specifically, referring to fig. 2, a gate terminal of the first PMOS transistor (PM 3) and an emitter e of the triode 11 are both connected to the first node (K1), a drain terminal of the first PMOS transistor (PM 3), a first terminal of the first resistor (R0), and a drain terminal of the first NMOS transistor (NM 0) are both connected to the second node (K2), a source terminal of the first PMOS transistor (PM 3) is biased, a source terminal of the first NMOS transistor (NM 0) is grounded, and the second node (K2) is connected to the first output terminal of the temperature hysteresis circuit 10.

A gate terminal of the second PMOS transistor (PM 4) is connected to a first input terminal (IN _ 0) of the temperature hysteresis circuit 10, the first input terminal (IN _ 0) is used for inputting an input reference voltage (Vi _ ref), a drain terminal of the second PMOS transistor (PM 4), a second terminal of the second resistor (R1), and a drain terminal of the second NMOS transistor (NM 1) are connected to a third node (K3), a source terminal of the second PMOS transistor (PM 4) is biased, a source terminal of the second NMOS transistor (NM 1) is grounded, and the third node (K3) is connected to a second output terminal of the temperature hysteresis circuit 10.

The positive end of the common mode feedback amplifier A0, the second end of the first resistor (R0) and the first end of the second resistor (R1) are all connected with the fourth node (K4), the negative end of the common mode feedback amplifier A0 is connected with the second input end (IN _ 1) of the temperature hysteresis circuit 10, the second input end (IN _ 1) is used for inputting and outputting a common mode reference voltage (Voc _ ref), and the output end of the common mode feedback amplifier A0, the gate end of the first NMOS transistor (NM 0) and the gate end of the second NMOS transistor (NM 1) are all connected with the fifth node (K5).

Wherein the first PMOS transistor (PM 3) is configured to: the switching-on is performed when the operating temperature of the functional circuit 30 increases to the maximum value T1 of the hysteresis temperature interval and the switching-off is performed when the operating temperature of the functional circuit 30 decreases to the minimum value T2 of the hysteresis temperature interval.

A second PMOS transistor (PM 4) configured to: opposite to the on-off state of the first PMOS transistor (PM 3).

The PMOS transistors PM3 to PM4 are input pair transistors of the fully differential amplifier 12, and if the gate voltages of the two, i.e., the absolute value of the voltage difference between the NET _7 voltage (emitter voltage) and the input reference voltage (Vi _ ref) input from IN _0, is greater than a certain specific value, one of the PMOS transistors PM3 to PM4 is turned off, and the other is turned on, so that the fully differential amplifier 12 outputs a low level and a high level. The method specifically comprises the following steps: when the working temperature of the functional circuit is increased to a higher temperature, the emitter voltage of the triode 11 is reduced, the absolute value of the differential pressure between the emitter voltage and the input reference voltage (Vi _ ref) input from IN _0 is larger than a certain specific value, the two output signal levels of the fully differential amplifier 12 are turned over, so that the enable signal of the functional circuit is changed, and the functional circuit is closed; when the working temperature of the functional circuit is reduced to a lower temperature, the emitter voltage of the triode 11 is increased, the absolute value of the voltage difference between the emitter voltage and the input reference voltage (Vi _ ref) input from IN _0 is larger than a certain value, the two output signal levels of the fully differential amplifier 12 are inverted again, so that the enable signal of the functional circuit is changed, and the functional circuit is restarted.

In the embodiment of the present invention, the output common-mode voltage of the fully-differential amplifier 12 is usually unstable, and a loop is required to be formed through the common-mode feedback structure to stabilize the dc operating point. Fig. 3 shows a circuit diagram of a common mode feedback amplifier A0 of the present invention, and referring to fig. 3, in an implementation manner of the main operational amplifier circuit of the embodiment of the present invention, the common mode feedback amplifier A0 may include a tenth PMOS transistor (PM 9), an eleventh PMOS transistor (PM 10), a twelfth PMOS transistor (PM 11), a seventh NMOS transistor (NM 6), and an eighth NMOS transistor (NM 7).

A source terminal of the tenth PMOS transistor (PM 9) is connected to a power source terminal (power source voltage is VDD), and a gate terminal of the tenth PMOS transistor (PM 9) is connected to the sixth node (K6).

The drain terminal of the tenth PMOS transistor (PM 9), the source terminal of the eleventh PMOS transistor (PM 10), and the source terminal of the twelfth PMOS transistor (PM 11) are all connected to the fourteenth node (K14).

A drain terminal of the eleventh PMOS transistor (PM 10), a gate terminal of the seventh NMOS transistor (NM 6), and a drain terminal of the seventh NMOS transistor (NM 6) are all connected to the fifteenth node (K15).

A drain terminal of the twelfth PMOS transistor (PM 11), a gate terminal of the eighth NMOS transistor (NM 7), and a drain terminal of the eighth NMOS transistor (NM 7) are all connected to the sixteenth node (K16).

The source end of the seventh NMOS transistor (NM 6) and the source end of the eighth NMOS transistor (NM 7) are both grounded.

In another implementation of the main operational amplifier circuit of the embodiment of the present invention, referring to fig. 4, the fully differential amplifier 12 includes a main operational amplifier circuit and a common mode feedback amplifier A0.

The main operational amplifier circuit comprises a first PMOS transistor (PM 3), a second PMOS transistor (PM 4), a first resistor (R0), a second resistor (R1), a first NMOS transistor (NM 0) and a second NMOS transistor (NM 1). The first NMOS transistor (NM 0) and the first PMOS transistor (PM 3) are respectively connected with the positive end of the common-mode feedback amplifier A0 through a first resistor (R0), the second NMOS transistor (NM 1) and the second PMOS transistor (PM 4) are respectively connected with the positive end of the common-mode feedback amplifier A0 through a second resistor (R1), and output common-mode voltage is sent to the common-mode feedback amplifier A0; the common mode feedback amplifier A0 stabilizes an output common mode voltage according to an output common mode reference voltage, and outputs the resultant stabilized voltage to the first NMOS transistor (NM 0) and the second NMOS transistor (NM 1), respectively.

Specifically, referring to fig. 4, a gate terminal of the first NMOS transistor (NM 0) and an emitter e of the triode 11 are both connected to the first node (K1), a drain terminal of the first NMOS transistor (NM 0), a first terminal of the first resistor (R0), and a drain terminal of the first PMOS transistor (PM 2) are both connected to the second node (K2), a source terminal of the first NMOS transistor (NM 0) is biased, a source terminal of the first PMOS transistor (PM 3) is connected to the power supply VDD, and the second node (K2) is connected to the first output terminal of the temperature hysteresis circuit 10.

A gate terminal of the second NMOS transistor (NM 1) is connected to a first input terminal (IN _ 0) of the temperature hysteresis circuit 10, the first input terminal (IN _ 0) is used for inputting an input reference voltage (Vi _ ref), a drain terminal of the second NMOS transistor (NM 1), a second terminal of the second resistor (R1), and a drain terminal of the second PMOS transistor (PM 4) are connected to a third node (K3), a source terminal of the second NMOS transistor (NM 1) is biased, a source terminal of the second PMOS transistor (PM 4) is connected to a power supply VDD, and the third node (K3) is connected to a second output terminal of the temperature hysteresis circuit 10.

The positive end of the common mode feedback amplifier A0, the second end of the first resistor (R0) and the first end of the second resistor (R1) are connected with a fourth node (K4), the negative end of the common mode feedback amplifier A0 is connected with the second input end (IN _ 1) of the temperature hysteresis circuit 10, the second input end (IN _ 1) is used for inputting and outputting a common mode reference voltage (Voc _ ref), and the output end of the common mode feedback amplifier A0, the grid end of the first PMOS transistor (PM 3) and the grid end of the second PMOS transistor (PM 4) are connected with a fifth node (K5).

Wherein the first NMOS transistor (NM 0) is configured to: the switching off is performed when the operating temperature of the functional circuit 30 increases to the maximum value T1 of the set hysteresis temperature interval and the switching on is performed when the operating temperature of the functional circuit 30 decreases to the minimum value T2 of the hysteresis temperature interval.

The second NMOS transistor (NM 1) is configured to: opposite to the on-off state of the first NMOS transistor (NM 0).

The NMOS transistors NM0 to NM1 are input pair transistors of the fully differential amplifier 12, and if the absolute value of the voltage difference between the two gate voltages, i.e., NET _7 voltage (emitter voltage) and the input reference voltage (Vi _ ref) input from IN _0, is greater than a certain value, one of the NMOS transistors NM0 to NM1 is turned off and the other is turned on, so that the fully differential amplifier 12 outputs a low level and a high level. The method specifically comprises the following steps: when the working temperature of the functional circuit is increased to a higher temperature, the emitter voltage of the triode 11 is reduced, the absolute value of the differential pressure between the emitter voltage and the input reference voltage (Vi _ ref) input from IN _0 is larger than a certain specific value, the two output signal levels of the fully differential amplifier 12 are turned over, so that the enable signal of the functional circuit is changed, and the functional circuit is closed; when the working temperature of the functional circuit is reduced to a lower temperature, the emitter voltage of the triode 11 is increased, the absolute value of the voltage difference between the emitter voltage and the input reference voltage (Vi _ ref) input from IN _0 is larger than a certain value, the two output signal levels of the fully differential amplifier 12 are inverted again, so that the enable signal of the functional circuit is changed, and the functional circuit is restarted.

Referring to fig. 4, the temperature hysteresis circuit 10 further includes a bias circuit 13, and the bias circuit 13 is configured to bias the transistor 11 and the fully differential amplifier 12; the bias circuit 13 includes a third PMOS transistor (PM 0), a fourth PMOS transistor (PM 1), a ninth NMOS transistor (NM 8), a tenth NMOS transistor (NM 9), and an eleventh NMOS transistor (NM 10).

The ninth NMOS transistor (NM 8) receives an externally input bias current proportional to temperature, and is mirrored by a tenth NMOS transistor (NM 9) and a third PMOS transistor (PM 0) and then is output to the fourth PMOS transistor (PM 1) connected to the triode 11 and the eleventh NMOS transistor (NM 10) connected to the fully differential amplifier 12, respectively, so that the triode 11 and the fully differential amplifier 12 operate stably.

Specifically, the source terminal of the third PMOS transistor (PM 0) and the source terminal of the fourth PMOS transistor (PM 1) are both connected to a power supply terminal (power supply voltage is VDD), and the drain terminal of the ninth NMOS transistor (NM 8), the drain terminal of the tenth NMOS transistor (NM 9), and the source terminal of the eleventh NMOS transistor (NM 10) are all connected to ground voltage.

The gate end of the third PMOS transistor (PM 0), the drain end of the third PMOS transistor (PM 0) and the gate end of the fourth PMOS transistor (PM 1) are connected with a sixth node (K6); a third input end (IN _ 2) of the temperature hysteresis circuit 10, a gate end of a ninth NMOS transistor (NM 8), a drain end of the ninth NMOS transistor (NM 8), a gate end of a tenth NMOS transistor (NM 9), and a gate end of an eleventh NMOS transistor (NM 10) are all connected with a seventeenth node (K17), and the third input end (IN _ 2) of the temperature hysteresis circuit is used for inputting a bias current (Iref) IN direct proportion to temperature;

the drain terminal of the fourth PMOS transistor (PM 1) is connected with the first node (K1), and the drain terminal of the eleventh NMOS transistor (NM 10), the source terminal of the first NMOS transistor (NM 0) and the source terminal of the second NMOS transistor (NM 1) are connected with the seventh node (K7).

The node voltage of the seventeenth node (K17) is denoted NET _12.

For the setting of the IN _2 current value, that is, the setting of the bias current (Iref), the magnitude thereof may be enough to satisfy the bias requirement for enabling the transistor 11 and the fully differential amplifier 12 to operate normally.

For another implementation of the main operational amplifier circuit according to the embodiment of the present invention, the output common-mode voltage of the fully-differential amplifier 12 is usually unstable, and a loop is formed through a common-mode feedback structure to stabilize the dc operating point. Referring to fig. 5, which shows a circuit diagram of a common mode feedback amplifier A0 of the present invention, referring to fig. 5, in a specific embodiment, the common mode feedback amplifier A0 may include a tenth PMOS transistor (PM 9), an eleventh PMOS transistor (PM 10), a seventh NMOS transistor (NM 6), an eighth NMOS transistor (NM 7), and a twelfth NMOS transistor (NM 11).

A source terminal of the twelfth NMOS transistor (NM 11) is connected to a power source terminal (power source voltage VDD), and a gate terminal of the twelfth NMOS transistor (NM 11) is connected to the seventeenth node (K17).

The source end of the twelfth NMOS transistor (NM 11), the source end of the seventh NMOS transistor (NM 6) and the source end of the eighth NMOS transistor (NM 7) are all connected with the fourteenth node (K14).

A drain terminal of the seventh NMOS transistor (NM 6), a gate terminal of the tenth PMOS transistor (PM 9), and a drain terminal of the tenth PMOS transistor (PM 9) are all connected to the fifteenth node (K15).

A drain terminal of the eighth NMOS transistor (NM 7), a gate terminal of the eleventh PMOS transistor (PM 10), and a drain terminal of the eleventh PMOS transistor (PM 10) are all connected to the sixteenth node (K16).

The source end of the tenth PMOS transistor (PM 9) and the source end of the eleventh PMOS transistor (PM 10) are both connected with the power supply VDD.

In the embodiment of the present invention, the first resistor (R0) and the second resistor (R1) obtain the output common mode voltage outputted by the fully differential amplifier 12, i.e. NET _8, NET \u8 voltage value and the externally connected output common mode reference voltage (Voc _ ref), as the differential input to the input terminal of the common mode feedback amplifier A0, and output NET _11 voltage value at the negative output terminal of the common mode feedback amplifier A0 to return to the gates of the two load NMOS transistors NM0 and NM1 of the fully differential amplifier 12, thereby completing the closed loop feedback.

As shown IN fig. 1 and 2, since the output common mode reference voltage IN _1 is the output common mode reference voltage (Voc _ ref), the voltage determines the output dc operating point of the fully differential amplifier 12 through the action of the common mode feedback structure, and IN order to make the output swing of the fully differential amplifier 12 as large as possible, the output common mode voltage NET _8 needs to be the voltage average of the high and low levels of the two corresponding output voltages NET _1 and NET _0 when T2 (or T1), which can be obtained through estimation. When the output swing of the fully differential amplifier 12 is as large as possible, the output common mode voltage NET _8 should be equal to the output common mode reference voltage IN _1, so the voltage value of the output common mode reference voltage IN _1 can be set to be the voltage average value of the high and low levels of the two corresponding output voltages NET _1 and NET _0 at T2 (or T1). IN this embodiment, when the operating temperature of the functional circuit 30 is raised to T2 (e.g. 150 ℃), the voltage value of the emitter NET _7 (emitter voltage) of the triode 11 is lower than the set voltage value of the input reference voltage IN _0, and the difference between the two voltages can turn on the PM3 and turn off the PM4, at this time, NET _1 IN the first signal output by the hysteresis circuit 10 is high level and NET _0 is low level, the high level is about the power voltage VDD minus the source-drain voltages of the two PMOS transistors (PM 2, PM 3), the low level is about the drain-source voltage of one NMOS transistor (NM 1), and the output common mode reference voltage is the average of the two voltages. For example: VDD =1.8V, and under the condition of the SMIC180RF process (which is one of the COMS processes), the high level is about 1.3V and the low level is about 0.3V, so the value of the voltage value of the output common mode reference voltage IN _1 should be 0.8V, which is verified to meet the normal operation requirement of the over-temperature protection circuit.

Referring to fig. 2, the transistor 11 is a PNP type transistor (also called PNP type bipolar transistor), the voltage (NET _ 7) (emitter voltage) of the first node (K1) is equal to the emitter voltage of the transistor 11, and the voltage (NET _ 7) (emitter voltage) of the first node (K1) is configured to:

1. decreases when the operating temperature of the functional circuit 30 increases, and falls below a specific voltage value of the input reference voltage (Vi _ ref) when the operating temperature of the functional circuit 30 increases to the maximum value T1 of the hysteresis temperature section that is set, and

2. increases when the operating temperature of the functional circuit 30 decreases, and is higher than a certain voltage value of the input reference voltage (Vi _ ref) when the operating temperature of the functional circuit 30 decreases to the minimum value T2 of the set hysteresis temperature section.

The first PMOS transistor (PM 3) is specifically configured to:

1. is turned on when the voltage (NET _ 7) (emitter voltage) of the first node (K1) is lower than the input reference voltage (Vi _ ref) by a certain voltage value, and

2. is turned off when the voltage (NET _ 7) (emitter voltage) of the first node (K1) is higher than the input reference voltage (Vi _ ref) by a certain voltage value;

the second PMOS transistor (PM 4) is specifically configured to:

1. is turned off when the voltage (NET _ 7) (emitter voltage) of the first node (K1) is lower than the input reference voltage (Vi _ ref) by a certain voltage value, and

2. and is turned on when the voltage (NET _ 7) (emitter voltage) of the first node (K1) is higher than the input reference voltage (Vi _ ref) by a certain voltage value.

In the embodiment of the present invention, the voltage value of the input reference voltage (Vi _ ref) may be set to an average value of the first voltage value (V1) and the second voltage value (V2). The first voltage value (V1) is a voltage value corresponding to the first node (K1) when the operating temperature of the functional circuit 30 increases to a maximum value T1 of the hysteresis temperature interval, and the second voltage value (V2) is a voltage value corresponding to the first node (K1) when the operating temperature of the functional circuit 30 decreases to a minimum value T2 of the hysteresis temperature interval.

In an embodiment of the present invention, the voltage value of the output common mode reference voltage (Voc _ ref) may be set to an average value of the third voltage value (V3) and the fourth voltage value (V4). The third voltage value (V3) is a voltage value corresponding to the second node (K2) or the third node (K3) when the operating temperature of the functional circuit 30 increases to the maximum value T1 of the hysteresis temperature interval, and the fourth voltage value (V4) is a voltage value corresponding to the second node (K2) or the third node (K3) when the operating temperature of the functional circuit 30 decreases to the minimum value T2 of the hysteresis temperature interval.

A current mirror composed of PMOS transistors PM 0-PM 2 applies bias current (Iref) which is directly proportional to temperature and is input from outside to a PNP triode 11 and a fully differential amplifier 12 composed of PMOS transistors PM 3-PM 4, NMOS transistors NM 0-NM 1, resistors R0-R1 and a common mode feedback amplifier A0, so that a first node voltage (NET _ 7) (emitter voltage) with a negative temperature coefficient can be obtained, and the first node voltage (NET _ 7) (emitter voltage) can be reduced along with the rise of temperature.

In an alternative embodiment, the first signal (corresponding to NET _ 0/1) includes a first sub-signal (corresponding to NET _ 1) and a second sub-signal (corresponding to NET _ 0) that are opposite in phase, the first output terminal of the temperature hysteresis circuit 10 is configured to output the first sub-signal, and the second output terminal of the temperature hysteresis circuit 10 is configured to output the second sub-signal.

Accordingly, the schmitt trigger circuit may include a first schmitt trigger (ST _ 1) and a second schmitt trigger (ST _ 0), the second signal (corresponding to a NET _ 2/3) includes a third sub-signal (corresponding to a NET _ 3) and a fourth sub-signal (corresponding to a NET _ 2) that are opposite to each other, the first schmitt trigger (ST _ 1) receives an output of the first output terminal of the temperature hysteresis circuit 10, and the first schmitt trigger (ST _ 1) is specifically configured to: and performing signal enhancement based on the first sub-signal and outputting a third sub-signal.

A second schmitt trigger (ST _ 0) receives an output of the second output terminal of the temperature hysteresis circuit, the second schmitt trigger (ST _ 0) being specifically configured to: and performing signal enhancement based on the second sub-signal and outputting a fourth sub-signal.

The voltage (NET _ 1) corresponding to the first sub-signal is in negative correlation with the emitter voltage (NET _ 7), and the voltage (NET _ 3) corresponding to the third sub-signal is in negative correlation with the voltage (NET _ 1) corresponding to the first sub-signal.

Fig. 6 shows a circuit diagram of a schmitt trigger of the present invention, and referring to fig. 6, in a specific embodiment, the schmitt trigger may include a sixth PMOS transistor (PM 5), a seventh PMOS transistor (PM 6), and an eighth PMOS transistor (PM 7), a third NMOS transistor (NM 2), a fourth NMOS transistor (NM 3), and a fifth NMOS transistor (NM 4).

An input end (IN _ 3) of the Schmitt trigger, a gate end of the sixth PMOS transistor (PM 5), a gate end of the seventh PMOS transistor (PM 6), a gate end of the third NMOS transistor (NM 2) and a gate end of the fourth NMOS transistor (NM 3) are all connected with the eighth node (K8).

The source end of the sixth PMOS transistor (PM 5) is connected with the power supply end (the power supply voltage is VDD), the drain end of the sixth PMOS transistor (PM 5), the source end of the seventh PMOS transistor (PM 6) and the source end of the eighth PMOS transistor (PM 7) are connected with the ninth node (K9), and the drain end of the eighth PMOS transistor (PM 7) is grounded.

The drain terminal of the seventh PMOS transistor (PM 6), the gate terminal of the eighth PMOS transistor (PM 7), the drain terminal of the third NMOS transistor (NM 2), the gate terminal of the fifth NMOS transistor (NM 4) and the output terminal (OUT _ 2) of the Schmitt trigger are all connected with the tenth node (K10).

The source end of the third NMOS transistor (NM 2), the drain end of the fourth NMOS transistor (NM 3) and the source end of the fifth NMOS transistor (NM 4) are all connected with an eleventh node (K11), the source end of the fourth NMOS transistor (NM 3) is grounded, and the drain end of the fifth NMOS transistor (NM 4) is connected with a power supply end (the power supply voltage is VDD).

Based on the circuit description above, in the embodiment of the present invention, the voltage (NET _ 7) (emitter voltage) of the first node (K1) is equal to the emitter voltage of the transistor 11, the transistor 11 is used as a core device for temperature detection, and the emitter voltage of the transistor 11 has a negative temperature coefficient, i.e. it decreases with the increase of temperature, so that the emitter voltage reflects the operating temperature of the circuit to be detected and is used as one input voltage of the post-stage fully differential amplifier 12, and the emitter voltage and another external, already set input reference voltage (Vi _ ref) are used as two inputs of the fully differential amplifier.

For the setting of the voltage value of IN _0, i.e. the setting of the input reference voltage (Vi _ ref), assuming that the over-temperature protection circuit needs to shut down the functional circuit when the temperature is higher than 150 ℃ (T1) and restart the functional circuit when the temperature is reduced to 130 ℃ (T2), the voltage value of the input reference voltage (Vi _ ref) can be: average value of NET _7 voltage value at 150 ℃ and NET _7 voltage value at 130 ℃. The reason for this setting is that: when the working temperature of the functional circuit reaches 150 ℃, the voltage value of NET _7 corresponding to the emitter of the triode 11 is lower than the set input reference voltage (Vi _ ref), and due to the conduction characteristic of the PMOS transistor, the difference value of the two can enable the first PMOS transistor PM3 to be conducted (PM 3 works in a linear area) and the second PMOS transistor PM4 to be turned off (PM 4 works in a cut-off area), at the moment, NET _1 is high level and NET _0 is low level, after the two output levels are used as a fully differential amplifier 12 to be output, the two output levels can be used as enabling signals to turn off the functional circuit through further processing of a rear-stage module, and one-time over-temperature protection is finished; similarly, when the operating temperature of the functional circuit is reduced to 130 ℃, the voltage value of NET _7 corresponding to the emitter of the triode 11 is higher than the set input reference voltage (Vi _ ref), and due to the conduction characteristics of the PMOS transistors, the difference between the two can make the first PMOS transistor PM3 turn off (PM 3 works in the cut-off region) and the second PMOS transistor PM4 turn on (PM 4 works in the linear region), at this time, NET _1 is low and NET _0 is high, after the two output levels are output as the fully differential amplifier 12, the two output levels can be used as enable signals to restart the functional circuit through further processing of the post-stage module, that is, the functional circuit is restarted once under the control of the fully differential amplifier.

It can be seen that the fully differential amplifier 12 can implement a certain hysteresis function by switching the operating intervals of the input pair transistors, in other words, only when the voltage value of the emitter NET _7 of the transistor 11 representing the operating temperature of the functional circuit is higher or lower than the input reference voltage (Vi _ ref) for a certain interval, the operating intervals of the input pair transistors are interchanged, which further causes the high and low levels of the two output voltages NET _1 and NET _0 to be interchanged. Intuitively, this voltage interval reflects the temperature interval, which achieves the hysteresis function.

IN practical application, the voltage value of IN _0 as the input reference voltage of the fully differential amplifier is changed along with the change of the requirement of the hysteresis temperature interval of the protected circuit, so that the adjustable hysteresis temperature interval is realized.

Referring to fig. 2, the temperature hysteresis circuit 10 further includes a bias circuit 13, and the bias circuit 13 is configured to bias the transistor 11 and the fully differential amplifier 12; the bias circuit 13 includes a third PMOS transistor (PM 0), a fourth PMOS transistor (PM 1), and a fifth PMOS transistor (PM 2).

The third PMOS transistor (PM 0) receives an externally input bias current proportional to temperature, and outputs the bias current to the fourth PMOS transistor (PM 1) connected to the triode 11 and the fifth PMOS transistor (PM 2) connected to the fully differential amplifier 12, respectively, so that the triode 11 and the fully differential amplifier 12 operate stably.

Specifically, the source terminal of the third PMOS transistor (PM 0), the source terminal of the fourth PMOS transistor (PM 1), and the source terminal of the fifth PMOS transistor (PM 2) are all connected to a power supply terminal (power supply voltage is VDD).

A third input end (IN _ 2) of the temperature hysteresis circuit 10, a gate end of the third PMOS transistor (PM 0), a gate end of the fourth PMOS transistor (PM 1), and a gate end of the fifth PMOS transistor (PM 2) are all connected to a sixth node (K6), and the third input end (IN _ 2) of the temperature hysteresis circuit is used for inputting a bias current (Iref) proportional to temperature;

a drain terminal of the third PMOS transistor (PM 0) is connected to the third input terminal (IN _ 2) of the temperature hysteresis circuit 10, a drain terminal of the fourth PMOS transistor (PM 1) is connected to the first node (K1), and drain terminals of the fifth PMOS transistor (PM 2), the first PMOS transistor (PM 3), and the second PMOS transistor (PM 4) are connected to the seventh node (K7).

The node voltage of the sixth node (K6) is NET _6.

For the setting of the current value of IN _2, that is, the setting of the bias current (Iref), the magnitude thereof may meet the bias requirement for enabling the transistor 11 and the fully differential amplifier 12 to normally operate.

Fig. 7 shows a circuit diagram of an embodiment of the over-temperature protection circuit of another functional circuit of the present invention, and referring to fig. 7, optionally, the over-temperature protection circuit further includes a signal shaping circuit 40, and the hysteresis enhancing circuit 20 may be connected to the functional circuit 30 through the signal shaping circuit 40.

The signal shaping circuit 40 is configured to shape the second signal (corresponding to NET _ 2/3) to obtain a shaped third signal (the signal output from the OUT _0/1 terminal), and output the third signal to the functional circuit 30, so that the functional circuit 30 is turned off or turned on according to the third signal.

In an alternative embodiment, referring to fig. 7, the signal shaping circuit 40 may specifically include an inverter circuit and a reset-set flip-flop.

The inverter circuit comprises at least one inverter (INV _ 0/1), and the inverter circuit is configured to shape the second signal (corresponding to a voltage NET _ 2/3) for the first time, obtain a fourth signal (corresponding to a voltage NET _ 4/5), and output the fourth signal to the reset-set flip-flop.

The reset set flip-flop (SRT _ 0) is configured to shape the fourth signal a second time to obtain a third signal (the signal output from the OUT _0/1 terminal).

In the embodiment of the present invention, the signal shaping circuit 40 may further shorten the rising edge time and the falling edge time of the second signal, so that the rising edge and the falling edge of the input second signal become steeper, and the probability of misjudgment of high and low levels is reduced. In addition, the signal shaping circuit 40 may also perform level shift on the second signal, that is, the low level of the second signal may be adjusted to be high, and the high level of the second signal may be adjusted to be low, so that the enable signal output by the over-temperature protection circuit is adapted to the protected functional circuit.

In an alternative embodiment, referring to fig. 7, the inverter circuit may specifically include a first inverter (INV _ 1) and a second inverter (INV _ 0), an input end of the first inverter (INV _ 1) is connected to an output end of the first schmitt trigger (ST _ 1), an input end of the second inverter (INV _ 0) is connected to an output end of the second schmitt trigger (ST _ 0), an output end of the first inverter (INV _ 1) is connected to a reset input end (R end) of the reset set trigger (SRT _ 0), and an output end of the second inverter (INV _ 0) is connected to a set input end (S end) of the reset set trigger (SRT _ 0).

The fourth signal (corresponding to a voltage NET _ 4/5) includes a fifth sub-signal (corresponding to a voltage NET _ 5) and a sixth sub-signal (corresponding to a voltage NET _ 4) that are inverted with respect to each other. Accordingly, the first inverter (INV _ 1) is configured to shape the third sub-signal (corresponding to the voltage NET _ 3) for the first time, to determine a value to shorten the signal rising edge time and the signal falling edge time, and to adjust the level of the signal, to obtain the fifth sub-signal (corresponding to the voltage NET _ 5), and to output the fifth sub-signal to the reset input terminal (terminal R) of the reset set flip-flop (SRT _ 0).

The second inverter (INV _ 0) is configured to shape the fourth sub-signal (corresponding to the voltage NET _ 2) for the first time, to shorten the signal rising edge time and the signal falling edge time, and to adjust the signal level high and low, to obtain the sixth sub-signal (corresponding to the voltage NET _ 4), and to output the sixth sub-signal to the set input terminal (S terminal) of the reset-set flip-flop (SRT _ 0).

The voltage (NET _ 5) corresponding to the fifth sub-signal and the voltage (NET _ 3) corresponding to the third sub-signal are in negative correlation.

Fig. 8 shows a circuit diagram of an inverter of the present invention, and referring to fig. 8, in a specific embodiment, the inverter may include a ninth PMOS transistor (PM 8) and a sixth NMOS transistor (NM 5).

A gate terminal of the ninth PMOS transistor (PM 8), a gate terminal of the sixth NMOS transistor (NM 5), and an input terminal (IN _ 4) of the inverter are all connected to the twelfth node (K12).

The source terminal of the ninth PMOS transistor (PM 8) is connected to the power supply terminal (power supply voltage VDD), and the source terminal of the sixth NMOS transistor (NM 5) is grounded.

A drain terminal of the ninth PMOS transistor (PM 8), a drain terminal of the sixth NMOS transistor (NM 5), and an output terminal (OUT _ 3) of the inverter are all connected to the thirteenth node (K13).

Further, the third signal (the signal output from the OUT _0/1 terminal) may include a seventh sub-signal (the signal output from the OUT _1 terminal) and an eighth sub-signal (the signal output from the OUT _0 terminal) that are inverted with respect to each other. Accordingly, the reset set flip-flop (SRT _ 0) is configured to perform second shaping on the fifth sub-signal (corresponding to the voltage NET _ 5) and the sixth sub-signal (corresponding to the voltage NET _ 4) to shorten the signal rising edge time and the signal falling edge time and adjust the level of the signal, and output the seventh sub-signal (signal output from the OUT _1 terminal) from the non-Q terminal (denoted by QN in the drawing) of the reset set flip-flop (SRT _ 0) to the functional circuit 30, and output the eighth sub-signal (signal output from the OUT _0 terminal) from the Q terminal (denoted by Q in the drawing) of the reset set flip-flop to the functional circuit 30.

The voltage corresponding to the seventh sub-signal (the signal output from the OUT _1 terminal) is positively correlated with the voltage (NET _ 5) corresponding to the fifth sub-signal.

In the embodiment of the present invention, the substrate of each PMOS transistor is connected to a power supply terminal (power supply voltage is VDD), and the substrate of each NMOS transistor is grounded.

Fig. 9 shows a circuit diagram of a reset-set flip-flop of the present invention, and referring to fig. 9, in a specific embodiment, the reset-set flip-flop (SRT _ 0) includes a first NAND gate device (NAND 1) and a second NAND gate device (NAND 0).

The first input end of the first NAND gate device (NAND 1) is the reset input end (R end) of the reset set trigger (SRT _ 0), the first input end of the second NAND gate device (NAND 1) is the set input end (S end) of the reset set trigger, the output end of the first NAND gate device is the non-Q end of the reset set trigger (SRT _ 0), and the output end of the second NAND gate device (NAND 1) is the Q end of the reset set trigger (SRT _ 0).

The second input end of the first NAND gate device (NAND 1) is connected with the output end of the second NAND gate device (NAND 1), and the second input end of the second NAND gate device (NAND 1) is connected with the output end of the first NAND gate device (NAND 1).

In the embodiment of the invention, the inverter and the reset set trigger in the signal shaping circuit can carry out double shaping and double level shifting on the second signal, so that the enabling signal output by the over-temperature protection circuit has clear high and low level distinction, and further the control on the functional circuit is more accurate.

As shown in fig. 7, in the embodiment of the present invention, the over-temperature protection circuit composed of the temperature hysteresis circuit 10, the hysteresis enhancement circuit 20 and the signal shaping circuit 40 may be a small module of all modules of the power chip, and the module is configured to output an enable signal according to a change in temperature, where the output enable signal determines whether other modules (i.e., the functional circuit 30) in the power chip are working normally, and the third signal (the signal output from the OUT _0/1 terminal) is used as the enable signal.

For example, in one embodiment, if the operating temperature of the functional circuit 30 is higher than 150 ℃, the output of the OUT _0 terminal changes from high level to low level, and all the modules in the power chip that use the output signal of the OUT _0 terminal as the enable signal are turned off, so that the power chip does not continue to operate at an excessively high temperature; when the operating temperature of the functional circuit 30 falls back to 130 ℃ due to heat dissipation of the chip, the output of the OUT _0 terminal changes to high level again, and all the modules in the power chip, which use the output signal of the OUT _0 terminal as an enable signal, are turned on, so that the power chip enters a normal operating state again.

Correspondingly, if the working temperature of the functional circuit is higher than 150 ℃, the output of the OUT _1 end is changed from low level to high level, and all modules in the power chip which take the output signal of the OUT _1 end as an enabling signal are closed, so that the power chip can not continuously work at the overhigh temperature; when the working temperature of the functional circuit falls back to 130 ℃ due to the heat dissipation of the chip, the output of the OUT _1 end is changed into low level again, and all modules in the power supply chip, which take the output signal of the OUT _1 end as an enabling signal, are started, so that the power supply chip enters a normal working state again.

IN summary, when the operating temperature of the functional circuit increases, the voltage of the emitter voltage NET _7 decreases, and the temperature increases to T1, so that the voltage of NET _7 is lower than the specific voltage value of the input reference voltage (IN _0 voltage), the first PMOS transistor PM3 of the fully differential amplifier IN the temperature hysteresis circuit is turned on, the second PMOS transistor PM4 is turned off, NET _0 IN the first signal output by the temperature hysteresis circuit is at a low level, NET _2 IN the second signal output by the hysteresis enhancement circuit is at a high level, NET _4 IN the fourth signal output by the inverter circuit is at a low level, and the OUT _0 end IN the third signal output by the signal shaping circuit outputs a low level, thereby controlling the functional circuit to turn off.

When the working temperature of the functional circuit is reduced, the voltage of an emitter voltage NET _7 is increased, the temperature is reduced to T2, so that the voltage of NET _7 is higher than the specific voltage value of an input reference voltage (IN _0 voltage), a first PMOS transistor PM3 of a fully differential amplifier IN the temperature hysteresis circuit is turned off, a second PMOS transistor PM4 is turned on, NET _0 IN a first signal output by the temperature hysteresis circuit is IN a high level, NET _2 IN a second signal output by the hysteresis enhancement circuit is IN a low level, NET _4 IN a fourth signal output by the inverter circuit is IN a high level, an OUT _0 end IN a third signal output by the signal shaping circuit outputs a high level, and the functional circuit is controlled to be restarted.

Fig. 10 and 11 exemplarily show the output simulation result of the over-temperature protection circuit of one functional circuit of the present invention, which can realize the hysteresis temperature interval of 131-148.5 ℃. Fig. 10 shows a case where the operating temperature of the functional circuit is increased from 120 ℃ to 160 ℃, a solid line represents an output voltage of the OUT _0 terminal of the over-temperature protection circuit, and a dotted line represents an output voltage of the OUT _1 terminal of the over-temperature protection circuit, as can be seen from fig. 9, when the operating temperature of the functional circuit is increased to about 148.5 ℃, the over-temperature protection circuit can turn off the functional circuit; fig. 11 shows the case where the operating temperature of the functional circuit is reduced from 160 ℃ to 120 ℃, the solid line is the output voltage of the OUT _0 terminal of the over-temperature protection circuit, and the dotted line is the output voltage of the OUT _1 terminal of the over-temperature protection circuit, as can be seen from fig. 10, when the operating temperature of the functional circuit is reduced to about 131 ℃, the over-temperature protection circuit can restart the functional circuit to operate normally.

In the embodiment of the invention, when the working temperature of the functional circuit is increased to a higher temperature and is reduced to a lower temperature, the input pair transistors of the fully differential amplifier can work in different states, so that the over-temperature protection circuit outputs enable signals with different voltages to trigger the functional circuit to be turned off or turned on, thus the over-temperature protection of the functional circuit is realized, and the temperature hysteresis of the over-temperature protection is realized. In addition, the embodiment of the invention can realize temperature hysteresis through the fully differential amplifier, and then enhance the hysteresis effect through the Schmitt trigger, thereby realizing a larger hysteresis temperature interval, and the hysteresis temperature interval is adjustable.

The embodiment of the invention also provides a power supply chip, which comprises a functional circuit and the over-temperature protection circuit for performing over-temperature protection on the functional circuit.

In the embodiment of the invention, when the working temperature of the functional circuit is increased to a higher temperature and decreased to a lower temperature, the gate end voltage of the input geminate transistor of the fully differential amplifier is greatly changed, so that the located temperature hysteresis circuit outputs different high and low levels, and further the over-temperature protection circuit outputs enable signals with different voltages, thereby triggering the functional circuit to be turned off or turned on. Therefore, the over-temperature protection of the functional circuit is realized, and the temperature delay of the over-temperature protection is realized.

The over-temperature protection circuit of a functional circuit and the power chip provided by the invention are introduced in detail, and a specific example is applied in the text to explain the principle and the implementation of the invention, and the description of the above embodiment is only used to help understand the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims

1. The over-temperature protection circuit of the functional circuit is characterized by comprising a temperature hysteresis circuit and a hysteresis enhancement circuit, wherein the hysteresis enhancement circuit is respectively connected with at least one functional circuit;

the temperature hysteresis circuit is used for detecting and controlling the temperature of the functional circuit and comprises a triode and a fully differential amplifier; the emitter electrode of the triode outputs an emitter voltage to the fully differential amplifier; the fully differential amplifier outputs a first signal to the hysteresis enhancement circuit based on the emitter voltage, and an input reference voltage and an output common-mode reference voltage which are input from the outside;

the hysteresis enhancing circuit comprises a Schmitt trigger circuit, and the Schmitt trigger circuit enhances and shapes the first signal and outputs a second signal to the functional circuit;

2. The over-temperature protection circuit of a functional circuit according to claim 1, wherein the fully differential amplifier comprises a main operational amplifier circuit and a common mode feedback amplifier;

3. The over-temperature protection circuit of claim 2, wherein the method further comprises:

the first PMOS transistor is configured to be turned on when the operating temperature of the functional circuit rises to the maximum value of a set hysteresis temperature interval and turned off when the operating temperature of the functional circuit falls to the minimum value of the hysteresis temperature interval; the second PMOS transistor is configured to be in an opposite on-off state to the first PMOS transistor.

4. The over-temperature protection circuit of the functional circuit according to claim 3, wherein the emitter voltage is configured to decrease when the operating temperature of the functional circuit increases and to be lower than a specific voltage value of the input reference voltage when the operating temperature of the functional circuit increases to a maximum value of a set hysteresis temperature interval; and configured to increase when the operating temperature of the functional circuit decreases and to be higher than the certain voltage value when the operating temperature of the functional circuit decreases to a minimum value of the hysteresis temperature interval;

5. The over-temperature protection circuit of the functional circuit according to claim 4, wherein the voltage value of the input reference voltage is set to an average value of the first voltage value and the second voltage value; the first voltage value is a voltage value corresponding to the gate terminal of the first PMOS transistor when the operating temperature of the functional circuit is increased to the maximum value of the hysteresis temperature interval, and the second voltage value is a voltage value corresponding to the drain terminal of the first PMOS transistor when the operating temperature of the functional circuit is decreased to the minimum value of the hysteresis temperature interval.

6. The over-temperature protection circuit of the functional circuit according to claim 4, wherein the voltage value of the output common mode reference voltage is set to an average value of a third voltage value and a fourth voltage value; the third voltage value is a voltage value corresponding to the drain terminal of the first NMOS transistor when the operating temperature of the functional circuit increases to the maximum value of the hysteresis temperature interval, and the fourth voltage value is a voltage value corresponding to the drain terminal of the first NMOS transistor when the operating temperature of the functional circuit decreases to the minimum value of the hysteresis temperature interval.

7. The excess temperature protection circuit of the functional circuit according to claim 2, wherein the first signal includes a first sub-signal and a second sub-signal that are inverted with respect to each other; a first output terminal of the temperature hysteresis circuit is configured to output the first sub-signal, and a second output terminal of the temperature hysteresis circuit is configured to output the second sub-signal;

the Schmitt trigger circuit comprises a first Schmitt trigger and a second Schmitt trigger, and the second signal comprises a third sub-signal and a fourth sub-signal which are opposite in phase to each other; the first schmitt trigger receives an output of the first output end of the temperature hysteresis circuit, and is specifically configured to perform signal enhancement based on the first sub-signal and output the third sub-signal; the second schmitt trigger receives an output of the second output terminal of the temperature hysteresis circuit, and is specifically configured to perform signal enhancement based on the second sub-signal and output the fourth sub-signal;

8. The over-temperature protection circuit of the functional circuit according to claim 2, wherein the temperature hysteresis circuit further comprises a bias circuit for biasing the transistor and the fully differential amplifier; the bias circuit comprises a third PMOS transistor, a fourth PMOS transistor and a fifth PMOS transistor;

the third PMOS transistor receives bias current input from the outside and respectively outputs the bias current to the fourth PMOS transistor connected with the triode and the fifth PMOS transistor connected with the fully differential amplifier, so that the triode and the fully differential amplifier can stably operate.

9. The over-temperature protection circuit of the functional circuit according to claim 1, wherein the over-temperature protection circuit further comprises a signal shaping circuit, and the hysteresis enhancement circuit is connected with the functional circuit through the signal shaping circuit;

10. The over-temperature protection circuit of the functional circuit according to claim 9, wherein the signal shaping circuit includes an inverter circuit and a reset-set flip-flop;

11. The over-temperature protection circuit of a functional circuit according to claim 10, wherein the inverter circuit comprises a first inverter and a second inverter;

12. The excess temperature protection circuit of the functional circuit according to claim 11, wherein the third signal includes a seventh sub-signal and an eighth sub-signal that are inverted with respect to each other; the reset set flip-flop is configured to shape the fifth sub-signal and the sixth sub-signal for a second time to shorten a signal rising edge time and a signal falling edge time and adjust a level of a signal, and output the seventh sub-signal from a non-Q terminal of the reset set flip-flop to the functional circuit and output the eighth sub-signal from a Q terminal of the reset set flip-flop to the functional circuit;

13. A power supply chip characterized in that it comprises a functional circuit and an over-temperature protection circuit for over-temperature protection of the functional circuit as claimed in any one of claims 1 to 12.